TWI824516B - Resistive random-access memory devices with multicomponent electrodes and discontinuous interface layers - Google Patents

Abstract

The present invention relates to a resistive random access memory (RRAM) device. a RRAM The device may include a first electrode, a first interface layer formed on the first electrode; a switching oxide layer formed on the first interface layer; and a second electrode formed on the switching oxide layer . The switching oxide layer includes a transition metal oxide. The first interface layer includes a first discontinuous film of a first material that has greater chemical stability than the transition metal oxide. The RRAM device may further include a second interface layer between the switching oxide layer and the second electrode. The second interface layer includes a second discontinuous film of a second material that has greater chemical stability than the transition metal oxide. The second electrode may include a plurality of electrode assemblies including an alloy, a first layer of a first metallic material, and/or a second layer of a second metallic material.

Description

Resistive random access with multi-component electrodes and discontinuous interface layer storage device

This application is filed on May 12, 2021, and is called U.S. Patent Application No. 17/319,057, titled "Resistive Random Access Memory Device with Multi-Component Electrodes", filed on May 12, 2021, titled " U.S. Patent Application No. 17/319.068 "Resistive Random Access Memory Device with Multi-Component Electrodes" was filed on November 15, 2021, and is titled "Resistive Random Access Memory Device with Multi-Component Electrodes and Discontinuous Interface Layer" Storage Device," U.S. Patent Application No. 17/454,914, each of which is hereby incorporated by reference in its entirety.

Embodiments of the present invention relate to a resistive random access memory (RRAM) device, and more particularly to an RRAM device having multi-component electrodes and a discontinuous interface layer.

A resistive random access memory (RRAM) device is a two-terminal passive component with adjustable and nonvolatile resistance. By applying appropriate programmable signals to the RRAM device, the RRAM device can be switched between a high resistance state (HRS) and a low resistance state (LRS). Perform electrical switching. RRAM devices can be used to form crossbar arrays for applications in in-memory computing, non-volatile solid-state storage, image processing, neural networks, etc.

The following is a simplified summary of the invention intended to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. This summary is not intended to identify key or critical elements of the invention or to delineate any scope of particular implementations of the invention or the scope of the patent claims. The sole purpose of this Summary is to simplify the presentation of some concepts of the invention in the language of the more detailed description that is subsequently presented.

In one aspect of the invention, a resistive random access memory (RRAM) device may include: a first electrode; a first interface layer fabricated on the first electrode, wherein the first interface layer includes a first material of a first electrode. a discontinuous thin film; a switching oxide layer fabricated on the first interface layer, wherein the switching oxide layer includes at least one transition metal oxide, and the first material is smaller than the at least one transition metal The oxide has stronger chemical stability; the second electrode is fabricated on the switching oxide layer.

2.0和y

2.5。 In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, where x

2.0 and y

2.5.

In some embodiments, the first material includes at least one of Al ₂ O ₃ , MgO, Y ₂ O ₃ or La ₂ O ₃ .

In some embodiments, the first discontinuous film of the first material includes one or more first pores, and wherein the switching oxide layer contacts the first pore through at least one of the first pores. One or more parts of an electrode.

In some embodiments, the thickness of the first interface layer is between 0.2 nanometer and 1 nanometer.

In some embodiments, the second electrode includes a tantalum alloy. The tantalum alloy further includes at least one of hafnium, molybdenum, tungsten, niobium or zirconium. The tantalum alloys include binary alloys composed of tantalum, ternary alloys composed of tantalum, quaternary alloys composed of tantalum, quintuple alloys composed of tantalum, six-element alloys composed of tantalum or tantalum alloys. At least one of high order alloys.

In some embodiments, the RRAM device includes a second interface layer between the switching oxide layer and the second electrode, wherein the second interface layer includes a second discontinuous film of a second material, Wherein the second material has stronger chemical stability than the at least one transition metal oxide. The second electrode contacts at least a portion of the switching oxide layer.

In some embodiments, the second material includes at least one of Al ₂ O ₃ , MgO, Y ₂ O ₃ or La ₂ O ₃ .

In some embodiments, the thickness of the second interface layer is between 0.2 nanometer and 1 nanometer.

In some embodiments, a first layer includes a first metallic material; a second layer includes a second metallic material, wherein the first layer is fabricated on the switching oxide layer and the second layer is fabricated on the switching oxide layer. The first layer includes a first metallic material. The first material has stronger chemical stability than the oxide of the first metal material, and the oxide of the first metal material has stronger chemical stability than the at least one transition metal oxide. . The RRAM device of claim 14, wherein the first metal material in the second electrode includes at least one of Ti, Hf or Zr. In some embodiments, the second metallic material in the second electrode includes tantalum.

In some embodiments, the first layer including the first metallic material has a thickness between 0.2 nanometers and 5 nanometers.

One or more aspects of the invention provide a method of manufacturing an RRAM device. The method includes fabricating a first interface layer including a first discontinuous film of a first material on a first electrode of the RRAM device. The method also includes fabricating a switching oxide layer including at least one transition metal oxide on the first interface layer, wherein the first material has a stronger chemical resistance than the at least one transition metal oxide. Stability. The method also includes fabricating a second interface layer comprising a second discontinuous film of a second material on the switching oxide layer, wherein the second material has a stronger oxidation potential than the at least one transition metal oxide. chemical stability. The method further includes fabricating a second electrode on the second interface layer.

In some embodiments, the first discontinuous film of the first material includes at least one pore, and fabricating the switching oxide layer including at least one transition metal oxide at the first interface includes at least A pore deposits the at least one transition metal oxide on the first electrode. Fabricating the first interface layer including a first discontinuous film of a first material on a first electrode of the RRAM device includes depositing the first material on the first electrode to form the first discontinuous film. film.

According to one or more aspects of the present invention, an RRAM device may include a first electrode, a first interface layer fabricated on the first electrode, a switching oxide layer fabricated on the first interface layer, a second interface layer on the switching oxide layer and a second electrode manufactured on the switching oxide layer.

According to one or more aspects of the present invention, an RRAM device may include a first electrode, a switching oxide layer fabricated on the first electrode, an interface layer fabricated on the switching oxide layer, and an interface layer fabricated on the interface. on the second electrode. The switching oxide layer may include at least one transition metal oxide. The interface layer may include a discontinuous film of a material that is more chemically stable than the at least one transition metal oxide.

100:cross circuit

111a, 111b, 111i, 111n: row line

113a, 113b, 113j, 113m: column lines

120a, 120b, 120ij, 120z: cross-point devices

200: Crosspoint device

201:RRAM device

203:Transistor

211:Bit line

213:Select line

215: word line

300a, 300b, 300c: RRAM devices

310:Substrate

320: first electrode

330: Switch oxide layer

340: Second electrode

335a: Conductive channel

335b: Interrupt conductive path

400a, 400b, 400c, 400d, 400e: semiconductor devices

410:Substrate

420: first electrode

422:Interface layer

422a: Discontinuous film

424:pore

430: Switch oxide layer

440: Second electrode

435a: Conductive channel

500a, 500b, 500c, 500d: semiconductor devices

532: Second interface layer

532a: Discontinuous film

534:pore

535a: Conductive channel

535b: Interrupt conductive path

540: Second electrode

600a, 600b, 600c, 600d: semiconductor devices

630: Switch oxide layer

632:Interface layer

632a: Discontinuous film

634:pore

635a: Conductive channel

635b: Interrupt conductive path

640: Second electrode

700: Example of method for fabricating second electrode of RRAM device

710:First floor

720:Second floor

1000: Examples of methods of fabricating RRAM devices

1010, 1020, 1030, 1040: steps

1100: Examples of methods of fabricating RRAM devices

1110, 1120, 1130, 1140, 1150: steps

1200: Examples of methods of fabricating RRAM devices

1210, 1220, 1230, 1240: steps

1300: Example of method of fabricating top electrode of RRAM device

1310, 1320: steps

The present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the invention. However, the drawings should not be used to limit the invention to specific embodiments, but only for explanation and understanding.

Figure 1 is a schematic diagram of an exemplary crossover circuit shown in accordance with some embodiments of the present invention.

Figure 2 is a schematic diagram of an exemplary cross-point device shown in accordance with some embodiments of the present invention.

3A-3C, 4A-4F, 5A-5D, and 6A-6D are cross-sectional views of exemplary RRAM devices shown in accordance with some embodiments of the invention.

Figure 7 is a cross-sectional view of a top electrode in an RRAM device according to some embodiments of the present invention.

Figure 8 is an Ellingham plot representing the chemical stability of metal oxides in accordance with some embodiments of the present invention.

Figure 9 is a tantalum-titanium (Ta-Ti) binary phase diagram according to some embodiments of the present invention.

Figure 10 is a flowchart of a method of manufacturing an RRAM device according to some embodiments of the present invention.

Figure 11 is a flowchart of a method of manufacturing an RRAM device according to some embodiments of the present invention.

Figure 12 is a flowchart of a method of manufacturing an RRAM device according to some embodiments of the present invention.

Figure 13 depicts a flow chart of a method of manufacturing a top electrode in an RRAM device according to some embodiments of the present invention.

Figure 14A depicts a tantalum-hafnium (Ta-Hf) binary phase diagram according to some embodiments of the invention.

Figure 14B depicts a tantalum-tungsten (Ta-W) binary phase diagram according to some embodiments of the invention.

Figure 14C depicts a tantalum-molybdenum (Ta-Mo) binary phase diagram according to some embodiments of the invention.

Figure 14D depicts a tantalum-niobium (Ta-Nb) binary phase diagram according to some embodiments of the invention.

Figure 14E depicts a tantalum-zirconium (Ta-Zr) binary phase diagram according to some embodiments of the invention.

Aspects of the present invention provide resistive random access memory (RRAM) devices and methods of fabricating RRAM devices. RRAM devices are two-terminal passive components with adjustable resistance. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer between the first electrode and the second electrode. The first electrode may include non-reactive metal, such as platinum (Pt), palladium (Pd), etc. The second electrode may include a reactive metal such as tantalum (Ta) or the like. Electrodes that include non-reactive metals are also referred to herein as "non-reactive electrodes." Electrodes including reactive metals are also referred to herein as "reactive electrodes." The switching oxide layer may include a transition metal oxide such as hafnium oxide (HfOx) or tantalum oxide (TaOx). The RRAM device can In an initial or original state, and before any suitable electrical analog (eg, a voltage or current signal applied to the RRAM device) is applied, the RRAM device may have an initially high resistance. The RRAM device can be switched from a raw state to a lower resistance state through a forming process, or from a high resistance state (HRS) to a low resistance state (LRS) through a setup process. The forming process may refer to programming the device from an original state. The setup process may refer to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide layer, the reactive metal can adsorb oxygen ions from the switching oxide layer and generate oxygen vacancies in the switching oxide layer. The oxygen ions can be absorbed in the switching oxide layer through the vacancy mechanism. migration. During the formation process, appropriate programming signals (eg, voltage or current signals) may be applied to the RRAM device, which may cause drift of oxygen ions to migrate from the switching oxide layer to the reactive electrode. Thus, conductive channels or conductive filaments can be formed by switching oxide layers (eg, from reactive to non-reactive electrodes). Then, the RRAM device can be reset to a high resistance state by applying a reset signal (eg, voltage signal, current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause oxygen ions to migrate back to the switching oxide layer and thus interrupt the conductive filaments. By applying appropriate programming signals (eg, voltage signals, current signals, etc.) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a designated RRAM device through a selector, such as a transistor.

In some embodiments, it may be desirable to scale RRAM devices to appropriate dimensions (e.g., critical dimensions of 100 nm, 10 nm, or smaller dimensions) to enable in-memory computing (IMC) applications (e.g., where high-density RRAM devices and/or low power consumption of IMC applications). However, as the critical dimensions of conventional RRAM devices shrink, the conductive filaments formed on conventional RRAM devices may not shrink accordingly. For example, the size of the conductive filaments formed on scaled-down RRAM devices will not scale. Therefore, forming, setting, and/or resetting a traditional shrink RRAM devices may still require relatively high current or voltage. This would also prevent efficient scaling of the selectors (eg, transistors) and/or integrated circuits used to provide current or voltage to the scaled-down RRAM device. In addition, the scaled-down RRAM device may have a relatively small area top electrode. The top electrode may not adsorb as many oxygen ions as large-sized RRAM devices. This can cause equipment failure and/or operational failure of the RRAM device. For example, delamination between the reactive electrode and the switching oxide layer due to the presence of oxygen ions can trigger device failure. For another example, under external voltage, oxygen ions may migrate from the switching oxide to the top electrode. Once the external voltage is removed, the oxygen ions may migrate back to the switching oxide, resulting in unstable operation and failure of the non-volatile memory. .

In order to solve the above and other defects of traditional RRAM devices, the present invention provides an RRAM device with a multi-component electrode structure, a multi-layer electrode structure and an interface layer, which can enhance the performance of the RRAM device and realize low-power IMC applications. In some embodiments, the RRAM device may include a bottom electrode, a first interface layer formed on the bottom electrode, a switching oxide layer formed on the first interface layer, and a switching oxide layer formed on the switching oxide layer. top electrode on the layer. The bottom electrode may include platinum or other suitable non-reactive metal. The switching oxide layer may include transition metal oxides, such as HfOx, TaOx, TiOx, NbOx, ZrOx, etc. The first interface layer may include a discontinuous film of a first material, wherein the first material has greater chemical stability than the transition metal oxide. The first material may include, for example, aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), yttrium oxide (Y ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), etc. The addition of the first interface layer can reduce the contact area between the switching oxide layer and the first electrode, thereby making the formation process less sudden, reducing the formation voltage, reducing the reset current, and reducing the voltage and/or voltage during subsequent operations. current requirements. For example, the first electrode and the switching oxide may be in complete direct contact without the presence of the first interface layer. When there is a continuous first interface layer between the first electrode and the switching oxide, the first electrode does not directly contact the switching oxide. In contrast, when a discontinuous first interface layer exists between the first electrode and the switching oxide, direct contact between the first electrode and the switching oxide is reduced or controlled.

In some implementations, the RRAM device may further include a second interface layer fabricated on the switching oxide layer. In some embodiments, the top electrode can be fabricated on the second interface layer. The second interface layer may include a discontinuous film of a second material that is more chemically stable than the transition metal oxide. The addition of the second interface layer can reduce the contact area between the switching oxide layer and the top electrode.

In some embodiments, the top electrode may include one or more multi-component electrode structures. For example, in one embodiment, the top electrode may include one or more tantalum alloys. The tantalum alloy may be and/or include a binary alloy containing Ta, a ternary alloy containing Ta, a quaternary alloy containing Ta, a five-element alloy containing Ta, a six-element alloy containing Ta and/or a Ta-containing High-element alloys (for example, alloys containing more than 6 metal elements). Each alloy includes tantalum and one or more other metallic elements that possess desirable thermodynamic and/or kinetic properties compared to tantalum, e.g., tungsten (W), hafnium (Hf), molybdenum (Mo ), niobium (Nb), zirconium (Zr), etc. For example, using an alloy of tantalum instead of pure tantalum metal to fabricate the top electrode can reduce the migration of tantalum into the switching oxide layer during the formation process, thereby reducing the size of the conductive filaments formed in the switching oxide layer (e.g., by reducing the conductive filaments lateral size or diameter). This will increase the conductive filament resistance of the RRAM device, and therefore increase the resistance of the RRAM device in the low-resistance state and the high-resistance state, which may reduce RRAM device operations, such as forming, setting, resetting, and/or adjusting the RRAM device, required voltage and/or current. The multi-component electrode structure RRAM device can exhibit dynamic memory behavior in multiple dimensions and is suitable for realizing dynamic learning, edge processing, inference engine acceleration, and other IMC applications.

In other embodiments, the top electrode may include multiple layers composed of different metallic materials. For example, the top electrode may include a titanium (Ti) layer and a tantalum (Ta) layer. The Ti layer can be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between 0.2nm and 5nm. The thickness of the Ta layer may be about 50 nm. In some embodiments, the thickness of the Ti layer may be between 0.3nm and 2nm. Both Ti and Ta can adsorb and release oxygen ions during device operation. Adding a thin Ti layer to an RRAM device can change the original resistance of the RRAM device, leading to a less abrupt formation process, lowering the formation voltage, reducing reset current, and reducing voltage and/or current requirements in subsequent operations.

Accordingly, the present invention provides techniques for fabricating RRAM devices with high conductive filament resistance and reduced operating voltage and current. The RRAM device can also provide required linearity, analog, retention and fatigue characteristics for IMC applications. The addition of the first interface layer and/or the second interface layer can reduce the contact between the switching oxide layer and the bottom electrode and/or the contact between the switching oxide layer and the top electrode. These technologies enable effective reduction of RRAM devices and low-power IMC applications using RRAM devices.

Figure 1 is a schematic diagram of an example 100 of a crossover circuit shown in accordance with some embodiments of the present invention. As shown, the cross circuit 100 may include a plurality of interconnected conductive lines, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n, in the cross circuit of n rows and m columns, and One or more column lines 113a, 113b, ..., 113j, ..., 113m. The cross circuit 100 may further include cross point devices 120a, 120b, ..., 120z, etc. Each crosspoint device can connect one row line and one column line. For example, crosspoint device 120ij may connect row line 111i and column line 113j. In some embodiments, the crossover circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and/or other suitable crossover devices. circuit components. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

The row lines 111 may include a first row line 111a, a second row line 111b, . . . , 111i, . . . and an n-th row line 111n. Each row line 111a, ..., 111n may be and/or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

The column lines 113 may include a first column line 113a, a second column line 113b, . . . and an m-th column line 113m. Each column line 113a-m may be and/or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

Each crosspoint device 120 may be and/or include any suitable device having adjustable resistance, such as a memristor, pulse code modulation (PCM) device, floating gate, spintronics device, RRAM, static Random Access Memory (SRAM), etc. In some embodiments, one or more of the crosspoint devices 120 may include RRAM devices described in connection with Figures 3A-5B.

Crossover circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, the input voltage signal may be applied to one or more rows in crossbar circuit 100 (eg, one or more selected rows). Input signals may pass through crosspoint devices in each row of the crossbar circuit 110 . The conductance of the crosspoint device can be adjusted to a specific value (also referred to as a "weight"). Based on Ohm's law, the input voltage multiplied by the crosspoint conductance generates the current flowing through the crosspoint device. Based on Kirchhoff’s law, the current generated by the sum of the currents of the devices on each column line is used as the output signal, and the output signal can be read from the column line (for example, the output of the ADC). According to Ohm's law and Kirchhoff's law, the input-output relationship of the cross array can be expressed as I=VG, where I is the current and represents the output signal matrix; V is the voltage and represents the input signal matrix; G represents the conductance of the cross-point device matrix. Therefore, according to Ohm's law, the input signal is weighted at each cross-point device by its conductance. The weighted current is output through each column line and accumulated based on Kirchhoff's law. This enables in-memory computing (IMC) by implementing parallel multiplications and sums over the crossbar array.

Figure 2 is a schematic diagram of an example 200 of a cross-point device according to some embodiments of the present invention. As shown, crosspoint device 200 may connect bit lines (BL) 211, select lines (SEL) 213, and word lines (WL) 215. The bit line 211 and the word line 215 may be a column line and a row line respectively as described in FIG. 1 .

Crosspoint device 200 may include RRAM device 201 and transistor 203 . A transistor is a three-terminal device, which can be labeled gate (G), source (S), and drain (D). The transistor 203 may be connected in series to the RRAM device 201. As shown in FIG. 2 , the first electrode of the RRAM device 201 may be connected to the drain of the transistor 203 . The second electrode of the RRAM device 201 may be connected to the bit line 211 . The source of transistor 203 may be connected to word line 215 . The gate of the transistor 203 may be connected to the select line 213 . RRAM devices may include one or more RRAM devices as described in Figures 3A-7. Crosspoint device 200 may also be configured in a 1-transistor-1-resistor (1T1R) configuration. The transistor 203 may perform as a selector and current controller, and a current limiter may be set for the RRAM device during programming. The gate voltage of the transistor 203 can set a current limiter for the crosspoint device 200 during programming, thereby controlling the conductivity and analog behavior of the crosspoint device 200 . For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a setting signal (eg, voltage signal, current signal) may be provided through bit line (BL) 211 . Another voltage, also called the select voltage or gate voltage, can be applied to the transistor gate via the select line (SEL) 213, thereby opening the gate and setting the current limiter, while the word line (WL) 215 Can be set to ground. When crosspoint device 200 resets from a low resistance state to a high resistance state, a gate voltage may be applied to the gate of transistor 203 via select line 213, thereby opening the transistor gate. At the same time, a reset signal can be sent to the RRAM device 201 through the word line 215, and the bit line 211 can be set to ground.

Figures 3A, 3B, and 3C show cross-sectional views of example RRAM devices in accordance with some embodiments of the invention. The RRAM devices 300a, 300b, and 300c may correspond to RRAM devices in an initial state, a low resistance state, and a high resistance state, respectively.

As shown in FIG. 3A, the RRAM device 300a may include a substrate 310, a first electrode 320, a switching oxide layer 330, and a second electrode 340. The RRAM device 300a may further include one or more other components that may be used to implement in-memory computing applications.

Substrate 310 may include one or more layers including any suitable material that may serve as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al ₂ O ₃ ), Aluminum nitride (AlN), etc. In some embodiments, substrate 310 may include diodes, transistors, interconnect devices, integrated circuits, and the like. In some embodiments, the substrate may include driver circuitry that includes one or more individually controllable circuits (eg, a circuit array). In some embodiments, the driver circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

The first electrode 320 may be and/or include any suitable material that is electronically conductive and non-reactive to the switching oxide. For example, the first electrode 320 may include platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), or the like.

The switching oxide layer 330 may include one or more transition metal oxides among binary oxides, ternary oxides, and higher oxides, such as TaOx, HfOx, TiOx, NbOx, ZrOx, and the like. In some embodiments, the chemical stability of the non-reactive metal in the first electrode 320 may be higher than the chemical stability of the transition metal oxide in the switching oxide layer 330 .

Second electrode 340 may include any suitable metallic material that is electronically conductive and reactive toward the switching oxide. For example, the metal material of the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 is reactive to the switching oxide and has appropriate oxygen solubility, so that a portion of the oxygen can be adsorbed from the switching oxide layer 330 to achieve switching oxidation. Oxygen vacancies are generated in the material layer 330 . In other words, the reactive metal material in the second electrode 340 may have appropriate oxygen solubility and/or oxygen mobility. In some embodiments, the second electrode 340 may not only generate oxygen vacancies in the switching oxide layer 330 (eg, by scavenging oxygen ions), but may also serve as an oxygen reservoir or source for the switching oxide layer 330 during cell programming.

The RRAM device 330a may have an initial resistance (also referred to as "original resistance") after being fabricated. The initial resistance of RRAM device 300a can be changed, and RRAM device 300a can switch to a low resistance state through the formation process. For example, a suitable voltage or current may be applied to RRAM device 300a. Applying a voltage to the RRAM device 300 can cause the metal material of the second electrode to adsorb oxygen ions from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer 330 . Oxygen vacancy-rich conductive channels (eg, conductive filaments) may thereby be formed in the switching oxide layer 330 . For example, as shown in FIG. 3B , a conductive channel 335a is formed in the switching oxide layer 330 . As shown, a conductive channel 335a may be formed through the switching oxide layer 330 from the second electrode 330 to the first electrode 320. RRAM device 300b can be reset to a high resistance state. For example, a reset signal (eg, a voltage signal or a current signal) may be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal may have opposite polarities, that is, positive signals and negative signals respectively. The reset signal may cause oxygen ions to migrate back to the switching oxide layer 330 and recombine with one or more oxygen vacancies. For example, during a reset process, as shown in FIG. 3C , an interrupted conductive channel 335b may be formed in the switching oxide layer 330 . As shown in the figure, the conductive path is interrupted due to an oxide gap between the interrupted conductive path 335b and the first electrode 320. The lateral dimension of conductive channel 335b may be smaller than the lateral dimension of conductive channel 335a. In some embodiments, the conductive channel 335b cannot continuously connect the first electrode 320 and the second electrode 340. RRAM devices 330a-c can be electrically switched between high resistance states and low resistance states by applying appropriate programming signals (eg, voltage signals, current signals, etc.) to the RRAM devices.

4A-4F are schematic diagrams illustrating cross-sectional views of example structures 400a, 400b, 400c, 400d, 400e, and 400f of RRAM devices in accordance with some embodiments of the invention.

As shown in FIG. 4A, the first electrode 420 may be fabricated on the substrate 410. The first electrode 420 and the substrate 410 may respectively correspond to the first electrode 320 and the substrate 310 described in FIGS. 3A, 3B, and 3C.

As shown in FIG. 4B , an interface layer 422 may be fabricated on the first electrode 420 . The interface layer 422 (also referred to herein as the "first interface layer) may be and/or include a discontinuous film 422a. For example, the discontinuous film 422a may include one or more pores 424. The pores 424 (also referred to herein as "first pores") may be of any suitable size and/or dimensions and may be randomly dispersed across the interface layer 422. Although a specific number of pores is shown in Figure 4B, This is illustrative only. The discontinuous film 422a can include any suitable number of pores. In some embodiments, the thickness of the interface layer 422 and/or the discontinuous film 422a can range from about 0.2 nanometers to about 0.5 nanometers. between nanometers. In some embodiments, the discontinuous film 422a may be an Al ₂ O ₃ film with a thickness equal to or less than 0.5 nanometers. In some embodiments, the discontinuous film 422a may include an Al 2 O 3 film with a thickness less than 1 nm. Nano-sized Al ₂ O ₃ thin film.

2.0，對於TaOx(其中Ta2O5為完全氧化物)，x

2.5。作為一個示例，所述切換氧化物層430可以包括Ta2O5。作為另一個示例，所述切換氧化物層430可以包括HfO2。 As shown in FIG. 4C , a switching oxide layer 430 may be fabricated on the interface layer 422 . The switching oxide layer 430 may include one or more transition metal oxides, such as TaOx, HfOx, TiOx, NbOx, ZrOx and other binary oxides, ternary oxides or higher oxides, where x may be used to represent The oxide is anoxic compared to the complete (or final) oxide, and the value of x can vary with the ratio of oxygen to metal atoms in the stoichiometry of its complete oxide, for example, for HfO is a complete oxide), x

2.0, for TaOx (where Ta2O5 is a complete oxide), x

2.5. As an example, the switching oxide layer 430 may include Ta2O5. As another example, the switching oxide layer 430 may include HfO2.

In some embodiments, a portion or portions of a transition metal oxide may be disposed on the first electrode 420 through one or more pores 424 during fabrication of the switching oxide layer 430 . Accordingly, the switching oxide layer 430 may be in contact with one or more portions of the first electrode 420 .

2.0和y

2.5，且所述第一材料可以包括Al₂O₃,MgO,Y₂O₃,La₂O₃等。 In some embodiments, the interface layer 422 may include a first material that has greater chemical stability than the transition metal oxide in the switching oxide layer 430 . Therefore, the first material may not react with the transition metal oxide in the switching oxide layer 430 . The first material may include a monovalent metal element. As an example, the switching oxide in the switching oxide layer may be and/or include one or more transition metal oxides, such as at least one of HfOx or TaOy, where x

2.0 and y

2.5, and the first material may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc.

Referring to FIG. 8 , an Ellingham plot can be used to identify materials that are more chemically stable than the transition metal oxide in the switching oxide layer 430 . As shown, the Ellingham diagram 800 plots the Gibbs free energy variable of the oxidation reaction as a function of temperature. The chemical stability of the material can be determined based on the material's Gibbs energy of generation value. The Gibbs free energy shown on the vertical axis in FIG. 8 represents the free energy of formation of an oxide (including 1 mole of oxygen), and the horizontal axis represents the Kelvin temperature. As shown in the figure, the relative stability of these oxides increases from Ta2O5, TiO2, HfO2 to Al ₂ O ₃ . Al ₂ O ₃ is more stable than HfO2 at room temperature. It should be noted that aluminum metal melts at 933k (660 degrees Celsius), and the aluminum liquid has a higher entropy than individual aluminum. Al ₂ O ₃ becomes less stable than HfO 2 at higher temperatures. In the Ellingham diagram, the curve for the material of the interface layer 422 may be lower than the curve corresponding to the transition metal oxide in the switching oxide layer 420 . As an example, in some embodiments, Al ₂ O ₃ may be used as the first material, wherein the transition metal oxide in the switching oxide layer 430 includes HfO 2 or Ta 2 O 5 . The first material containing Al ₂ O ₃ does not react with the transition metal oxide containing HfO 2 or Ta 2 O 5 during the setup process and the reset process.

As shown in FIG. 4D, a second electrode 440 may be fabricated on the switching oxide layer 430. In some embodiments, the second electrode 440 may include one or more top electrodes 700 as described in FIG. 7 . In some embodiments, the second electrode 440 fabricated on the switching oxide layer 430 may include one or more alloys. Each alloy may include two or more metallic elements. Each alloy may include a binary alloy (e.g., an alloy containing two metal elements), a ternary alloy (e.g., an alloy containing three metal elements), a quaternary alloy (e.g., an alloy containing four metal elements), a quintile alloy. Meta-alloys (eg, alloys containing five metallic elements), hexa-metal alloys (eg, alloys containing six metallic elements), and/or high-alloys (eg, alloys containing more than six metallic elements). In some embodiments, the second electrode 340 may include one or more alloys containing a first metal element and one or more second metal elements. Each second metal element may be less or more reactive toward the transition metal oxide in the switching oxide layer than the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of W, Hf, Mo, Nb, Zr, etc. In some embodiments, the ratio of the first metal element and the second metal element in the alloy of the second electrode 440 may be about 50 atomic percent. In some embodiments, the appropriate ratio of the first metallic element to the second metallic element in the alloy can be optimized over the entire composition range. During the formation process, the second metal element may form fewer oxygen vacancies in the switching oxide layer than the first metal element, and therefore, the lateral dimensions of the conductive filaments formed in the RRAM device including the second electrode containing the alloy May be smaller than the lateral dimensions of conductive filaments formed in RRAM devices that include second electrodes containing only the first metal. Implementation of a Ta-containing alloy in the second electrode 440 in an RRAM device may make the formation process less abrupt, lower the formation voltage, lower the reset current, and reduce voltage and/or current requirements during subsequent operation.

For example, the second electrode 440 may include one or more Ta-containing alloys (also referred to as “Ta alloys”). Each Ta alloy may include Ta and one or more other metal elements (eg, Hf, W, Mo, Nb, Zr, etc.). Exemplarily, the second electrode 440 may include one or more binary alloys containing Ta. For example, Ta-containing binary alloys may include Ta-Hf alloys, Ta-W alloys, Ta-Mo alloys, Ta-Nb alloys, Ta-Zr alloys, and the like. Exemplarily, the second electrode 440 may include one or more ternary alloys containing Ta. For example, the ternary alloy containing Ta may include Ta-Hf-Mo alloy, Ta-Hf-Nb alloy, Ta-Hf-W alloy, Ta-Hf-Zr alloy, Ta-Mo-Nb alloy, Ta-Mo-W Alloy, Ta-Mo-Zr alloy, Ta-Nb-W alloy, Ta-Nb-Zr alloy, Ta-W-Zr alloy, etc. Exemplarily, the second electrode 440 may include one or more quaternary alloys containing Ta. For example, the Ta-containing quaternary alloy may include Ta-Hf-Mo-Nb alloy, Ta-Hf-Mo-W alloy, Ta-Hf-Mo-Zr alloy, Ta-Hf-Nb-W alloy, Ta-Hf- Nb-Zr alloy, Ta-Mo-Nb-W alloy, Ta-Mo-Nb-Zr alloy, Ta-Nb-W-Zr alloy, etc. Exemplarily, the second electrode may include one or more quinary alloys containing Ta. For example, Ta-containing five-element alloys may include Ta-Hf-Mo-Nb-W alloy, Ta-Mo-Nb-W-Zr alloy, Ta-Hf-Nb-W-Zr alloy, Ta-Hf-Mo-W- Zr alloy, Ta-Hf-Mo-Nb-Zr alloy, etc. Exemplarily, the second electrode 440 may include a six-element alloy containing Ta, such as Ta-Hf-Mo-Nb-W-Zr alloy. For example, the second electrode 440 may include a high-element alloy containing Ta. In some embodiments, the high-element alloy may further include vanadium (V).

In some embodiments, the second electrode 440 may include multiple alloys. Each alloy may be a Ta alloy containing Ta and one or more other metal elements (eg, Hf, W, Mo, Nb, Zr, etc.). The Ta alloy may be and/or include a binary alloy, a ternary alloy, a quaternary alloy, a five-element alloy, a six-element alloy, a high-element alloy, etc. Exemplarily, the second electrode 440 may include a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a third alloy containing Ta. Two or more of the sixth alloys superior. In some embodiments, the first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta and the sixth alloy containing Ta They can be binary alloys, ternary alloys, quaternary alloys, five-element alloys, six-element alloys and high-element alloys.

In some embodiments, the multiple alloys in the second electrode 440 may correspond to the same number of combinations of metal elements. For example, the first alloy containing Ta and the second alloy containing Ta may respectively include a first binary alloy containing Ta (eg, Ta-W alloy) and a second binary alloy containing Ta (eg, Ta- Mo alloy). Exemplarily, the first alloy containing Ta and the second alloy containing Ta may respectively include a first ternary alloy containing Ta (for example, Ta-Hf-Mo alloy) and a second ternary alloy containing Ta (e.g., Ta-Hf-Mo alloy). For example, Ta-Hf-Nb alloy). By way of example, the second electrode 440 may include a variety of alloy systems. Each alloy system can contain a mixture of specific metallic elements with different compositions. For example, a binary system may include one or more binary alloys containing two metallic elements, such as Ta and Hf, with different compositions. Each binary alloy can be a combination of two metallic elements with a specific composition. Illustratively, a ternary system may include one or more ternary alloys containing three metallic elements (eg, Ta, Hf, and W) with different compositions. Each ternary alloy can be a combination of three metallic elements with a specific composition. In some embodiments, the second electrode 440 may include a Ta alloy system containing one or more alloy systems. In some embodiments, the Ta alloy system may include two or more alloy systems. For example, the Ta alloy system may include a six-element system containing one or more alloys of Ta, Hf, W, Mo, Nb, and Zr. The Ta alloy system may further include one or more binary systems, ternary systems, quaternary systems and/or quintuple systems containing Ta alloys. The binary system may include one or more of Ta-Hf alloy system, Ta-W alloy system, Ta-Mo alloy system, Ta-Nb alloy system and/or Ta-Zr alloy system. The ternary system may include Ta-Hf-Mo alloy system, Ta-Hf-Nb alloy system, Ta-Hf-W alloy system, Ta-Hf-Zr alloy system, Ta-Mo-Nb alloy system, Ta-Mo-W alloy system, Ta-Mo-Zr alloy system, Ta-Nb-Zr alloy system, Ta-Nb-W alloy system and/or One or more of the Ta-W-Zr alloy systems. The quaternary alloy system may include Ta-Hf-Mo-Nb alloy system, Ta-Hf-Mo-W alloy system, Ta-Hf-Mo-Zr alloy system, Ta-Hf-Nb-W alloy system, Ta-Hf- One or more of the Nb-Zr alloy system, Ta-Mo-Nb-W alloy system, Ta-Mo-Nb-Zr alloy system, and Ta-Nb-W-Zr alloy system. Five-element alloys may include Ta-Hf-Mo-Nb-W alloy system, Ta-Mo-Nb-W-Zr alloy system, Ta-Hf-Nb-W-Zr alloy system, Ta-Hf-Mo-W-Zr One or more of the alloy system and/or Ta-Hf-Mo-Nb-Zr alloy system. Each alloy system included in second electrode 440 may possess unique thermodynamic and kinetic properties and may be considered an electrode component. Therefore, the second electrode 440 may include multiple electrode components for providing multiple state variables, thereby enabling rich dynamics with different time constants that can be used for calculation and learning. For example, each electrode component may possess a different reactivity toward the switching oxide or affinity toward oxygen. Each electrode component can have different diffusivity (eg, self-diffusion, interdiffusion, diffusion time constant, etc.). Second electrode 440 with multiple compositions can provide multiple dynamic behaviors for IMC applications. Therefore, RRAM devices containing multi-component second electrodes can exhibit dynamic memory behavior in multiple dimensions.

4E and 4F illustrate semiconductor devices 400e and 400f that may correspond to low resistance states and high resistance states, respectively, of RRAM device 400d. The addition of the discontinuous film 422 can reduce the contact area between the switching oxide layer 430 and the first electrode 420 . As shown in FIG. 4E, a conductive channel 435a (eg, a conductive filament) may be formed from the second electrode 440 to the first electrode 420 through the interface layer 422 and the switching oxide layer 430. As shown in FIG. 4F, during the reset process, an interrupted conductive channel 435b may be formed in the switching oxide layer 430. Compared to Figures 3B and 3C, the lateral dimensions of the conductive channel 435a and the illustrated interrupted conductive channel 435b may be smaller than the lateral dimensions of 335a and 335b, respectively. Therefore, formed on a film having a discontinuous film 422 The lateral dimensions of the conductive filaments in an RRAM device may be smaller than the lateral dimensions of the conductive filaments formed in an RRAM device in which a porous and/or discontinuous film is not formed between the first electrode and the switching oxide layer . The addition of discontinuous film 422 to RRAM devices can make the formation process less abrupt, reduce formation voltage, reduce reset current, and reduce voltage and/or current requirements during subsequent operations.

In some embodiments, an RRAM device may include a plurality of interface layers fabricated between the first electrode and the second electrode. Each interface layer may include a discontinuous film as described in Figure 4B. For example, as shown in FIG. 5A, semiconductor device 500a may be fabricated by fabricating interface layer 532 (also referred to as a "second interface layer") on semiconductor structure 400c as described in FIG. 4C. In some embodiments, the second interface layer 532 may include a discontinuous film 532a of the second material. The second material may have greater chemical stability than at least one transition metal oxide in the switching oxide layer 430 . As an example, the second material may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. The second material may be the same as the first material, or may be different.

The discontinuous film 532a may include one or more pores 534 (also referred to as "one or more second pores"). The pores 534 may be of any suitable size and/or dimensions. The plurality of apertures 534 may or may not have the same size and/or dimensions. In some embodiments, the second interface layer 532 and/or the second discontinuous film 532a may include a plurality of pores 534 randomly distributed on the second discontinuous film 532. The discontinuous membrane 532a may include any suitable number of pores.

In some embodiments, the thickness of the second interface layer 532 and/or the discontinuous film 532a (also referred to as the "second thickness") may be between about 0.2 nanometers and about 0.5 nanometers. As another example, the second interface layer 532 may include a discontinuous Al ₂ O ₃ film with a thickness equal to or less than 0.5 nanometers. In some embodiments, the second interface layer 532 may include a discontinuous Al ₂ O ₃ film with a thickness less than 1 nanometer. The second thickness of the second interface layer 532 may be the same as the first thickness of the first surface layer 422 , or may be different.

As shown in FIG. 5B, a second electrode 540 may be fabricated on the second interface layer 532 to fabricate the semiconductor device 500b. The second interface layer 532 may therefore be positioned between the switching oxide layer 430 and the second electrode 540 . The second electrode 540 may be and/or include the second electrode 440 as described in Figures 4D-4F. In some embodiments, one or more portions of the second electrode 540 may be disposed on the switching oxide layer 430 through one or more apertures 534 during fabrication of the switching oxide layer 430 . Accordingly, the second electrode 540 may contact one or more portions of the switching oxide layer 430 through the one or more pores 534 .

5C and 5D illustrate semiconductor devices 500c and 500d respectively corresponding to the low resistance state and the high resistance state of RRAM device 500b. The joint addition of the first interface layer 422 and the second interface layer 532 can further reduce the contact area between the switching oxide layer 430 and the first electrode 420 and the contact area between the switching oxide layer 430 and the third electrode. The contact area of the two electrodes 540. As shown in FIG. 5C , a conductive channel 535a ( For example, conductive filaments). As shown in Figure 5D, interrupt conductive channels 535b may be formed in the switching oxide layer 430 during the reset process. Compared to Figures 3B and 3C, the lateral dimensions of the conductive channel 535a and the interrupted conductive channel 535b may be smaller than the lateral dimensions of 335a and 335b respectively. Therefore, the lateral size of the conductive filaments formed on the RRAM device having both the interface layer 422 and the second interface layer 532 can be further reduced, thereby making the formation process less abrupt, reducing the formation voltage, and reducing resets. current and reduce voltage and/or current requirements during subsequent operation.

In some embodiments, an interface layer may be fabricated at the switching oxide layer of the RRAM device in accordance with some embodiments of the present invention. For example, as shown in FIG. 6A, switching oxide layer 630 may be fabricated on semiconductor device 400a as described in connection with FIG. 4A. Interface layer 632 may be fabricated on the switching oxide layer 630 to fabricate semiconductor device 600a. The switching oxide layer 630 may be and/or include the switching oxide layer 430 described in connection with Figures 4C-4F. In some embodiments, the interface layer 632 may include a discontinuous film of a third material. The third material may have greater chemical stability than at least one transition metal oxide in the switching oxide layer 630 . As an example, the third material may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc.

The discontinuous film 632a may include one or more apertures 634 (also referred to as "one or more third apertures"). The pores 634 may be of any suitable size and/or dimensions and may be randomly distributed on the second discontinuous film 632 . In some embodiments, the thickness of the interface layer 632 (also referred to as the "third thickness") may be between about 0.2 nanometers and about 0.5 nanometers. As another example, the thickness of the interface layer 632 may be equal to or less than a thickness of 0.5 nanometers. As a further example, the thickness of the interface layer 632 may be less than 1 nanometer.

As shown in FIG. 6B, a second electrode 640 may be fabricated on the interface layer 632 to fabricate the semiconductor device 600b. Therefore, the interface layer 632 may be positioned between the switching oxide layer 630 and the second electrode 640 . The second electrode may be and/or include second electrode 440 described in connection with Figures 4D-4F. In some embodiments, during fabrication of the second electrode 640, one or more portions of the second electrode 640 may be disposed on the switching oxide layer 630 through one or more apertures 634. Accordingly, the second electrode 640 may contact one or more portions of the switching oxide layer 630 .

6C and 6D illustrate semiconductor devices 600c and 600d respectively corresponding to the low resistance state and the high resistance state of RRAM device 660b. The addition of the discontinuous film 632 can reduce the contact area between the switching oxide layer 630 and the second electrode 640 . As shown in FIG. 6C , a switching oxide may be formed from the second electrode 640 to the first electrode 420 through the switching oxide. Layer 630 and conductive channels 635a (eg, conductive filaments) of the discontinuous film 632. As shown in FIG. 6D , an interrupted conductive channel 635b may be formed in the switching oxide layer 630 during the reset process. Compared to Figures 3B and 3C, the lateral dimensions of the conductive channel 635a and the interrupted conductive channel 635b may be smaller than the lateral dimensions of 335a and 335b respectively. Therefore, the lateral dimensions of the conductive filaments formed on the RRAM device having the discontinuous film 632 may be smaller than the lateral dimensions of the conductive filaments formed on the RRAM device not having the discontinuous film 632 . The use of the discontinuous film 632 in RRAM devices can make the formation process less abrupt, lower the formation voltage, reduce reset current, and reduce voltage and/or current requirements during subsequent operations.

Figure 7 illustrates a cross-sectional view of an example 700 of a top electrode in accordance with some embodiments of the invention.

As shown, the top electrode 700 may include a first layer 710 and a second layer 720. The first layer 710 may include a first metal material that may scavenge oxygen from the transition metal oxide in the switching oxide layer. The second layer 720 may include a second metal material that may scavenge oxygen from the transition metal oxide in the switching oxide layer. The oxide of the first metal material has higher chemical stability than the transition metal oxide in the switching oxide layer. Accordingly, the first metal material can react with and scavenge oxygen from the transition metal oxide in the switching oxide layer. The oxide of the first metallic material may be less chemically stable than the first material of the first discontinuous film and the second material of the second discontinuous film. Therefore, the first metallic material may not chemically reduce the first discontinuous film and the second discontinuous film. As mentioned above, the Ellingham plot can be used to determine and compare the chemical stabilities of two or more elements.

The first metallic material and the second metallic material may include different chemical elements and possess different oxygen affinities and/or different thermodynamic and kinetic properties. The first metal material and the second metal material may be incompatible. In some embodiments, the A metallic material may include Ti. The second metal material may include Ta. In some embodiments, the first layer 710 may be and/or include a Ti metal layer (eg, a Ti film). The second layer 720 may be and/or include a Ta metal layer (eg, Ta film). As shown in the Ta-Ti binary phase diagram in Figure 9, the Ta and Ti phase diagrams are immiscible and have minimum mutual solubility at 300K (27°C), which is approximately the operating temperature of RRAM devices (e.g. , temperatures near or above room temperature). Therefore, the addition of Ti in RRAM devices may not affect the operating mechanism of Ta conductive filaments in switching oxides and the switching mechanism of RRAM devices described in this paper. The RRAM device shown in Figure 7 can be applied to IMC applications that require RRAM devices with excellent performance in terms of analog behavior, linearity, persistence, reliability, etc. The incompatibility and minimum mutual solubility between the Ta and Ti phase diagrams can also allow thermodynamic equilibrium to be reached between the second layer 720 and the first layer 710 . Therefore, a thin Ti film can function as designed without reacting with or being dissolved by the Ta film.

In addition, because Ti has a higher oxygen affinity than Ta, Ti can more easily scavenge oxygen ions from switching oxides. Therefore, incorporating the first layer 710 into the RRAM device can further improve the performance of the RRAM device by reducing the formation voltage required during RRAM formation and the current and voltage requirements during subsequent operations. For example, the second electrode 440 shown in FIGS. 4D-4F, the second electrode 540 shown in FIGS. 5B-5D, and/or the second electrode 640 shown in FIGS. 6B-6D may be and/or include a third electrode. Two electrodes 700. During the formation process, both the first metal material and the second metal material may create oxygen vacancies in switching oxide layers 330, 430, and/or 630. Compared to Figures 3B and 3C, the lateral dimensions of the conductive channels and interrupted conductive channels may be smaller than the lateral dimensions of 335a and 335b, respectively. Since Ti has a higher oxygen affinity than Ta, the original resistance of the RRAM device 500b including the top electrode 700 may be less than that of the RRAM device not including the top electrode 700, resulting in a lower formation voltage, a lower reset voltage , lower reset current, etc.

Ti can also easily store oxygen ions during setup (when oxygen ions migrate from the switching oxide to the second electrode). This allows the second electrode to store oxygen during the reset process ions, and thus prevents device failure (which can be caused by the presence of oxygen molecules between the switching oxide and the second electrode) and/or operating failures (which can be caused by oxygen ions migrating back to the switching oxide or switching instability once the reset voltage is removed Caused).

The first layer 710 can be grown to a suitable thickness so that the first metal material (eg, Ti) of the first layer 710 can function as described above without affecting the inclusion of the second metal material on the switching oxide layer 330 The formation of conductive filaments (such as Ta conductive filaments). In some embodiments, the thickness of the first layer 710 may be between 0.2 nm and about 5 nm. In some embodiments, the thickness of the first layer 710 may be between 0.5 nm and about 2 nm. In some embodiments, the thickness of the first layer 710 may be approximately 1 nm. In some embodiments, the thickness of the first layer 710 may be less than 1 nm. The second layer 720 is thicker than the first layer 710 . In some embodiments, the thickness of the second layer 720 may be between 5 nm and 300 nm. For example, the thickness of the second layer 720 may be between about 10 nm and about 100 nm. In some embodiments, the thickness of the second layer 720 may be between about 10 nm and about 200 nm. In some embodiments, the thickness of the second layer 720 may be approximately 50 nm. The thickness of the first electrode may be between approximately 5 nm and 100 nm. In some embodiments, the thickness of the first electrode may be about 30 nm. In some embodiments, the dimensions (eg, critical dimensions) of RRAM devices 400d, 500b, and/or 600b may be between 1 μm and single digit nanometers. In some embodiments, the critical dimension of RRAM devices 400d, 500b, and/or 600b may be about or less than 0.28 μm, and/or between 1 μm and 1 nanometer. In some embodiments, the critical dimension of RRAM devices 400d, 500b, and/or 600b may be between 1 μm and 2 nm. In some embodiments, the critical dimension of RRAM devices 400d, 500b, and/or 600b may be between 1 μm and 5 nm. In some embodiments, the critical dimensions of RRAM devices 400d, 500b, and/or 600b may be in the single-digit nanometer scale (eg, between approximately 1 nm and 9 nm).

In one embodiment, the second layer 720 may be fabricated directly on the first layer 710 . For example, as shown in Figure 7, the surface of the second layer 720 may be directly connected to the One layer of 710 surface. In another embodiment, one or more other suitable material layers may be deposited between first layer 710 and second layer 720.

Adding the first layer 710 to the RRAM device can reduce the original resistance of the RRAM device, reduce the formation voltage, and reduce the reset current, so that the formation process is not sudden, the conductive filaments with lower conductivity and the lower voltage during subsequent operations and current.

Although certain components of RRAM devices 400d-f, 500b-d, and 600b-d are shown in Figures 4D-4F, 5B-5D, and 6B-6D, this is for illustrative purposes only. RRAM devices 400d-f, 500b-d, and 600b-d may include one or more additional layers of suitable materials for implementing IMC applications. For example, one or more interface layers (not shown) may be fabricated between the switching oxide layer and one or more of the second and first electrodes to improve interface stability and device performance.

Figure 10 is a flowchart illustrating an example 1000 of a method of manufacturing an RRAM device in accordance with some embodiments of the invention.

In 1010, a first electrode may be fabricated on the substrate. The first electrode may be fabricated using physical vapor deposition (PVD) technology, chemical vapor deposition (CVD) technology, sputter deposition technology, atomic layer deposition (ALD) technology and/or any other suitable deposition technology to deposit one or more Non-reactive metal layer, such as Pt, Pd, Ir, etc. In some embodiments, fabricating the first electrode may deposit one or more Pt layers. The first electrode may be and/or include first electrodes 320 and 420 as described in connection with Figures 3A-6D.

At 1020, an interface layer can be fabricated on the first electrode. Fabricating the interface layer may involve depositing a first material on the first electrode to form a first discontinuous film of the first material. The first discontinuous film may contain one or more pores. The first material may have greater chemical stability than the transition metal oxide in the switching oxide layer described below. In some embodiments, the first material may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. The interface layer may be and/or include a first interface layer 422 as described in connection with Figures 4B-5D. In some embodiments, fabricating the first interface layer may involve depositing a first material layer having an appropriate thickness to The first discontinuous film is formed. For example, fabricating the first interface layer may involve depositing a first material to a thickness of between about 0.2 nm and about 1 nm. The first discontinuous film may be deposited using PVD, CVD, ALD and/or any other suitable deposition technique.

At 1030, a switching oxide layer can be fabricated on the interface layer. The switching oxide layer may include one or more transition metal oxides. The transition metal oxide may include, for example, TaOx, HfOx, TiOx, NbOx, ZrOx, etc. In some embodiments, one or more portions of the transition metal oxide may be deposited on the first electrode through one or more of the first pores during fabrication of the switching oxide layer. The switching oxide layer may be deposited using PVD, CVD, ALD and/or any other suitable deposition technique. The switching oxide layer may be and/or include the switching oxide layer 430 described in connection with Figures 4C-5D.

At 1040, a second electrode may be fabricated on the switching oxide layer. The second electrode may include one or more alloys. Each alloy may contain a first metallic element and one or more second metallic elements. Each of the second metal element and the first metal element has different reactivity towards the transition metal oxide on the switching oxide layer. In some embodiments, the first metallic element may be Ta. The second metal element may be one or more of W, Hf, Mo, Nb, Zr, etc. Based on the binary phase diagrams involving Ta and the second metal element W, Hf, Mo, Nb or Zr as shown in Figures 14A-14E, Ta-W (Figure 14B), Ta-Mo (Figure 14C) and Ta-Nb (Fig. 14D) A continuous solid solution is formed, and Ta-Hf (Fig. 14A) and Ta-Zr (Fig. 14E) are immiscible at the RRAM device operating temperature. No binary intermetallic compounds are formed between these binary alloys. The absence of intermetallic compounds in these binary systems is advantageous for IMC applications, and such alloy electrodes can be easily fabricated and controlled. For example, the second electrode may be made by co-sputtering the first metal and the second metal to make an alloy. As another example, making the second alloy may involve starting from an alloy target such as Ta- W alloy, Ta-Hf alloy, Ta-Mo alloy, Ta-Nb alloy, Ta-Zr alloy, etc.) by sputtering the first metal element (for example, pure Ta metal) and the second metal element (for example, pure Hf metal) necessary ingredients.

In some embodiments, fabricating the second electrode may involve fabricating a variety of electrode components including Ta, Hf, Nb, Mo, W, and/or Zr. Each electrode assembly may be and/or include a binary alloy, a ternary alloy, a quaternary alloy, a quinary alloy, a six-component alloy, and/or a cavernous alloy of Ta. For example, fabricating the second electrode may fabricate second electrode 440 including one or more alloys and/or alloy systems as depicted in Figure 4D. More specifically, for example, manufacturing the second electrode may involve manufacturing a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a fifth alloy containing Ta. Two or more of its sixth alloys. The first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta and the sixth alloy containing Ta may respectively be binary alloys. , ternary alloys, quaternary alloys, five-element alloys, six-element alloys and high-element alloys.

In some embodiments, fabricating the second electrode may involve fabricating multiple layers of multiple metallic materials, such as layers 710 and 720 as depicted in FIG. 7 . In some embodiments, the second electrode may be fabricated by performing one or more operations described in connection with FIG. 13 .

The second electrode may be deposited using PVD, CVD, ALD and/or any other suitable deposition technique. The second electrode may be and/or include second electrode 440 described in connection with Figures 4D-4F.

Figure 11 is a flowchart of an example 1100 of a method of manufacturing an RRAM device in accordance with some embodiments of the present invention.

At 1110, a first electrode may be fabricated on the substrate. The first electrode may be fabricated on the substrate by performing one or more operations associated with step 1010 of FIG. 10 . The first electrode may be and/or include first electrodes 320 and/or 420 described in connection with Figures 3A-6D.

At 1120, a first interface layer can be fabricated on the first electrode. Fabricating the first interface layer may involve fabricating a first discontinuous film of the first material. The first interface layer may be fabricated on the first electrode by performing one or more operations associated with step 1020 of FIG. 10 . The first interface layer may be and/or include first interface layer 422 described in connection with Figures 4B-5D.

At 1130, a switching oxide layer can be fabricated on the first interface layer. The switching oxide layer may be fabricated on the first interface layer by performing one or more operations associated with step 1030 of FIG. 10 . The switching oxide layer may be and/or include switching oxide layer 430 as described in connection with Figures 4C-5D.

At 1140, a second interface layer can be fabricated on the switching oxide layer. Fabricating the second interface layer may involve fabricating a second discontinuous film of a second material that is more chemically stable than the transition metal oxide in the switching oxide layer. In some embodiments, the second material may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. In some embodiments, fabricating the second interface layer may involve depositing a second material with an appropriate thickness to form the second discontinuous film. The discontinuous film may be deposited using PVD, CVD, ALD and/or any other suitable deposition technique. The second interface layer may be and/or include the second interface layer 532 described in connection with Figures 5A-5D.

At 1150, a second electrode may be fabricated on the second interface layer. The second electrode may be fabricated on the second interface layer by performing one or more operations associated with step 1040 of FIG. 10 . In some embodiments, during fabrication of the second electrode, one or more portions of the second electrode may be deposited on the switching oxide layer through one or more second pores. The second electrode may be and/or include the second electrode 540 described in connection with Figures 5B-5D.

Figure 12 is a flowchart illustrating an example 1200 of a method of fabricating an RRAM device in accordance with some embodiments of the invention.

At 1210, a first electrode may be fabricated on the substrate. The first electrode may be fabricated on the substrate by performing one or more operations associated with step 1010 of FIG. 10 . The first electrode may be and/or include first electrodes 320 and/or 420 described in connection with Figures 3A-6D.

At 1220, a switching oxide layer can be fabricated on the first electrode. The switching oxide layer may include one or more transition metal oxides. The transition metal oxide may include, for example, TaOx, HfOx, TiOx, NbOx, ZrOx, etc. The switching oxide layer may be and/or include switching oxide layer 630 as described in connection with Figures 6A-6D.

At 1230, an interface layer can be fabricated on the switching oxide layer. The interface layer may include a discontinuous film of a material that is more chemically stable than the transition metal oxide in the switching oxide layer. The interface layer may be fabricated on the switching oxide layer by performing one or more operations associated with step 1140 of FIG. 11 . The interface layer may be and/or include the second interface layer 632 described in connection with Figures 6A-6D.

At 1240, a second electrode can be fabricated on the interface layer. The second electrode may be fabricated on the interface layer by performing one or more operations associated with step 1150 of FIG. 11 . The second electrode may be and/or include second electrode 640 described in connection with Figures 6B-6D.

Figure 13 is a flowchart of an example method 1300 for fabricating a top electrode of an RRAM device in accordance with some embodiments of the present invention.

At 1310, a first layer including a first metallic material may be fabricated. The first metal material may include a first metal element such as Ti, Hf, and Zr. The first layer of first metallic material may be fabricated by depositing a first metal (eg, Ti metal) using PVD, CVD, sputtering, ALD, and/or any other suitable deposition technique. Fabricating the first layer of first metallic material may This involves depositing a first metal layer of appropriate thickness, such as a thickness between about 0.2 nm and about 5 nm, a thickness between about 0.5 nm and about 2 nm, and the like.

At 1320, a second layer including a second metallic material may be fabricated. The second metal material may include a second metal element different from the first metal element. For example, the second metallic element may be Ta. In some embodiments, fabricating the second layer containing the second metallic material may involve fabricating by depositing a second metal (eg, Ta metal) using PVD, CVD, sputtering, ALD, and/or any other suitable deposition technique. . Fabricating the second layer of the second metal may involve depositing a suitable thickness of the second metal layer, eg the second metal layer may be thicker than the first metal layer. In some embodiments, the second metal layer may be deposited with a thickness of between 10 nm and 100 nm. In some embodiments, the second layer of the second metal can be deposited directly on the first layer of the first metal. In this embodiment, the surface of the first layer of first metal may be directly connected to one or more partial surfaces of the second layer of second metal.

In some embodiments, fabricating the second layer that includes the second metallic material may involve fabricating a layer that includes one or more alloys. As mentioned above, each alloy may include a first metallic element and one or more second metallic elements. Each second metal element may have different reactivity toward the transition metal oxide and the first metal element in the switching oxide layer. In some embodiments, the first metal element may be Ta. The second metal element may be one or more of W, Hf, Mo, Nb, Zr, etc. Fabricating the second layer of Ta alloy may involve depositing Ta alloy using PVD, CVD, sputtering, ALD and/or any other suitable deposition technique. Fabricating the second layer of Ta alloy may involve depositing a Ta alloy layer of appropriate thickness, for example, the Ta alloy layer being thicker than the first layer of the first metal. In some embodiments, a layer containing one or more Ta alloys may be deposited to a thickness of between about 5 nm and 100 nm.

For simplicity of explanation, the method of the present invention is depicted and described as a sequence of actions. However, actions according to the present invention can occur in various orders and/or simultaneously, and are consistent with the present invention. Other actions not shown and not described in the invention occur together. Furthermore, not all illustrated acts may be required to implement methods in accordance with the disclosed subject matter. Additionally, those skilled in the art will understand and appreciate that these methods may alternatively be represented as a series of interrelated states through state diagrams or events.

As used herein, the terms "about," "about," and "substantially" may mean within normal tolerances in the art, such as within 2 standard deviations of the mean, and in some embodiments ±20% of the target dimension. Within, in some embodiments within ±10% of the target size, in some embodiments within ±5% of the target size, in some embodiments within ±2% of the target size, in some embodiments within Within ±1% of the target size, and in some embodiments within ±0.1% of the target size. The terms "about" and "about" may include target dimensions. All numerical values described herein are modified by the term "about" unless otherwise specified or apparent from context.

As used herein, a range includes all values within that range. For example, a range of 1 to 10 may include any number, combination of numbers, subranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and fractions thereof.

The present invention is described in many details in the above description. It will be apparent, however, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form rather than in specific detail in order to highlight the aspects of the present invention.

The terms "first", "second", "third", "fourth", etc. used herein are labels used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

The word "example" or "demonstrative" as used herein is meant as an example, instance, or illustration. Any aspect or design described herein as an "example" or "demonstration" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the purpose of using the words "example" or "demonstrative" is to present the concept in a concrete way. In this application, the term "or" is meant to include "or", not to exclude "or". That is, unless otherwise stated or it appears from the context By the way, "X includes A or B" means any natural inclusive permutation. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. Furthermore, the terms "a" and "an" used in the patent scope of this and the appended applications shall generally be understood to mean "one or more" unless otherwise specified or clear from the context to the singular form. Reference in this specification to "one embodiment" or "an embodiment" means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "one embodiment" or "an embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

As used herein, when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present.

Although additional changes and modifications to the present invention will undoubtedly be apparent to those of ordinary skill in the art upon understanding the foregoing description, it should be understood that any specific embodiments shown and described by way of illustration should not be construed as considered to be restricted. Therefore, the details of various embodiments are not intended to limit the scope of the patent application, which itself merely describes the technical features of the present invention.

400a: Semiconductor devices

410:Substrate

420: first electrode

600b: Semiconductor devices

630: Switch oxide layer

632:Interface layer

632a: Discontinuous film

634:pore

640: Second electrode

Claims (19)

A resistive random access memory (RRAM) device, comprising: a first electrode; a first interface layer manufactured on the first electrode, wherein the first interface layer includes a first discontinuous film of a first material; A switching oxide layer fabricated on the first interface layer, wherein the switching oxide layer includes at least one transition metal oxide, and the first material has stronger properties than the at least one transition metal oxide. chemical stability; a second electrode fabricated on the switching oxide layer; wherein the first electrode includes platinum (Pt), palladium (Pd), or iridium (Ir); the first material includes Al ₂ At least one of O ₃ , MgO, Y ₂ O ₃ or La ₂ O ₃ . The RRAM device of claim 1, wherein the at least one transition metal oxide includes at least one of HfO _x or TaO _y , where x

2.0 and y

2.5. The RRAM device of claim 1, wherein the first discontinuous film of the first material includes one or more first pores, and wherein the switching oxide layer passes through at least one of the first pores. One contacts one or more portions of the first electrode. The RRAM device of claim 1, wherein the thickness of the first interface layer is between 0.2 nm and 1 nm. The RRAM device of claim 1, wherein the second electrode includes a tantalum alloy. The RRAM device of claim 5, wherein the tantalum alloy further includes at least one of hafnium, molybdenum, tungsten, niobium or zirconium. The RRAM device according to claim 6, wherein the tantalum alloy includes a binary alloy composed of tantalum, a ternary alloy composed of tantalum, a quaternary alloy composed of tantalum, a quinary alloy composed of tantalum, and a ternary alloy composed of tantalum. At least one of a six-element alloy composed of tantalum or a high-element alloy composed of tantalum. The RRAM device of claim 1, further comprising: a second interface layer between the switching oxide layer and the second electrode, wherein the second interface layer includes a second discontinuous layer of a second material. Thin film, wherein the second material has greater chemical stability than the at least one transition metal oxide. The RRAM device of claim 8, wherein the second electrode contacts at least a portion of the switching oxide layer. The RRAM device of claim 9, wherein the second material includes at least one of Al ₂ O ₃ , MgO, Y ₂ O ₃ or La ₂ O ₃ . The RRAM device of claim 9, wherein the thickness of the second interface layer is between 0.2 nm and 1 nm. The RRAM device of claim 1, wherein the second electrode includes: a first layer including a first metal material; a second layer including a second metal material, wherein the first layer is manufactured from the switching oxidation On the physical layer, the second layer is fabricated on the first layer including the first metal material. The RRAM device of claim 12, wherein the first material has stronger chemical stability than the oxide of the first metal material, and the oxide of the first metal material is more chemically stable than the at least one transition Strong metal oxides have stronger chemical stability. The RRAM device of claim 13, wherein the first metal material in the second electrode includes at least one of Ti, Hf or Zr. The RRAM device of claim 14, wherein the second metal material in the second electrode includes tantalum. The RRAM device of claim 12, wherein the thickness of the first layer including the first metal material is between 0.2 nanometers and 5 nanometers. A method of manufacturing an RRAM device, including: on a first electrode of the RRAM device, manufacturing a first interface layer including a first discontinuous film of a first material; on the first interface layer, manufacturing a first interface layer including at least one A switching oxide layer of a transition metal oxide, wherein the first material has greater chemical stability than the at least one transition metal oxide; on the switching oxide layer, a second material is produced on the switching oxide layer. A second interface layer of a second discontinuous film, wherein the second material has stronger chemical stability than the at least one transition metal oxide; on the second interface layer, a second electrode is manufactured; wherein The first electrode includes platinum (Pt), palladium (Pd), or iridium (Ir); the first material includes at least one of Al ₂ O ₃ , MgO, Y ₂ O ₃ or La ₂ O ₃ . The method of claim 17, wherein the first discontinuous film of the first material includes at least one pore, and the film including the at least one transition metal oxide is fabricated at the first interface. Switching an oxide layer includes depositing the at least one transition metal oxide on the first electrode through the at least one pore. The method of claim 17, wherein fabricating the first interface layer including the first discontinuous film of the first material on the first electrode of the RRAM device includes forming the first interface layer on the first electrode of the RRAM device. The first material is deposited on the electrode to form the first discontinuous film.