CN104465986A - Resistive memory and manufacture method thereof - Google Patents
Resistive memory and manufacture method thereof Download PDFInfo
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- CN104465986A CN104465986A CN201310424207.7A CN201310424207A CN104465986A CN 104465986 A CN104465986 A CN 104465986A CN 201310424207 A CN201310424207 A CN 201310424207A CN 104465986 A CN104465986 A CN 104465986A
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Abstract
The invention discloses a resistive memory and a manufacture method thereof. The method comprises: first of all, sequentially forming a first electrode, a variable resistance layer and a mask layer on a substrate; then, forming a dielectric layer covering the first electrode, the variable resistance layer and the mask layer on the substrate; next, performing an etching process to form an opening in the dielectric layer and the mask layer, the opening exposing a part of the variable resistance layer; afterwards, forming a second electrode in the opening, and afterwards, forming a conductive layer on the second electrode.
Description
Technical field
The invention relates to a kind of memory and preparation method thereof, and relate to a kind of resistance-type memory and manufacture method thereof especially.
Background technology
The development of resistance-type memory (such as resistive random access memory (resistive randomaccess memory, RRAM)) is in recent years very quick, is the structure of the future memory attracted most attention at present.Possess low-power consumption, working at high speed, high density due to resistance-type memory and be compatible with CMOS (Complementary Metal Oxide Semiconductor) (complementary metal oxide semiconductor, CMOS) potential advantages of technology, are therefore suitable as follow-on non-volatile memory device very much.
Existing resistance-type memory generally includes the top electrode of relative configuration and bottom electrode and the variable resistance layer between top electrode and bottom electrode, namely has general known metal-insulator-metal (MIM) structure.In general, after forming above-mentioned metal-insulator-metal structure, can prior to resistance-type memory covers one dielectric layer, and then in dielectric layer, form the opening exposing the top electrode of partial ohmic formula memory, and insert electric conducting material in opening, to make contact hole (contact).
In current technique, be generally utilize the mode of dry-etching (i.e. plasma etching) in dielectric layer, form above-mentioned opening.But in the process of dry-etching, the plasma cognition of part enters the variable resistance layer between top electrode and bottom electrode via the top electrode of resistance-type memory, and is trapped in variable resistance layer.Thus, resistance-type memory problem electrically will be caused.In addition, if utilize Wet-type etching to replace dry-etching, then easy because crossing etching (overetch) and required contact hole profile cannot be formed, and then easily cause the problem of short circuit.
Summary of the invention
The invention provides a kind of manufacture method of resistance-type memory, the electrode as top electrode is formed in contact window by it.
The present invention separately provides a kind of resistance-type memory, and its electrode as top electrode is configured in contact window.
The present invention proposes a kind of manufacture method of resistance-type memory, and it is prior to substrate sequentially forms the first electrode, variable resistance layer and mask layer.Then, in substrate, form the dielectric layer of covering first electrode, variable resistance layer and mask layer.Then, carry out etch process, in dielectric layer and mask layer, form opening, this opening exposes part variable resistance layer.Then, in opening, the second electrode is formed.Afterwards, on the second electrode, conductive layer is formed.
According to the manufacture method of the resistance-type memory described in the embodiment of the present invention, above-mentioned after formation mask layer and before formation dielectric layer, be more included in cover layer substrate being formed covering first electrode, variable resistance layer and mask layer.
According to the manufacture method of the resistance-type memory described in the embodiment of the present invention, the formation method of above-mentioned the first electrode, variable resistance layer and mask layer is such as prior to substrate sequentially forms electrode material layer, variable resistive material layer and mask layer.Afterwards, Patternized technique is carried out to electrode material layer, variable resistive material layer and mask layer.
According to the manufacture method of the resistance-type memory described in the embodiment of the present invention, above-mentioned etch process is such as dry etch process.
According to the manufacture method of the resistance-type memory described in the embodiment of the present invention, above-mentioned mask layer is such as oxide skin(coating), nitride layer, oxynitride layer, the composite bed be made up of oxide skin(coating) and nitride layer or the composite bed that is made up of oxide skin(coating) and oxynitride layer.
According to the manufacture method of the resistance-type memory described in the embodiment of the present invention, above-mentioned mask layer is such as the composite bed be made up of oxide skin(coating) and nitride layer or the composite bed be made up of oxide skin(coating) and oxynitride layer, and the formation method of opening is such as first carry out dry etch process, removes the partial nitridation nitride layer in part of dielectric layer and mask layer or oxynitride layer.Afterwards, carry out wet etch process, remove the portions of oxide layer in mask layer.
The present invention separately proposes a kind of resistance-type memory, and it comprises the first electrode, variable resistance layer, mask layer, dielectric layer, the second electrode and conductive layer.First electrode, variable resistance layer and mask layer are sequentially configured in substrate.Dielectric layer to be configured in substrate and to cover the first electrode, variable resistance layer and mask layer, has the opening exposing part variable resistance layer in its dielectric layer and mask layer.Second electrode is configured at the bottom of opening and is connected with variable resistance layer.Conductive layer is configured on the second electrode.
According to the resistance-type memory described in the embodiment of the present invention, above-mentioned mask layer is such as oxide skin(coating), nitride layer or oxynitride layer.
According to the resistance-type memory described in the embodiment of the present invention, above-mentioned mask layer is such as the composite bed be made up of oxide skin(coating) and nitride layer or the composite bed be made up of oxide skin(coating) and oxynitride layer.
According to the resistance-type memory described in the embodiment of the present invention, the composite bed that the first above-mentioned electrode is such as titanium nitride layer or is made up of titanium layer and titanium nitride layer.
According to the resistance-type memory described in the embodiment of the present invention, the composite bed that the second above-mentioned electrode is such as titanium nitride layer or is made up of titanium layer and titanium nitride layer.
According to the resistance-type memory described in the embodiment of the present invention, the material of above-mentioned variable resistance layer is such as metal oxide materials.
According to the resistance-type memory described in the embodiment of the present invention, more comprise cover layer, this cover layer to be configured in substrate and to cover the first electrode, variable resistance layer and mask layer.
According to the resistance-type memory described in the embodiment of the present invention, in above-mentioned substrate, be such as configured with contact hole, and this contact hole and the first Electrode connection.
Based on above-mentioned, the present invention, after formation variable resistance layer, first forms contact window, then form electrode in contact window.Therefore, when forming contact window with dry etch process, owing to not having conductive layer (electrode) above variable resistance layer, the plasma that dry etch process uses can't enter variable resistance layer via the conduction of the conductive layer (electrode) above variable resistance layer and be trapped in variable resistance layer.Thus, the impact final formed resistance-type memory caused electrically can effectively be avoided.
Accompanying drawing explanation
The Making programme generalized section of resistance-type memory of Figure 1A to Fig. 1 D for illustrating according to embodiments of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
[symbol description]
100: substrate
101,116: conductive layer
102,114: electrode
104: variable resistance layer
106: mask layer
106a: oxide skin(coating)
106b: nitride layer
108: cover layer
110: dielectric layer
112: opening
The Making programme generalized section of resistance-type memory of Figure 1A to Fig. 1 D for illustrating according to embodiments of the invention.First, please refer to Figure 1A, in substrate 100, sequentially form electrode 102, variable resistance layer 104 and mask layer 106.Substrate 100 is such as dielectric substrate.In addition, in substrate 100, be formed with the conductive layer 101 as contact hole, and conductive layer 101 contacts with electrode 102.The material of conductive layer 101 is such as W, Al, Cu, Pt, Ta or AlCu.The formation method of conductive layer 101 is well known to those skilled in the art, and illustrates no longer separately at this.In addition, electrode 102, variable resistance layer 104 are such as prior to substrate 100 sequentially forms electrode material layer, variable resistive material layer and mask layer with the formation method of mask layer 106, and then carry out Patternized technique to electrode material layer, variable resistive material layer and mask layer.Electrode material layer is such as tantalum nitride layer, tantalum nitride aluminium lamination, titanium nitride layer, titanium aluminum nitride layer or the composite bed that is made up of titanium layer and titanium nitride layer.Variable resistive material layer is such as high dielectric constant material layer.For example, high dielectric constant material layer can be layers of metal oxide materials.Above-mentioned metal oxide materials is such as HfO
2, TiO
2, WO
3, Al
2o
3, Ta
2o
5or ZrO
2.Or high dielectric constant material layer also can be the composite bed be made up of the metal oxide layer of above-mentioned more than two kinds.
In addition, in the present embodiment, mask layer is the composite bed be made up of two layer of material with different etching selectivity, i.e. oxide skin(coating) and the nitride layer that is located thereon.Therefore, after carrying out above-mentioned Patternized technique, namely the mask layer 106 formed is made up of oxide skin(coating) 106a and the nitride layer 106b that is located thereon.In another embodiment, above-mentioned nitride layer 106b also can be replaced oxynitride layer.The thickness of oxide skin(coating) 106a is such as between 5nm to 30nm.The thickness of nitride layer 106b is such as between 20nm to 300nm.The thickness of mask layer 106 can adjust according to the thickness of variable resistance layer 104.
Then, please refer to Figure 1B, in substrate 100, be optionally conformally formed the cover layer 108 of coated electrode 102, variable resistance layer 104 and mask layer 106.The material of cover layer 108 is such as nitride, and its thickness is such as between 10nm to 40nm.The stack architecture that cover layer 108 is made up of with mask layer 106 electrode 102, variable resistance layer 104 in order to protection.Afterwards, on cover layer 108, dielectric layer 110 is formed.Dielectric layer 110 is the interlayer dielectric layer of general common name.
Then, please refer to Fig. 1 C, carry out etch process, in dielectric layer 110, cover layer 108 and mask layer 106, form the opening 112 of exposed portion variable resistance layer 104.Opening 112 is the follow-up contact window in order to form contact hole.The formation method of opening 112 is such as carry out etch process.In detail, in the present embodiment, mask layer 106 is made up of oxide skin(coating) 106a and the nitride layer 106b that is located thereon, and dry etch process therefore can be used directly to remove part of dielectric layer 110, part of covering layer 108, partial nitridation nitride layer 106b and portions of oxide layer 106a to form opening 112.Because opening 112 exposes part variable resistance layer 104, namely there is not any conductive layer above variable resistance layer 104, therefore the plasma that dry etch process uses can't enter variable resistance layer 104 and be trapped in variable resistance layer 104 via the conduction of conductive layer, thus can avoid the impact caused final formed resistance-type memory electrically.
Special one carry be, except using dry etch process directly to remove part of dielectric layer 110, part of covering layer 108, partial nitridation nitride layer 106b and portions of oxide layer 106a to be formed except opening 112, the mode that the two-stage can also be adopted to etch is to form opening 112.In detail, dry etch process can be first used to remove part of dielectric layer 110, part of covering layer 108 and partial nitridation nitride layer 106b, and by the difference of etching selectivity between nitride layer 106b and oxide skin(coating) 106a using oxide skin(coating) 106a as the etching stopping layer of dry etch process.Then, wet etch process is used to remove the oxide skin(coating) 106a come out, to form the opening 112 exposing part variable resistance layer 104.Mode according to this, the plasma used due to dry etch process can't contact with variable resistance layer 104, therefore can more effectively avoid plasma to enter in variable resistance layer 104.In addition, because wet etch process is only used for removing oxide skin(coating) 106a, therefore can avoid causing overetched problem because etching period is long.
In the above-described embodiments, mask layer 106 is made up of oxide skin(coating) 106a and the nitride layer 106b that is located thereon.But the present invention is not limited to this.In other embodiments, mask layer 106 also can have single layer structure, and namely mask layer 106 can be oxide skin(coating), nitride layer or oxynitride layer.In the case, also can use dry etch process or use dry etch process collocation wet etch process to form opening 112.
Afterwards, please refer to Fig. 1 D, in opening 112, form electrode 114.Electrode 114 is such as be made up of titanium nitride layer, or the composite bed that electrode 114 is also made up of titanium layer and titanium nitride layer.Then, formed on electrode 114 as contact hole conductive layer 116.The material of conductive layer 116 is such as W, Ti, Al, Cu, Pt, Ta or AlCu.The formation method of conductive layer 116 is well known to those skilled in the art, and illustrates no longer separately at this.
In sum, the present invention, after formation variable resistance layer, prior to forming contact window in the interlayer dielectric layer on variable resistance layer, then forms electrode in contact window.Thus, making in the process of contact window with dry etch process, plasma can not enter in variable resistance layer via the conduction of the conductive layer (electrode) above variable resistance layer, thus can avoid the impact caused final formed resistance-type memory electrically.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. a manufacture method for resistance-type memory, is characterized in that, comprising:
The first electrode, variable resistance layer and mask layer is sequentially formed in substrate;
In described substrate, form dielectric layer, described dielectric layer covers described first electrode, described variable resistance layer and described mask layer;
Carry out etch process, in described dielectric layer and described mask layer, form opening, described opening exposes the described variable resistance layer of part;
The second electrode is formed in described opening; And
Conductive layer is formed on described second electrode.
2. the manufacture method of resistance-type memory as claimed in claim 1, wherein after the described mask layer of formation and before the described dielectric layer of formation, more be included in described substrate and form cover layer, described cover layer covers described first electrode, described variable resistance layer and described mask layer.
3. the manufacture method of resistance-type memory as claimed in claim 1, the formation method of wherein said first electrode, described variable resistance layer and described mask layer comprises:
Electrode material layer, variable resistive material layer and mask layer is sequentially formed in described substrate; And
Patternized technique is carried out to described electrode material layer, described variable resistive material layer and described mask layer.
4. the manufacture method of resistance-type memory as claimed in claim 1, wherein said etch process comprises dry etch process.
5. the manufacture method of resistance-type memory as claimed in claim 1, the composite bed that wherein said mask layer comprises oxide skin(coating), nitride layer, oxynitride layer, the composite bed be made up of oxide skin(coating) and nitride layer or is made up of oxide skin(coating) and oxynitride layer.
6. the manufacture method of resistance-type memory as claimed in claim 5, wherein said mask layer comprises the composite bed be made up of oxide skin(coating) and nitride layer or the composite bed be made up of oxide skin(coating) and oxynitride layer, and the formation method of described opening comprises:
Carry out dry etch process, remove the described nitride layer of part in the described dielectric layer of part and described mask layer or described oxynitride layer; And
Carry out wet etch process, remove the described oxide skin(coating) of part in described mask layer.
7. a resistance-type memory, is characterized in that, comprising:
Sequentially be configured at suprabasil first electrode, variable resistance layer and mask layer;
Dielectric layer, being configured in described substrate and covering described first electrode, described variable resistance layer and described mask layer, have opening in wherein said dielectric layer and described mask layer, described opening exposes the described variable resistance layer of part;
Second electrode, to be configured in described opening and to be connected with described variable resistance layer; And
Conductive layer, is configured on described second electrode.
8. resistance-type memory as claimed in claim 7, the composite bed that wherein said mask layer comprises oxide skin(coating), nitride layer, oxynitride layer, the composite bed be made up of oxide skin(coating) and nitride layer or is made up of oxide skin(coating) and oxynitride layer.
9. resistance-type memory as claimed in claim 7, the composite bed that wherein said first electrode comprises tantalum nitride layer, tantalum nitride aluminium lamination, titanium nitride layer, titanium aluminum nitride layer or is made up of titanium layer and titanium nitride layer.
10. resistance-type memory as claimed in claim 7, the composite bed that wherein said second electrode comprises tantalum nitride layer, tantalum nitride aluminium lamination, titanium nitride layer, titanium aluminum nitride layer or is made up of titanium layer and titanium nitride layer.
11. resistance-type memories as claimed in claim 7, the material of wherein said variable resistance layer comprises metal oxide materials.
12. resistance-type memories as claimed in claim 7, more comprise cover layer, and described cover layer to be configured in described substrate and to cover described first electrode, described variable resistance layer and described mask layer.
13. resistance-type memories as claimed in claim 7, are configured with contact hole in wherein said substrate, and described contact hole and described first Electrode connection.
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| TW200824046A (en) * | 2006-11-20 | 2008-06-01 | Ind Tech Res Inst | Resistive random access memory (RRAM) and method for fabricating the same |
| TW200840026A (en) * | 2007-03-29 | 2008-10-01 | Ind Tech Res Inst | Resistive random access memory and method for fabricating the same |
| US20090191367A1 (en) * | 2008-01-30 | 2009-07-30 | Industrial Technology Research Institute | Memory devices, stylus-shaped structures, electronic apparatuses, and methods for fabricating the same |
| CN102097374A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and manufacturing method thereof |
| US20120286231A1 (en) * | 2010-01-21 | 2012-11-15 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| CN103094472A (en) * | 2011-11-01 | 2013-05-08 | 无锡华润上华科技有限公司 | Manufacturing method of resistor type random access memory unit |
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2013
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200824046A (en) * | 2006-11-20 | 2008-06-01 | Ind Tech Res Inst | Resistive random access memory (RRAM) and method for fabricating the same |
| TW200840026A (en) * | 2007-03-29 | 2008-10-01 | Ind Tech Res Inst | Resistive random access memory and method for fabricating the same |
| US20090191367A1 (en) * | 2008-01-30 | 2009-07-30 | Industrial Technology Research Institute | Memory devices, stylus-shaped structures, electronic apparatuses, and methods for fabricating the same |
| CN102097374A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and manufacturing method thereof |
| US20120286231A1 (en) * | 2010-01-21 | 2012-11-15 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| CN103094472A (en) * | 2011-11-01 | 2013-05-08 | 无锡华润上华科技有限公司 | Manufacturing method of resistor type random access memory unit |
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