200840026 九、發明說明： 【發明所屬之技術領域】 本發明關於-種隨機存取記憶體，特別關於一種電阻式 機存取記憶體。 ％ 【先前技術】 積體電路設計者-直在尋求理想的半導體記憶體:一種可 隨機存取、可被迅速地讀取及寫入、非揮發性但可無限次數 f 改變且消粍很少功率之裝置。電阻式記憶體技術已日益被 提供了所有該等優點。 ’ 對於擁有雙穩定電阻轉換的過渡金屬氧化可變電随來 說，其低電阻導電路师iame顺決定餘轉換的_，因= 電阻導電路师lament)也會影響操物卿 圖，習知電阻式記憶體包含〜下電極U)、-可電變電阻、 層20完全覆蓋該下電極10、 P ；，^ 久上電極30，由圖中可丟山 電流會流經介於上及下電極間的可電變電 看出， 電變電阻介電層20與上下電朽妬# J 毛層20 ’而可 大，所產生的低電阻導電路徑所產生的範圍會t散/^_愈 該如何践阻導電雜針，改善電阻分佈，是提昇 憶體效能的關鍵。 〜何升兒阻式言己 為解決上述問題，Samsun—出—個可將電 中的新結構記憶體單元，其主要方法是將下=路傻集 小，所以可電變電阻介電層2〇盥上兩 ° 面積矣宿 4〇縮小，電阻導電路徑會集中在較小的\域内》成：疊層結構 示。然而此方法所能將電阻導電 σ弟2圖戶斥 ^5〇备目小的範圍受微影勤 0949-A21881TWF(N2)；P51950139TW；phoelip 5 200840026 與可變電阻介電層20白勺 刻能力力的限制，且下電極丨q愈々 接觸也會產生問題。 > ^國專利US20_〇27893亦揭露一種電阻式記憶體，請 參考第3a至3C目，係為該電阻式記憶體的製造方法的示意 圖。百先’如第3a圖所示，形成_圖形化下電極ιι〇於一 ^ 板’亚形成-具有一開口 130的絕緣層12〇於該下電極η〇 之上，其中該開口 130係露出該下電極110的上表面。 ▲接著，請參照第3b圖順應性形成—可電變電阻介電層14〇 方㈠亥基板1〇〇之上。接著，請參照第3c圖，蝕刻該可電變電 阻介電層140直到露出該絕緣層12〇，只時所殘存的可電變電 阻介電層140a具有-上寬下窄之凹陷145(indenta㈣。最後， 形成-上電極16G於該絕緣層12Q與可電變電阻介電層 之上，由於該上電極160係順應性形成於該具有該凹陷145 t 2變電阻介電層MOa之上，因此所形成的上電極16〇具有 一犬出尖端165(protmsion)。由於尖端放電效應，該電阻式言己 fe體可藉由該突出尖端165將電阻導電路徑限制在該尖端 附近，提昇電阻式記憶體效能。然而，在此電阻式記憶體的製 私中，由於在製作的過程中必需回蝕刻該可電變電阻介電層 140 ’如此一來，將會對元件特性造成不可預期的影響。 因此’發展出新穎的電阻式記憶體結構及製程，將電阻導 電路牷集出且克服習知技術的缺點，是目前記憶體製程技冬好一 項重要的課題。 【發明内容】 本發明之目的在於提供一電阻式記憶體，使可變電阻層令 0949-A21881 TWF(N2)；P51950139TW；phoelip 6 200840026 =電較為集中，藉此來改善操作 ^的分佈，並提供⑽的操作區間。根據本發明=實^ 例，該電阻式記憶體包括：一 ^ ^ 之上；一且古一鬥 人 基底，一下黾極，配置於該基底 二〃 # Π·^;Ι電層配置於該下電極之上，其中今開 口係露出該下電極上表面； 之下帝楠之卜，卄彻兮 出寺私大鳊，形成於讀開口内 係具有一上『毛，其中遠大出導電尖端 兮入 構，一可變電阻絕緣層，坦覆如成於 變電阻絕緣層之上。 及上包極，形戍於該可 之另-目的在於提供_種電阻式記憶 法，包括提供一基底；依續形成一 ^ ]衣以万 基底之極及一第一介電層於該 ΓΓ= 弟一開口之第二介電層於該第〜介電層 节第二=弟一開口露出該第—介電層；經由該第1 口對 =一”笔層進行一 _製程，以形成一第二開口，其中該第 大於該?—開口 ’使得該第二介電層在第二開口 '，於卜n’/相—介電層及該突懸作為罩幕，沉積一導 形成—突出導電尖端於該第二開口内之下 :;r= 電層;坦覆性形成-可變電阻絕緣層於 该弟一介電層之上並填滿該第二開口； 曰％ 該可變電阻絕緣層之上。 ，，成—電極於 以下藉由數個實施例及比較實施例，以更進200840026 IX. Description of the Invention: [Technical Field] The present invention relates to a random access memory, and more particularly to a resistive access memory. % [Prior Art] Integrated circuit designers - looking for ideal semiconductor memory: a random access, can be read and written quickly, non-volatile but infinite number of f changes and rarely Power device. Resistive memory technology has increasingly been offered with all of these advantages. For the transition metal oxide variable electric with double-stabilized resistance conversion, the low-resistance circuit breaker iame cis determines the remaining conversion _, because = resistance lead circuitator lament) will also affect the motion figure, conventional The resistive memory comprises a lower electrode U), an electrically variable resistor, a layer 20 completely covering the lower electrode 10, P, and a permanent electrode 30, and the current can flow through the upper and lower sides. It can be seen from the electrical transformation between the electrodes that the electrically variable resistor dielectric layer 20 and the upper and lower electrical decay J# J layer 20' can be large, and the range generated by the low-resistance conductive path will be scattered/^_ How to resist conductive needles and improve the resistance distribution is the key to improving the performance of the memory. ~ He Shenger resists the words to solve the above problems, Samsun - a new structure memory unit that can be used in electricity, the main method is to make the lower = road silly set small, so the electrically variable resistance dielectric layer 2 On the 两2° area, the area is reduced by 4〇, and the conductive path of the resistance is concentrated in the smaller area. However, this method can reduce the resistance of the conductive σ 弟 2 户 ^ 〇 受 受 受 受 受 949 949 949 949 949 949 949 949 949 0949-A21881TWF (N2); P51950139TW; phoelip 5 200840026 and the variable resistance dielectric layer 20 The limitation of the force, and the lower contact of the lower electrode 丨q also causes problems. A reluctance memory is also disclosed in US Pat. No. 20,037, the entire disclosure of which is incorporated herein by reference. As shown in FIG. 3a, a patterned lower electrode is formed on a board, and an insulating layer 12 having an opening 130 is formed on the lower electrode η, wherein the opening 130 is exposed. The upper surface of the lower electrode 110. ▲ Next, please refer to Figure 3b for compliant formation—the electrically variable resistor dielectric layer 14〇(1) above the substrate 1〇〇. Next, referring to FIG. 3c, the electrically variable resistor dielectric layer 140 is etched until the insulating layer 12 is exposed, and the remaining electrically variable resistor dielectric layer 140a has a wide and narrow recess 145 (indenta (4) Finally, the formation-upper electrode 16G is over the insulating layer 12Q and the electrically variable resistor dielectric layer, and the upper electrode 160 is compliantly formed on the variable resistive dielectric layer MOa having the recess 145 t 2 , The formed upper electrode 16A thus has a canine tip 165. Due to the tip discharge effect, the resistive body can restrict the resistive conductive path near the tip by the protruding tip 165, and the resistive type is lifted. Memory performance. However, in the fabrication of the resistive memory, since the electrically variable resistor dielectric layer 140 must be etched back during the fabrication process, it will have an unpredictable effect on the device characteristics. Therefore, the development of a novel resistive memory structure and process, the collection of the resistance-conducting circuit and overcoming the shortcomings of the prior art is an important issue in the current memory system. The object of the invention is to provide a resistive memory such that the variable resistance layer is 0949-A21881 TWF(N2); P51950139TW;phoelip 6 200840026=the power is concentrated, thereby improving the distribution of the operation^ and providing the operation interval of (10) According to the present invention, the resistive memory includes: a ^ ^ on top; and an ancient one-person base, a lower bungee, disposed on the base two 〃 Π · ^; Above the lower electrode, wherein the opening exposes the upper surface of the lower electrode; the lower part of the dynasty bud, the 私 兮 寺 寺 寺 寺 寺 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , a varistor, a variable resistance insulating layer, which is overlaid on the variable resistance insulating layer, and an upper cladding, which is shaped to provide a resistive memory method, including providing a substrate; a second dielectric layer is formed on the second dielectric layer of the opening and the second dielectric layer in the second dielectric layer to expose the first a dielectric layer; performing a process on the =1" pen layer via the first port to Forming a second opening, wherein the first opening is greater than the opening - such that the second dielectric layer is in the second opening ', and the n'/phase-dielectric layer and the protruding layer are used as a mask to deposit a conductive formation - Extending the conductive tip below the second opening:; r = an electrical layer; forming a variable-resistive insulating layer over the dielectric layer and filling the second opening; 曰% the variable Above the resistive insulating layer, the electrode is further improved by several embodiments and comparative examples below.
及優點’但並非用來限制本發明之範圍，tL 明之乾圍應以所附之申請專利範圍a、,、 【實施方式】 0949-A21881TWF(N2)；P51950139TW；phoelip 200840026 明 > 閱第4a圖至第4g圖，係顯示符合本發明一較佳實方包 例所述之電阻式記憶體的製造方法，其製程流程剖面圖。 首先，請參照第4a圖，提供一基板2〇〇，並形成一下電極 210於减板^〇〇之上。“基板，，一詞係包括半導體晶圓上已开） 成的το件與復盍在晶圓上的各種塗膜，其上方可以已形成任何 所需的半導體元件，不過此處為了簡化圖式，僅以平整的基板 此外，该下電極21〇可更進一步與一電晶體之 貝施例中，该下雷；):¾ 9 Λ 上 化金屬材料，例如:Pt :才貝Α可為：火金咖^ ™、Ti施、TaN、或其組合。 ΐΓ〇 接著’凊參照第4b圖，依序 ==。’其中，該第—介電層22。及該第== 材料。該第—介電層22G可為 =貫，例中’係為氧切層；該第二介電層2 二二 層，在此實施例中，係為氮化·。 為亂化物 接著，請參照第m w ,、 二介電層230之上，並㈣:圖形化光阻層240於該第 光阻層作為_罩幕圖’以該圖形化 移至該第二介電層23〇成]^弟^電層23〇，將圖形轉 230a。 形成具有—開口 232的第二介電層 接著，請參胛筮心 挪作為_:並； 〇949-A2l881TWF(N2);P51950139TW；phoelip 200840026 開口 232對該第一介電層22〇進 222，其中開口 222之尺寸大於 飯刻衣程:以形成開口 層230a在開口 222上形成突懸231。在此,2係=該第二介電 對於該第-介f層220的侧速率切賴第二 的飯刻速率的特性，來等向性姓刻_該第 曰〇, 成具有開口 222之第-介電層22〇a。 二220,形 左丄士丨也丨, 明一貫施例中，古矣 蝕刻衣程係為-等向性祕刻製程，利用第—介電 口 厂，)與第二㈣層23G(氮化物)對飿刻溶液之㈣選日擇比的(= 兴，蝕刻出該開口 222。接著，移除該光阻層24〇。 、 、接著，請參照第4fH ’順應性的沉積—導電層⑽於 述結構，由於該突懸231的關係，沉積於該開口 ^曰 霉♦ 層形成-具有下寬上窄的突出導電尖端255於該下電極2 = ^。其中，該突出導電尖端255係與該下電極21〇直接接且 連結。該導電層250(突出導電尖端255)可為耐火金屬材 料、或是抗氧化金屬材料，例如：Pt、Au、、Pd η τ τ _ g Μ、Ru、Ru〇、 (ir、ω2、顶、TlA1N、TaN、或其組合。在本發明—奸_ 施例中，該突出導電尖端255係與該下電極21〇為相同材 值得注意的是，沉積該導電層250的方法可為物理氣相沈積 (Physical Vapor Deposition, PVD)或是化風 a 4 、 • 予乳相沈積法τ (Chemical Vapor Deposition，CVD) 〇 接著，移除形成於該第二介電層230a上的導電層25〇及 該第二介電層230a。請參照第4§圖，接著，坦覆性^成一可And the advantages of the invention are not intended to limit the scope of the invention, and the scope of the invention is to be attached to the appended patent application. a,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Figure 4 to Figure 4g are cross-sectional views showing the manufacturing process of the resistive memory according to a preferred embodiment of the present invention. First, referring to Fig. 4a, a substrate 2 is provided, and a lower electrode 210 is formed on the lower plate. The "substrate," which includes the semiconductor wafer has been opened, and the various coatings embossed on the wafer, above which any desired semiconductor components can be formed, but here to simplify the drawing In addition, the flat electrode is further provided, and the lower electrode 21 can further be combined with a transistor of a transistor, the lower mine;): 3⁄4 9 上 upper metal material, for example: Pt: Α贝Α can be: Fire gold coffee ^ TM, Ti application, TaN, or a combination thereof. ΐΓ〇 then '凊 with reference to Figure 4b, in order ==. 'where the first dielectric layer 22 and the first == material. The dielectric layer 22G may be a pass, in which case 'is an oxygen cut layer; the second dielectric layer 2 is a second layer, in this embodiment, it is nitrided. For the chaotic compound, please refer to Mw, on the second dielectric layer 230, and (4): the patterned photoresist layer 240 is transferred to the second dielectric layer 23 as the _mask image in the first photoresist layer ^Electrical layer 23〇, the pattern is rotated 230a. Form a second dielectric layer having an opening 232. Next, please refer to the heart as _: and; 〇 949-A2l881TWF (N2); P51950139TW; The phoelip 200840026 opening 232 dips 222 the first dielectric layer 22, wherein the opening 222 is larger in size than the rice engraving process: the opening layer 230a is formed to form a protrusion 231 on the opening 222. Here, the 2 system = the second The dielectric is characterized by the side rate of the first f-layer 220 being dependent on the second meal rate, and isotropically etched into the first dielectric layer 22A having the opening 222. Second 220, the left-handed gentleman is also awkward, in the consistent application of the example, the ancient tantalum etching process is an isotropic secret engraving process, using the first-dielectric port factory, and the second (four) layer 23G (nitride (4) Selecting the ratio of the etching solution (=), etching the opening 222. Then, removing the photoresist layer 24, and then, refer to the 4fH 'compliant deposition-conducting layer (10) In the structure described, due to the relationship of the protrusion 231, a layer deposited on the opening is formed - a protruding conductive tip 255 having a lower width and a narrower width at the lower electrode 2 = ^. wherein the protruding conductive tip 255 is associated with The lower electrode 21 is directly connected and connected. The conductive layer 250 (the protruding conductive tip 255) may be a refractory metal material or an anti-oxidation metal. Materials such as: Pt, Au, Pd η τ τ _ g Μ, Ru, Ru 〇, (ir, ω2, TOP, TlA1N, TaN, or a combination thereof. In the present invention, the projection conductive The tip 255 is the same as the lower electrode 21, and it is worth noting that the method of depositing the conductive layer 250 may be physical Vapor Deposition (PVD) or aerobic a 4 , • Pre-emulsion deposition τ (Chemical Vapor Deposition, CVD) Next, the conductive layer 25A and the second dielectric layer 230a formed on the second dielectric layer 230a are removed. Please refer to the 4th § diagram, and then, the succinct ^ can be
變電阻絕緣層260於該第一介電層220a之上並填滿，門L 222 ’使得該可變電阻絕緣層260完全包霜兮处山 文吻大出導電尖端 0949-A21881 TWF(N2)；P51950139TWiphoelip 9 200840026 255。取後’形成-上電極層27〇於該可變電阻絕緣層之 上，至此完成本發明所述之電阻式記憶體。值得注意的是，在 喊性形成該可變電阻絕緣層26G後，可視需要利用一化學機 械研磨來對該可變電阻絕緣層26〇進行平坦化。該可變電阻絕 ^層卜可包含⑽Mn〇3(PCM〇)、SrTi〇3(ST〇)、氧化鎳、氧化 鈦、氧化給、氧化錯、氧化叙、翁 , # , ^ 、辛虱化銳、氧化鉻、氧化銅、氧 化鐵、或其組5。虹電極27()可為耐火 ^屬材料，例如··“ 、喊 ^、TlAlN、TaN、或其組合。在本發明—較佳實施例中，該 ^電極謂可與該下電極训及該突料電尖端攻為相同材 綜上料’本發私優點在於，本發明職 声 二，’具有突出導電尖端，如此可以使可變電阻:中= 徑(ma職t)較為集中，藉此來改善操作 Γ分佈，並提供足夠的操作區間。此外，本發明不需對二二 觀緣層進行任何的靖程，所以不會對可變；：::二 造核壞，^對元件效料ϋ響ΐΐ 此-電阻式記憶體。 肢製程與設備即可製作 雖然本發明已以較佳實施例揭露如上，缺 — 本發明，任何熟習此技藝者，在^、亚非用以限疋 内，當可作些呼之更動盥、 離本兔明之精神和範圍 附之申請專侧所界;準此本發明娜 09^A2l88lTWF(N2)；P5l950139TW；phoe.ip 10 200840026 【圖式簡單說明】 第1係顯示習知技 意圖。 斤述之電阻式記憶體的剖面結構六 第2係顯示另一習知技術所 構示意圖。 卩且式圮fe體的剖面結 剖面圖 =。至自知技觸叙電阻式記憶體的製作流程The variable resistance insulating layer 260 is filled on the first dielectric layer 220a, and the gate L 222 ' makes the variable resistance insulating layer 260 completely frosted. The mountain kisses the conductive tip 0949-A21881 TWF (N2) ;P51950139TWiphoelip 9 200840026 255. The post-formation-upper electrode layer 27 is placed on the variable resistance insulating layer, and thus the resistive memory of the present invention is completed. It is to be noted that after the variable resistance insulating layer 26G is formed with a sinusoidal nature, the chemically resistive polishing may be used to planarize the variable resistance insulating layer 26A. The variable resistor layer may comprise (10) Mn〇3 (PCM〇), SrTi〇3 (ST〇), nickel oxide, titanium oxide, oxidation, oxidation, oxidation, Weng, #, ^, Xinhua Sharp, chromium oxide, copper oxide, iron oxide, or a group thereof 5. The rainbow electrode 27() may be a refractory material such as ", ", ", TlAlN, TaN, or a combination thereof. In the preferred embodiment of the present invention, the electrode may be associated with the lower electrode. The power tapping of the material is the same material. The advantage of the present invention is that the voice of the present invention has a prominent conductive tip, so that the variable resistance: medium = diameter (ma position t) is concentrated. To improve the operation Γ distribution and provide sufficient operation interval. In addition, the present invention does not need to perform any tempering process on the two or two viewing layers, so it is not variable;::: two nucleus is bad, ^ is the component effect - ΐΐ ΐΐ - - - ΐΐ ΐΐ ΐΐ ΐΐ ΐΐ ΐΐ 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 肢 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然 虽然When the call can be made more ambiguous, away from the spirit and scope of the rabbit Ming, the application side of the application; the invention of this invention Na 09^A2l88lTWF (N2); P5l950139TW;phoe.ip 10 200840026 [Simple diagram] The first system shows the conventional technical intent. The cross-sectional structure of the resistive memory 6. The second system shows a schematic diagram of another conventional technique. The cross-section of the profile of the 圮fe body is a cross-sectional view = to the production process of the self-knowledge technology resistive memory
第4a至第4g係⑬員示本發明一較佳實施例所述之 憶體的製作流程剖面圖。 【主要元件符號說明】 10〜下電極； 20〜可電變電阻介電層； 30〜上電極； 40〜疊層結構； 50〜低電阻導電路徑； 100〜基板； 110〜圖形化下電極； 120〜絕緣層； 130〜開口； 140、140a〜可電變電阻介電層； 145〜凹陷； 160〜上電極； 165〜突出尖端； 200〜基板； 0949-A21881TWF(N2)；P51950139TW；phoeiip 200840026 210〜電極； 220〜第一介電層； 220a〜第一介電層； 222〜開口； 230〜第二介電層； 230a〜第二介電層； 232〜開口； 240〜圖形化光阻層； 242〜開口； 231〜突懸； 250〜導電層； 255〜突出導電尖端； 260〜可變電阻絕緣層； 270〜上電極。Sections 4a to 4g are members showing a cross-sectional view of the production process of the memory of a preferred embodiment of the present invention. [Main component symbol description] 10~ lower electrode; 20~ electrically variable resistance dielectric layer; 30~ upper electrode; 40~ laminated structure; 50~ low resistance conductive path; 100~ substrate; 110~ patterned lower electrode; 120~insulating layer; 130~opening; 140, 140a~ electrically variable resistance dielectric layer; 145~ recessed; 160~ upper electrode; 165~ protruding tip; 200~ substrate; 0949-A21881TWF(N2); P51950139TW;phoeiip 200840026 210~electrode; 220~first dielectric layer; 220a~first dielectric layer; 222~opening; 230~second dielectric layer; 230a~second dielectric layer; 232~opening; 240~graphic photoresist Layer; 242~open; 231~ overhang; 250~ conductive layer; 255~ protruding conductive tip; 260~ variable resistance insulating layer; 270~ upper electrode.
0949-A21881 TWF(N2)；P51950139TW；phoelip 120949-A21881 TWF(N2); P51950139TW;phoelip 12