TWI357149B - Resistance random access memory and fabricating me - Google Patents

Description

1357149 P51950189TW 23030twf.doc/n IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a resistive memory __^ and a method of fabricating the same, and in particular to a resistive type of -=: Γ Memory and its making method. (10) The resistive type of the metal oxide layer is generally described as follows: the positive == with the precious metal 'heart,, etc., in order to succeed (4) and the memory element characteristics that can be read and written multiple times. However, in the way of β-shell weight, as the electrode, the following important metal races may be encountered, and the resistance of the material and the underlying resistance are peeled off. The other is that the precious metal is an electrode. Clothing is an important consideration on the table. Correction, because these precious metals respond to 'making problems with the dry process" and therefore not [invention] 2 provide - electric (four) memory, can reduce the low cost, improve the depolarization, the electrode and the underlying metal oxide layer adhesion is not good problem. A resistor memory (4) method is provided to solve the problem of process integration that is difficult to etch when the metal is heavy.柽本^月 proposed a kind of resistive memory, including - the cathode end of the electromagnet ^ oxidized steel tin (extinguishing - _ also, ιτ〇) anode terminal electrode and the yttrium metal layer metal oxide layer is located at the cathode το except the extreme electrode between. /, 5 1357149 P51950189TW 23030twf.doc/n In a consistent embodiment of the invention, the cathode terminal electrode comprises Ru〇2 or Ir〇2. Alternatively, the cathode terminal electrode is one selected from the group consisting of pt, Au, pd, Ru, and mixtures thereof. In an embodiment of the invention, the metal oxide layer is a non-stoichiometric metal oxide. For example, the metal oxide of the metal oxide blanket is at least one metal oxide selected from the group consisting of TiOx, HfOx, CU〇x, Ni0x, ZrOx, NbOx, Ta〇x and La〇x. In addition, the metal oxide layer includes the above gold

It is a mixed layer or laminate of oxides. In an embodiment of the invention, the strip line is further included and electrically connected to the ITO anode terminal electrode. In the implementation of the present invention, the invention further includes a secret polar region electrically connected to the cathode terminal electrode. β The present invention further proposes a method for fabricating a resistive memory. A substrate is deposited on the substrate in sequence—a conductive layer and a layer of metal.

Γ layer ΙΤ 0 layer. The layer is made to be an extreme electrode and the metal oxide layer is patterned. Thereafter, the conductive layer is patterned to become a cathode terminal electrode. In another embodiment of the invention, the step of patterning the (10) layer is performed to form a photoresist layer on the germanium layer, and the ITO layer not covered by the photoresist layer is removed by using HBr or CH4/H2, a germanium etching gas. . In another embodiment of the present & Ming, the step of patterning the HQ layer is to form a layer of photoresist layer 're-used 2' on the layer of the red layer of the patterned HQ layer) and the mixture of the HCl is removed by the photoresist layer. 6 1357149 P51950189TW 23030twf.doc/n In another embodiment of the present invention, the step of providing the substrate comprises first forming a transistor on a dream wafer, the method comprising at least one interpole and two source/secret regions. And then overlaid on the dream wafer - the inner dielectric layer (ILD). Thereafter, a dual damascene structure is formed in the inner dielectric layer and connected to the source/nopole, and a first inner metal dielectric layer (IMD1) is overlaid on the inner layer. . Then, in the J gold, the dielectric layer towel forms a double electrode-integrated electrode bottom

Bottom electrode connector (BEC). In another embodiment, the step of patterning the conductive layer further comprises forming a second inner metal dielectric layer (thin 2) on the substrate, and forming a contact with the anode electrode at the second inner metal dielectric layer. One of the electrodes is connected to H (tQp eleetrQde __r, tec) at the top, and then a bit line connected to the electric connector is formed on the second inner gold > 8 dielectric layer. In another embodiment of the invention, the method of forming a ruthenium layer on the metal oxide layer includes frequency, vacuum evaporation or spin coating. The implementation of the material, the material of the charging layer includes ΓιΝ, Ru02 or Ir〇2. In another embodiment of the invention, the material of the conductive layer is selected from the group consisting of Pt, Au, Pd, RU, and mixtures thereof. In the other, the above-mentioned metal oxide layer is a non-chemical 十 ten-oxide. The metal oxide in the metal oxide layer, for example, 疋 is selected from the group consisting of Τ1〇χ, Hf〇x, Cu〇x, Ni〇x, Zr〇x, Nb〇x, Ta〇 盥

At least one metal oxide in LaOx. Further, the above metal oxide layer package 1357149 P51950189TW 23030twf.doc/n includes a mixed layer or a laminate of the metal oxide. Since the invention adopts 1 butyl ruthenium as the anode terminal electrode, compared with the conventional method of using the metal, it can not only reduce the cost and improve the adhesion with the underlying metal oxide layer, but also because the ιτο itself can use various methods. Etching is performed to overcome the problem of process integration that is not easily etched when using precious metals. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] Fig. 1 is a schematic cross-sectional view showing a resistive memory according to a first embodiment of the present invention. Referring to FIG. 1, the resistive memory 100 of the first embodiment is composed of a cathode end electrode 102, a ITO anode terminal electrode 1〇4, and a metal oxide layer 106, wherein the metal oxide layer 1〇6 is located in the cathode. Between the extreme electrode 102 and the ITO anode terminal electrode 104. Further, in the first embodiment, there is a source/deuterium region 108 electrically connected to the cathode terminal electrode 丨 02 and a bit line 110 electrically connected to the ιτο anode terminal electrode. Referring to FIG. 1, the source/drain region 108 of the first embodiment and the gate 114, the gate dielectric layer 116, and the spacers 118 on a germanium wafer 112 form a transistor 120. The inner layer 112 is covered with an inner dielectric layer (ILD) 122 having a dual damascene structure 124 connected to the source/drain region 108. In addition, a first inner metal dielectric layer 8 1357149 P51950189TW 23030twf.doc/n (IMD1) 126 may be interposed between the inner dielectric layer (ILD) 122 and the resistive memory 100, and the first inner metal is A bottom electrode connector (BEC) 128 in the dielectric layer 126 connects the cathode terminal electrode 102 and the dual damascene structure 124, thereby enabling the cathode terminal electrode 1〇2 to be electrically connected to the source/drain region 108. Referring to FIG. 1 again, the bit line 11 第一 in the first embodiment may be located on a first inner metal dielectric layer 126 and a resistive memory 1 的 a second inner metal dielectric layer (IMD2). The surface of the 130 is electrically connected to the IT0 anode terminal electrode by an electrode top connector (TEC) 132 in the second inner metal dielectric layer 130. In the first embodiment, the cathode terminal electrode 102 includes TiN'Ru〇2 or Ir〇2. Further, the cathode terminal electrode 102 may also be one selected from the group consisting of ptAu, pd, 2 Ru, and a mixture thereof. In the first embodiment, the metal oxide layer 106 is a non-stoichiometric metal oxide. For example, the metal oxide in the metal oxide layer 1〇6 is selected from the group consisting of Ti〇x, Hf〇x, Cu〇x, Νί〇χ, ΖΓ〇χ, Nb〇x, τ&〇χ and LaOx. At least one metal oxide. In addition, the metal oxide layer 106 may also be a mixed layer or laminate of the above metal halides, and is not limited to that shown in FIG. 2A to 2G are schematic diagrams showing a fabrication flow (four) of a resistive memory according to a second embodiment of the present invention. Please note that the method of the second embodiment is one of various types of resistive memory, mainly for explaining the manufacturing process of the resistor portion in the present invention, and the configuration of other components such as a transistor, a bit line, and the like. The manner of formation and the sequence can be made according to the techniques known in the art, and are not limited to the one described in the first embodiment of the present invention. Referring to FIG. 2A', a transistor including at least a gate 202 and two source/no-pole regions 204, 206 may be formed on a germanium wafer 200. 208 'there is also a gate dielectric layer 210 and a gap. Wall 212. • Then, referring to FIG. 2B, the germanium wafer 200 is covered with an inner dielectric layer (ILD) 214. Thereafter, a dual damascene structure (dual _ damascene; ^ 相连 is formed in the inner dielectric layer 214 respectively connected to the source/pole regions 204, 206. Then, please refer to FIG. 2C for overlaying the inner dielectric layer 214 a first inner metal dielectric layer (IMD1) 218 is formed in the first inner metal dielectric layer 218 to form a bottom electrode connector (BEC) 220 connected to one of the dual damascene structures 216. The bottom connector 220 is electrically connected to the source/drain region 2〇6 by the dual damascene structure 216. Referring to FIG. 2D on the substrate 200 (or may be on the first inner metal dielectric layer 218). A conductive layer 222, a metal oxide layer 224 and a layer 226 are sequentially deposited. The material of the conductive layer 222 is, for example,

TiN, Ru〇2 or ir〇2; in addition, the material of the conductive layer 222 may also be one selected from the group consisting of Pt Au, Pd, Ru, and a mixture thereof. The metal oxide layer 224 is a non-stoichiometric metal oxide. For example, the metal oxide in the metal oxide layer 224 is, for example, at least one X metal oxide selected from the group consisting of τί〇χ, ΗίΌχ, CuOx, NiOx, ZrOx 'NbOx, TaOx and La〇x. Moreover, the above metal oxide layer 224 may further include a mixed layer or laminate of metal oxides, and is not limited to that shown in Fig. 2D. The method for forming the IT layer 226 1357149 P51950189TW 23030twf.doc/n is, for example, a sputtering, a vacuum evaporation or a spin coating method (Spjn c〇atjng) 0 and then 'Please refer to FIG. 2E' The ITO layer 226 is patterned (Fig. 2D) to form a layer of ITO anode terminal electrode 226a. Moreover, the step of patterning the ITO layer 226 may be selected from the following two types: the first is to form a photoresist layer (not shown) on the IT layer 226, and then use the HBr* dry etching gas shift. Except for the layer 226 not covered by the photoresist layer; the second is the same

A photoresist layer (not shown) is formed on the ITO layer 226, and a mixture of HF (HF'H2 〇 2.1 〇 H2 〇) and HCl is used to remove the IT0 layer 226 which is not covered by the photoresist layer. Subsequently, referring to FIG. 2F, the metal oxide layer 224 is patterned to form the V-electrode layer 222' to become a layer cathode terminal electrode 222 & The cathode, the terminal electrode, the metal oxide layer, and the IT anode terminal electrode 226a constitute the resistive memory of the present invention.

In addition, according to FIG. 2, in order to make the IT 〇 anode terminal electrode 2 finely connected to the 兀 line, an internal metal dielectric layer (iMD2) 228 may be formed on the substrate after the step of FIG. 2F. And then the second inner metal forms an electrode top i U which is in contact with the crucible electrode 226a (top electrode connect〇r, τ 〇 = genus: the upper electrode is formed with the electrode top connector 23. =:= the current is = = Material can still be successfully executed in Figure 3 and Figure 4, where ΙΤ〇1357149 P51950J89TW 23030fwf.doc/n is formed in an honest manner. Head 3 is the current-to-voltage of the electrical memory according to this structure ^Curve=Fig. 3 may be real fairy butterfly blocking two ^ #作二图4疋 According to the invention, the IT〇/Hf〇x fine structure ^Recalling the high and low electrical distribution of the transfer pattern after the resistance conversion, the 苴汽雷阳$ J force oyster over 60 P, electric grievance low resistance state still maintains excellent area ^ = can be suitable for DC resistance writing and erasing operations.

The wiimf batch is characterized by the use of low-cost, conductive ^ ι 〇 〇 as the anode-end electrode of the resistance type, which can reduce the cost of the metal, and can improve the anode = adhesion to the underlying metal oxide layer. Good question. In addition, since IT0 has s metal to be more pure smoke, the present invention is in terms of process integration and

However, the present invention has been disclosed in the above embodiments, but it is not intended to be used in the context of the present invention. Anyone who has a general knowledge of the technical field is not allowed to do anything in the spirit and scope of the present month. The scope of protection of the present invention is defined by the scope of the appended claims. [FIG. 1] FIG. 1 is a schematic cross-sectional view showing a resistive memory according to a first embodiment of the present invention. 2A to 2G are schematic cross-sectional views showing a manufacturing process of a resistive memory according to a second embodiment of the present invention. Figure 3 is a graph of current versus voltage for a resistive type of ITO/Hf〇x/TiN structure according to the present invention, 12 1357149 P51950189TW 23030 twf.doc/n. Fig. 4 is a graph showing the distribution of high and low resistance states of a resistive memory of an ITO/HfOx/TiN structure according to the present invention. [Description of main component symbols] 100: Resistive memory 102, 222a: cathode terminal electrode 104, 226a: ITO anode terminal electrode 106, 224: metal oxide layer 108, 204, 206: source/drain region 110, 232 : bit line 112, 200: germanium wafer 114, 202: gate 116, 210: gate dielectric layer 118, 212: spacer 120, 208: transistor 122, 214: inner dielectric layer φ I24, 216: double Mosaic structure 126, 218: first inner metal dielectric layer 128, 220: electrode bottom connector 130, 228: second inner metal dielectric layer 132, 230: electrode top connector 222: conductive layer 226: ITO layer 13

Claims (1)

P51950189TW 23030twf.d〇c/n X. Patent application scope: 1. A resistive memory comprising: a cathode terminal electrode; an ITO anode terminal electrode; and a metal oxide layer located at the cathode terminal electrode and the ITO anode Extreme between the Qin and the poles. 2. The resistive memory of claim 1, wherein the cathode terminal electrode comprises TiN, Ru02 or Ir02. 3. The resistive memory of claim 1, wherein the cathode terminal electrode is one selected from the group consisting of pt, Au, Pd, Ru, and a mixture thereof. A resistive memory, wherein the metal oxide layer is a non-stoichiometric metal oxide. 5. The resistive memory according to claim 4, wherein the metal oxide in the metal oxide layer is selected from the group consisting of TiOx, HfOx, CuOx, ΝιΟχ, ZrOx, NbOx, Ding & (\ and LaOx 6. The at least one metal oxide according to claim 5, wherein the metal oxide layer comprises a mixed layer or a laminate of the metal oxide. The resistive memory further includes a one-dimensional line electrically connected to the anode electrode of the ITO. 8. The resistive memory according to claim 1, further comprising a source/drain region And electrically connected to the cathode terminal electrode. 9. A method for manufacturing a resistive memory, comprising: 1357149 P51950189TW 23030twf.doc/n providing a substrate; and forming a conductive layer on the substrate; Depositing a metal oxide layer thereon; forming an ITO layer on the metal oxide layer; patterning the ITO layer to form an IT0 anode terminal electrification; patterning the metal oxide layer; and 'patterning the conductive layer to become Cathode end Pole. 10. The method of claim 9, wherein the step of patterning the (10) layer comprises: forming a photoresist layer on the ITO layer; and using a dry form of HBr or CH4/H2 The IT0 layer covered by the etching gas migration layer. The method of patterning the ITO layer, wherein the step of patterning the ITO layer comprises: forming a photoresist layer on the IT0 layer; as well as This (10) layer covered with HF (HF: H2 〇 2: 1 〇 H2 〇) and a photoresist layer of HCl was used. The method of preparing the resistive memory according to the invention of claim 9, wherein the step of providing the substrate comprises: forming a transistor on-on-chip, the transistor being at least Including a closed pole and two source/no-polar regions; covering the germanium wafer with an inner dielectric layer; one of the regions is formed in the inner dielectric layer to be connected to the source/drain electrodes Mosaic structure; 15 1357149 P51950189TW 2303Otwf. doc/n over the inner layer; l electrical layer overlying - the first inner metal dielectric layer; and = the first inner metal dielectric layer formed with the dual damascene structure jade bottom connector ( Bott〇m electrode connector ' BEC). After the step of patterning the conductive layer in the resistor memory of the resistive memory device described in the above paragraph (4), the method further comprises: forming a second inner metal dielectric layer on the substrate; Forming a contact with the anode electrode and a top connector (TEc) in the dielectric layer; forming a connection with the electrode on the 4th inner metal dielectric layer One yuan line.丨埂,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (4) The method includes the method for producing a resistive memory as described in claim 9 wherein the material of the conductive layer comprises welcoming, such as 〇2 or '(5). The method for producing a resistive memory according to the invention of claim 9, wherein the material of the conductive layer is one selected from the group consisting of Pt and Au. The layer of the resistive memory described in Item 9 of α, κιιπ is a non-stoichiometric metal oxide. 18. The method according to claim 17, wherein the metal oxide in the metal oxide layer is selected from the group consisting of HfOx, Cu〇x, Ni〇x, ΖΓ〇χ, 啊, wind and l ton. To X less 16 1357149 P51950189TW 23030twf.doc/n A metal oxide. 19. The resistive memory of claim 18, wherein the metal oxide layer comprises a mixed layer or layer of the metal oxide. 17