TWI627773B - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer, and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of tantalum and tantalum oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.

Description

Semiconductor structure and method of forming same

The present disclosure is directed to a semiconductor structure and method of forming the same. The present disclosure relates in particular to a semiconductor structure including a memory structure and a method of forming the same.

Variable Resistive Memory (RRAM) is a type of non-volatile memory that provides a simple structure, small memory cell size, scalability, ultra-high speed operation, low power operation, and complementary metals. Oxide semiconductor (CMOS) compatibility, and low cost. The RRAM includes a memory element that can have a resistance that can be varied between two or more stable resistance ranges by applying an electrical pulse. The RRAM may further include elements such as a top electrode, a bottom electrode, and the like. The materials used to form the memory elements and other elements of the RRAM can be selected and adjusted. Thereby, a larger sensing window, longer shelf life, better durability, and/or other performance improvements can be achieved.

The present disclosure relates to improvements in memory devices, particularly for RRAM.

According to some embodiments, a semiconductor structure is provided. Such a semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer, and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of tantalum and tantalum oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.

According to some embodiments, a method of forming a semiconductor structure is provided. This method of formation includes forming a memory structure that includes the following steps. A memory element is formed. The memory element includes titanium oxynitride. A first barrier layer is formed on the memory element. The first barrier layer includes at least one of tantalum and tantalum oxide. A second barrier layer is formed on the first barrier layer. The second barrier layer includes at least one of titanium and titanium oxide.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

100,200‧‧‧ memory structure

102, 202‧‧‧ bottom electrode

104, 204‧‧‧ memory components

106, 206‧‧‧ first barrier layer

108, 208‧‧‧ second barrier layer

110, 210‧‧‧ top electrode

120, 220‧‧‧ preliminary structure

130, 230‧‧‧Optoelectronics

132, 134, 232, 234‧‧‧ heavily doped areas

136, 236‧‧ ‧ gate electrode

138, 238‧‧ ‧ thyristor

140, 142, 240, 242‧‧‧lightly doped areas

144, 244‧‧‧ substrate

146, 246‧‧‧ dielectric layer

148, 150, 248, 250‧‧‧ conductive connectors

158, 258‧‧‧ metal layer

160, 260‧‧‧ part

Section 162, 262‧‧‧

252‧‧‧Residual parts

256‧‧‧ residual parts

302, 402‧‧‧ bottom electrode material

304‧‧‧Memory component materials

306, 406‧‧‧ first barrier material

308, 408‧‧‧ second barrier material

310, 410‧‧‧ top electrode material

452‧‧‧First insulation material

454‧‧‧ openings

456‧‧‧Second insulation material

502‧‧‧ line

504‧‧‧ line

512‧‧‧ line

514‧‧‧ line

Section 4021‧‧‧

Section 4022‧‧‧

Section 4023‧‧‧

H1‧‧‧ first height

H2‧‧‧second height

W1‧‧‧ first width

W2‧‧‧ second width

W3‧‧‧ third width

FIG. 1 illustrates an exemplary semiconductor structure in accordance with an embodiment.

FIG. 2 illustrates another exemplary semiconductor structure in accordance with an embodiment.

3A-3H illustrate a method of forming an exemplary semiconductor structure according to an embodiment.

4A-4M illustrate a method of forming another exemplary semiconductor structure in accordance with an embodiment.

5A-5B illustrate electrical properties of a semiconductor structure in accordance with an embodiment.

Various embodiments will be described in more detail below with reference to the drawings. For the sake of understanding, the same element symbols are used for the same elements common to the figures in the figures. It is contemplated that elements and features of one embodiment can be advantageously incorporated into another embodiment, which is not further enumerated.

Please refer to FIG. 1, which illustrates an exemplary semiconductor structure in accordance with an embodiment. The semiconductor structure includes a memory structure 100. Although not limited thereto, the memory structure 100 is illustrated herein as an RRAM structure. The memory structure 100 includes a memory element 104, a first barrier layer 106, and a second barrier layer 108. Memory element 104 includes titanium oxynitride (TiO _x N _y ). The first barrier layer 106 includes at least one of tantalum and niobium oxide (SiO _x ). The first barrier layer 106 is disposed on the memory element 104. The second barrier layer 108 includes at least one of titanium and titanium oxide (TiO _x ). The second barrier layer 108 is disposed on the first barrier layer 106.

In particular, although not limited thereto, the entire memory element 104 may be formed of titanium oxynitride having a programmable resistor suitable for RRAM applications. The first barrier layer 106 may be formed of tantalum. Alternatively, the first barrier layer 106 may be formed of yttrium oxide. The configuration of the tantalum or yttria barrier layer is advantageous for improving the preservation of the memory structure containing TiO _x N _y . The second barrier layer 108 may be formed of titanium. Alternatively, the second barrier layer 108 may be formed of titanium oxide. Configuring titanium or titanium oxide barrier layer will help to improve the durability of the memory structure containing TiO _x N _y, and the expansion of its sensing range.

The memory structure 100 can further include a top electrode 110. The top electrode 110 may include titanium nitride (TiN _x ), for example, which is entirely formed of titanium nitride. The top electrode 110 is disposed on the second barrier layer 108. The memory structure 100 can further include a bottom electrode 102. The bottom electrode 102 may include titanium nitride, for example, which is entirely formed of titanium nitride. The memory element 104 is disposed on the bottom electrode 102.

As shown in FIG. 1, the semiconductor structure may further include a conductive connection member 150, such as a contact or a via. The conductive connector 150 can be used to couple the memory structure 100 to a corresponding access device, such as the transistor 130 shown in FIG. 3A, or a diode. The bottom electrode 102 is disposed on the conductive connector 150.

Please refer to FIG. 2, which illustrates another exemplary semiconductor structure in accordance with an embodiment. The semiconductor structure includes a memory structure 200. The memory structure 200 includes a memory element 204, a first barrier layer 206, and a second barrier layer 208. Memory element 204 includes titanium oxynitride. The first barrier layer 206 includes at least one of tantalum and tantalum oxide. The first barrier layer 206 is disposed on the memory element 204. The second barrier layer 208 includes at least one of titanium and titanium oxide. The second barrier layer 208 is disposed on the first barrier layer 206. The memory structure 200 can further include a top electrode 210. The memory structure 200 can further include a bottom electrode 202. The semiconductor structure can further include a conductive connector 250. The first barrier layer 206, the second barrier layer 208, the top electrode 210, and the conductive connection 250 may be similar to the corresponding elements shown in FIG. The semiconductor structure shown in FIG. 2 is different from the semiconductor structure shown in FIG. 1 in that the semiconductor structure shown in FIG. 2 includes a sidewall type bottom electrode 202 and a small one of the associated layers. Memory element 204. The details will be described in the following paragraphs.

The bottom electrode 202 has an L shape. In some embodiments, the bottom electrode 202 has a first width W1, and the conductive connection member 250 on which the bottom electrode 202 is disposed has a second width W2, W1/W2 < 1/2. For example, the first width W1 may be from 10 Å to 200 Å. The second width W2 can be from 1000 Å to 5000 Å. The memory element disposed on the bottom electrode 202 can also have a first width W1. Memory element 204 can have a smaller size than memory element 104, thereby facilitating the scaling of memory devices such as RRAM devices. In some embodiments, memory element 204 has a first height H1 and bottom electrode 202 has a second height H2, H1/H2 1/10.

The description now refers to the method of forming a semiconductor structure in accordance with an embodiment. Please refer to FIGS. 3A-3H for an exemplary formation method. Figures 3A-3H are depicted as forming a semiconductor structure as shown in Figure 1.

The method includes forming a memory structure 100. Prior to forming the memory structure 100, a preliminary structure 120 can be provided to enable the memory structure 100 to be formed thereon. In particular, as shown in FIG. 3A, such a preliminary structure 120 can include a conductive connector 150 in which the memory structure 100 will be formed on the conductive connector 150.

In some embodiments, shown in FIG. 3A, the preliminary structure 120 includes a transistor 130 as an access device for the memory structure 100. The transistor 130 can include two opposing heavily doped regions 132 and 134, and a gate electrode 136 and a gate dielectric 138 disposed between the heavily doped regions 132 and 134. The transistor 130 can be more Two lightly doped regions 140 and 142 are included, corresponding to heavily doped regions 132 and 134, respectively. In some embodiments, heavily doped regions 132 and 134, and lightly doped regions 140 and 142, can be n-type doped regions. The gate electrode 136 may be formed of polysilicon. The gate dielectric 138 can be formed of an oxide. The heavily doped regions 132 and 134, and the lightly doped regions 140 and 142, may be disposed in a substrate 144 of the preliminary structure 120, such as a germanium substrate. The gate electrode 136 and the gate dielectric 138 are disposed on the substrate 144, and the gate electrode 136 is disposed on the gate dielectric 138. A dielectric layer 146 of the preliminary structure 120 can be disposed over the substrate 144 and over the gate electrode 136 and the gate dielectric 138. The preliminary structure 120 can include two conductive connectors 148 and 150. Conductive connectors 148 and 150 pass through dielectric layer 146 and are connected to the two terminals of the access device. In this method, the two terminals are heavily doped regions 132 and 134.

In other embodiments, instead of transistor 130, preliminary structure 120 includes a diode (not shown), or other device suitable as an access device for memory structure 100.

Next, the memory structure 100 is formed. First, as shown in Fig. 3B, a bottom electrode material 302 can be formed on the preliminary structure 120 as shown in Fig. 3A. The bottom electrode material 302 can be, but is not limited to, titanium nitride.

As shown in FIG. 3C, a memory element material 304 is formed, for example, formed on the bottom electrode material 302. Memory element material 304 includes titanium oxynitride. However, in some embodiments, other suitable materials can be used to form one or more additional layers of the memory element. In the case where the bottom electrode material 302 is titanium nitride and the memory element material 304 is titanium oxynitride, the memory element material 304 can be oxidized by the bottom electrode material. 302 to form. The oxidation process can be an O2 plasma process, an O2 process, or an O3 process, and the like.

As shown in FIG. 3D, a first barrier material 306 is formed over the memory device material 304. The first barrier material 306 includes at least one of tantalum and tantalum oxide. For example, the first barrier material 306 can be tantalum or tantalum oxide. The first barrier material 306, which is tantalum, can be formed by a deposition process. The first barrier material 306, which is yttrium oxide, can be formed by depositing a layer of tantalum and oxidizing the layer of tantalum.

As shown in FIG. 3E, a second barrier material 308 is formed on the first barrier material 306. The second barrier material 308 includes at least one of titanium and titanium oxide. For example, the second barrier material 308 can be titanium or titanium oxide. The second barrier material 308, which is titanium, can be formed by a deposition process. The second barrier material 308, which is titanium oxide, can be formed by depositing a titanium layer and oxidizing the titanium layer.

As shown in FIG. 3F, a top electrode material 310 can be formed on the second barrier material 308. The top electrode material 310 can be, but is not limited to, titanium nitride. The top electrode material 310 can be formed by a deposition process.

Next, as shown in FIG. 3G, a patterning process can be performed to remove excess top electrode material 310, second barrier material 308, first barrier material 306, memory device material 304, and bottom electrode material 302. Thereby forming a memory structure 100. In other embodiments, the materials used for memory structure 100 may be formed sequentially only in the desired regions, thus eliminating the need for a patterning process.

After forming the memory structure 100, as shown in FIG. 3H, a metal layer 158 can be formed. The metal layer 158 can include a conductive connection 148 and A portion 160 coupled to the conductive connector 148 and a portion 162 disposed on the memory structure 100 and coupled to the memory structure 100. The metal layer 158 can be formed by a deposition process and an etching process. According to some embodiments, a conventional back end of the line (BEOL) process can then be performed.

Please refer to FIGS. 4A-4M, which illustrate a method of forming another exemplary semiconductor structure in accordance with an embodiment. Figures 4A-4M are depicted as forming a semiconductor structure as shown in Figure 2.

The method includes forming a memory structure 200. Prior to forming the memory structure 200, a preliminary structure 220 can be provided to enable the structure 200 to be formed thereon. In particular, as shown in FIG. 4A, such a preliminary structure 220 can include a conductive connector 250 in which the memory structure 200 will be formed on the conductive connector 250.

In some embodiments, as shown in FIG. 4A, the preliminary structure 220 includes a transistor 230 as an access device for the memory structure 200. The transistor 230 can include two opposing heavily doped regions 232 and 234, and a gate electrode 236 and a gate dielectric 238 disposed between the heavily doped regions 232 and 234. The transistor 230 can further include two lightly doped regions 240 and 242 corresponding to the heavily doped regions 232 and 234, respectively. In some embodiments, heavily doped regions 232 and 234, and lightly doped regions 240 and 242, can be n-type doped regions. The gate electrode 236 may be formed of polysilicon. The gate dielectric 238 can be formed of an oxide. The heavily doped regions 232 and 234, and the lightly doped regions 240 and 242, may be disposed in a substrate 244 of the preliminary structure 220, such as a germanium substrate. The gate electrode 236 and the gate dielectric 238 are disposed on the substrate 244, and the gate electrode 236 is provided Placed on the gate dielectric 238. A dielectric layer 246 of the preliminary structure 220 can be disposed over the substrate 244 and over the gate electrode 236 and the gate dielectric 238. The preliminary structure 220 can include two conductive connections 248 and 250. Conductive connectors 248 and 250 pass through dielectric layer 246 and are connected to the two terminals of the access device. In this method, the two terminals are heavily doped regions 232 and 234.

In other embodiments, instead of transistor 230, preliminary structure 220 includes a diode (not shown), or other device suitable as an access device for memory structure 200.

Next, the memory structure 200 is formed. First, a bottom electrode 202 can be formed. As shown in FIG. 4B, a first insulating material 452 can be formed on the preliminary structure 220 as shown in FIG. 4A. The first insulating material 452 can be, but is not limited to, tantalum nitride (SiN _x ). The first insulating material 452 can be formed by a deposition process. The first insulating material 452 may have a thickness of 1000 Å to 2000 Å, for example, 1500 Å.

As shown in FIG. 4C, an opening 454 is formed in the first insulating material 452. A portion of the conductive connector 250 on which the memory structure 200 will be formed is exposed by the opening 454. For example, in some embodiments, approximately half of the upper surface area of the conductive connector 250 is exposed by the opening 454. In some embodiments, the opening 454 can be formed as a groove.

As shown in FIG. 4D, a bottom electrode material 402 can be conformally formed on the first insulating material 452 having the opening 454. The bottom electrode material 402 can be, but is not limited to, titanium nitride. The bottom electrode material 402 can be formed by a deposition process such as a chemical vapor deposition (CVD) process, or Processed vapor deposition (PVD) process. The bottom electrode material 402 can have a thickness of 50 Å to 200 Å, for example, 100 Å. The thickness of the bottom electrode material 402, and the associated first width W1 of the bottom electrode 202, can be controlled by the deposition process. Next, as shown in FIG. 4E, the bottom electrode material 402 is patterned such that a residual portion of the bottom electrode material 402 has a zigzag shape including a portion 4021 located on the first insulating material 452. A portion 4022 on one of the sidewalls of the opening 454 and a portion 4023 on the bottom of one of the openings 454.

As shown in FIG. 4F, a second insulating material 456 may be formed on the remaining portions of the first insulating material 452 and the bottom electrode material 402. A second insulating material 456 is filled into the opening 454. The second insulating material 456 can be, but is not limited to, an oxide. For example, both the first insulating material 452 and the second insulating material 456 can be tantalum nitride, oxide, or other suitable insulating material. The second insulating material 456 can be formed by a deposition process such as a deposition process using tetraethoxy decane (TEOS) in the process.

As shown in FIG. 4G, a planarization process may be performed such that the (Z-shaped) residual portion of the second insulating material 456 and the bottom electrode material 402 on the first insulating material 452 is in the first position. Portion 4021 on insulating material 452 is removed. As a result, the upper surface of the bottom electrode material 402 is exposed. The planarization process can be a chemical mechanical planarization (CMP) process.

Next, as shown in Fig. 4H, a memory element 204 is formed. Memory element 204 includes titanium oxynitride. In the case where the bottom electrode material 402 is titanium nitride and the memory element 204 is titanium oxynitride, the memory element 204 can be oxidized by the bottom electrode material. Material 402 is formed. The oxidation process can be an O2 plasma process, an O2 process, or an O3 process, and the like.

The remaining portion of the bottom electrode material 402 is used as the bottom electrode 202. In some embodiments, the bottom electrode 202 has a first width W1, and the conductive connection member 250 on which the bottom electrode 202 is disposed has a second width W2, W1/W2 < 1/2. For example, the first width W1 may be from 10 Å to 200 Å. The second width W2 can be from 1000 Å to 5000 Å. Since the memory element 204 is formed by oxidizing the bottom electrode material 402, the memory element 204 can also have a first width W1. In some embodiments, memory element 204 has a first height H1 and bottom electrode 202 has a second height H2, H1/H2 1/10. The first height H1 can be controlled by adjusting conditions during the oxidation process. The sum of the first height H1 and the second height H2 may be equal to the thickness of the first insulating material 452, which may be 1000 Å to 2000 Å, for example, 1500 Å.

As shown in FIG. 4I, a first barrier material 406 is formed over the memory element 204. The first barrier material 406 includes at least one of tantalum and tantalum oxide. For example, the first barrier material 406 can be tantalum or tantalum oxide. The first barrier material 406, which is germanium, can be formed by a deposition process. The first barrier material 406, which is yttrium oxide, can be formed by depositing a layer of tantalum and oxidizing the layer of tantalum. The first barrier material 406 can have a thickness of 5 Å to 50 Å, for example, 10 Å.

As shown in FIG. 4J, a second barrier material 408 is formed on the first barrier material 406. The second barrier material 408 includes at least one of titanium and titanium oxide. For example, the second barrier material 408 can be titanium or titanium oxide. Second barrier for titanium Material 408 can be formed by a deposition process. The second barrier material 408, which is titanium oxide, can be formed by depositing a titanium layer and oxidizing the titanium layer. The second barrier material 408 can have a thickness of 5 Å to 50 Å, for example, 10 Å.

As shown in FIG. 4K, a top electrode material 410 may be formed on the second barrier material 408. The top electrode material 410 can be, but is not limited to, titanium nitride. The top electrode material 410 can be formed by a deposition process. The top electrode material 410 may have a thickness of 50 Å to 500 Å, for example, 400 Å.

As shown in FIG. 4L, a patterning process can be performed to remove excess top electrode material 410, second barrier material 408, and first barrier material 406 to form memory structure 200. In other embodiments, these materials may be formed sequentially only in the desired regions, thus eliminating the need for a patterning process. In this exemplary formation method, in addition to the bottom electrode 202 and the memory element 204, a residual portion 252 of one of the first insulating material 452 and a residual portion 256 of the second insulating material 456 are also disposed on the conductive connecting member 250 and the first Between a barrier layer 206. The memory structure 200 can have a third width W3, W3 > W2. For example, the second width W2 may be about 0.3 [mu]m and the third width W3 may be about 0.5 [mu]m.

After forming the memory structure 200, as shown in FIG. 4M, a metal layer 258 can be formed. The metal layer 258 can include a portion 260 disposed on the conductive connector 248 and coupled to the conductive connector 248, and a portion 262 disposed on the memory structure 200 and coupled to the memory structure 200. The metal layer 258 can be formed by a deposition process and an etching process. According to some embodiments, a conventional back end process can then be performed.

The semiconductor structure in accordance with the embodiments provides better memory device performance, particularly better RRAM performance. Figure 5A illustrates the electrical properties of a semiconductor structure in accordance with an embodiment wherein line 502 corresponds to a set (SET) state and line 504 corresponds to a reset (RESET) state. As shown in Figure 5A, the semiconductor structure provides a higher RESET resistance and a lower SET resistance. Therefore, a larger sensing interval (greater than 10 times) is obtained between the SET state and the RESET state. In addition, the memory structure of the semiconductor structure, such as an RRAM device, is capable of operating over a wide range of currents. This facilitates the application of an optimized operating current to improve data retention time.

Figure 5B illustrates the electrical properties of a semiconductor structure according to an embodiment after a preservative test conducted at 250 °C for 3 days, with line 102 corresponding to the SET state and line 514 corresponding to the RESET state. As shown in Figure 5B, the semiconductor structure still has a large sensing interval after the preservative test. The semiconductor structure shows good reliability.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A semiconductor structure comprising: a memory structure comprising: a memory element formed of titanium oxynitride having a programmable resistance; a first barrier layer comprising at least one of germanium and germanium oxide, the first resist The barrier layer is disposed on the memory element; and a second barrier layer includes at least one of titanium and titanium oxide, and the second barrier layer is disposed on the first barrier layer. The semiconductor structure of claim 1, wherein the memory structure further comprises a bottom electrode, the memory element being disposed on the bottom electrode. The semiconductor structure of claim 2, wherein the bottom electrode has an L-shape. The semiconductor structure of claim 2, further comprising: a conductive connecting member, wherein the bottom electrode is disposed on the conductive connecting member; wherein the bottom electrode has a first width W1, and the conductive connecting member has a The second width W2, W1/W2 < 1/2. The semiconductor structure of claim 4, wherein the first width W1 is from 10 Å to 200 Å. The semiconductor structure of claim 4, wherein the second width W2 is from 1000 Å to 5000 Å. The semiconductor structure of claim 2, wherein the memory element has a first height H1, and the bottom electrode has a second height H2, H1/H2 1/10. A method for forming a semiconductor structure, comprising: forming a memory structure, comprising: forming a memory element from titanium oxynitride, the memory element having a programmable resistor; forming a first barrier layer on the memory element, the first The barrier layer includes at least one of tantalum and tantalum oxide; and a second barrier layer is formed on the first barrier layer, the second barrier layer comprising at least one of titanium and titanium oxide. The method of forming the memory structure of claim 8, wherein the forming the memory structure further comprises: forming a bottom electrode before forming the memory element, wherein the memory element is formed on the bottom electrode; wherein the memory is formed The step of the component includes oxidizing a bottom electrode material. The method of forming the memory structure of claim 8, wherein the forming the memory structure further comprises: forming a bottom electrode before forming the memory element, wherein the memory element is formed on the bottom electrode, wherein the bottom is formed The step of forming an electrode includes: forming a first insulating material; forming an opening in the first insulating material; Forming a bottom electrode material on the first insulating material having the opening in a conformal manner; patterning the bottom electrode material such that a residual portion of the bottom electrode material has a zigzag shape including a portion of the first insulating material, a portion of the sidewall of the opening, and a portion of the bottom of the opening; forming a portion of the first insulating material and the remaining portion of the bottom electrode material a second insulating material, the second insulating material is filled into the opening; and performing a planarization process such that the second insulating material on the first insulating material and the residual portion of the bottom electrode material are in a neutral position The portion on the first insulating material is removed.