TWI550610B - Damascene process of rram top electrodes - Google Patents

Damascene process of rram top electrodes Download PDF

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Publication number
TWI550610B
TWI550610B TW104109778A TW104109778A TWI550610B TW I550610 B TWI550610 B TW I550610B TW 104109778 A TW104109778 A TW 104109778A TW 104109778 A TW104109778 A TW 104109778A TW I550610 B TWI550610 B TW I550610B
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Taiwan
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layer
opening
barrier
interlayer
access
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TW104109778A
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Chinese (zh)
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TW201635292A (en
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賴二琨
李峰旻
林昱佑
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旺宏電子股份有限公司
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Description

電阻式隨機存取記憶體頂電極之鑲嵌製程Inlay process of resistive random access memory top electrode 【0001】【0001】

本發明是有關於基於金屬氧化物之記憶體裝置及其製造方法。The present invention relates to a metal oxide based memory device and a method of fabricating the same.

【0002】【0002】

電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)是一種非揮發性記憶體的類型,提供下列優點:小的記憶胞尺寸、可擴縮性、超高速操作、低功率操作、高耐久性、好的保持性、大的開關比以及CMOS相容性。RRAM的一種類型包括金屬氧化物層,藉由施加適用於積體電路中之實施之各種程度的電脈衝,可以產生金屬氧化物層以改變二或更多穩定電阻範圍之間的電阻。Resistive Random Access Memory (RRAM) is a type of non-volatile memory that provides the following advantages: small memory cell size, scalability, ultra-high speed operation, low power operation, and high endurance. Sexuality, good retention, large switching ratio, and CMOS compatibility. One type of RRAM includes a metal oxide layer that can be created to change the electrical resistance between two or more stable resistance ranges by applying various degrees of electrical pulses suitable for implementation in an integrated circuit.

【0003】[0003]

當積體電路製造技術按比例縮小,相較於線路圖案化,用於形成RRAM之頂電極的鑲嵌製程變得較適合。RRAM記憶胞可以包括具有第一端子與第二端子的一存取裝置、接觸第一端子的一第一插塞以及接觸第二端子的一第二插塞。此存取裝置可以是電晶體或二極體。一金屬氧化層接觸第一插塞之上表面且做為RRAM記憶胞中的記憶體元件。一絕緣層係配置於第一插塞與第二插塞上,且具有對應第一插塞與第二插塞的第一開口與第二開口。於第一開口與第二開口中可以配置第一頂電極與第二頂電極,且第一頂電極與第二頂電極分別連接至位元線與源極線。As integrated circuit fabrication techniques scale down, the damascene process used to form the top electrode of the RRAM becomes more suitable than line patterning. The RRAM memory cell can include an access device having a first terminal and a second terminal, a first plug contacting the first terminal, and a second plug contacting the second terminal. This access device can be a transistor or a diode. A metal oxide layer contacts the upper surface of the first plug and acts as a memory element in the RRAM memory cell. An insulating layer is disposed on the first plug and the second plug, and has first and second openings corresponding to the first plug and the second plug. The first top electrode and the second top electrode may be disposed in the first opening and the second opening, and the first top electrode and the second top electrode are respectively connected to the bit line and the source line.

【0004】[0004]

RRAM記憶胞的製造方法中,舉例來說,於開口中形成各自的頂電極之前,係氧化第一插塞與第二插塞之上表面以形成一金屬氧化層。當第二插塞係被設計為電性連接存取裝置之第二端子至源極線,位於第二插塞之上表面的金屬氧化層將被蝕刻。然而,蝕刻位於第二開口中之第二插塞之上表面的金屬氧化層可能造成對於第二插塞的損害,導致第二插塞中較高的電阻。再者,絕緣層中的第二開口之側壁可能受到汙染。舉例來說,若第二插塞包括銅(copper, Cu)且金屬氧化層包括氧化銅(copper oxide, CuO x),蝕刻第二開口中的金屬氧化層時,銅可能被濺鍍至第二開口之側壁上。 In the manufacturing method of the RRAM memory cell, for example, before the respective top electrodes are formed in the openings, the first plug and the upper surface of the second plug are oxidized to form a metal oxide layer. When the second plug is designed to electrically connect the second terminal to the source line of the access device, the metal oxide layer on the upper surface of the second plug will be etched. However, etching the metal oxide layer on the upper surface of the second plug in the second opening may cause damage to the second plug, resulting in a higher resistance in the second plug. Furthermore, the sidewalls of the second opening in the insulating layer may be contaminated. For example, if the second plug includes copper (cop) and the metal oxide layer includes copper oxide (CuO x ), when the metal oxide layer in the second opening is etched, the copper may be sputtered to the second On the side wall of the opening.

【0005】[0005]

此外,蝕刻第二開口中的金屬氧化層時,使用抗光蝕遮罩以保護第一開口中的金屬氧化層。蝕刻之後剝離抗光蝕遮罩,剝離的過程可能損害第一開口中的金屬氧化層。Further, when etching the metal oxide layer in the second opening, a photoresist mask is used to protect the metal oxide layer in the first opening. The photoresist mask is stripped after etching, and the stripping process may damage the metal oxide layer in the first opening.

【0006】[0006]

因此,為了提供一種符合成本效益的製造方法,希望提供一種記憶胞及其製造方法,能夠消除藉由蝕刻金屬氧化層造成之連接至源極線之插塞的損害可能性以及藉由對於金屬氧化層之光阻剝離造成的損害可能性,其中金屬氧化層做為可程式電阻元件。Therefore, in order to provide a cost-effective manufacturing method, it is desirable to provide a memory cell and a method of fabricating the same that can eliminate the possibility of damage to a plug connected to a source line by etching a metal oxide layer and by oxidizing the metal The possibility of damage caused by the peeling of the layer of the photoresist, wherein the metal oxide layer acts as a programmable resistive element.

【0007】【0007】

提供記憶體的製造方法。定義對應於第一層間導體(亦稱為插塞)的第一開口,於第一開口中之第一層間導體之上表面上形成金屬氧化層,在定義對應於第二層間導體的第二開口之前沉積第一阻障材料層於第一開口中。因此,此方法消除先前技術中藉由蝕刻第二開口中之金屬氧化層所造成之對於第二層間導體的損害可能性、藉由蝕刻第二開口中之金屬氧化層所造成之對於絕緣層中第二開口之側壁的汙染可能性以及藉由光阻剝離造成之對於第一開口中之金屬氧化層的損害可能性。Provides a method of manufacturing the memory. Defining a first opening corresponding to the first interlayer conductor (also referred to as a plug), forming a metal oxide layer on the upper surface of the first interlayer conductor in the first opening, and defining a portion corresponding to the second interlayer conductor A first barrier material layer is deposited in the first opening before the opening. Therefore, the method eliminates the possibility of damage to the second interlayer conductor caused by etching the metal oxide layer in the second opening in the prior art by etching the metal oxide layer in the second opening to the insulating layer. The possibility of contamination of the sidewall of the second opening and the possibility of damage to the metal oxide layer in the first opening caused by photoresist stripping.

【0008】[0008]

於實施方案中,於層間導體之陣列上形成絕緣層。蝕刻絕緣層以定義對應陣列中第一層間導體的第一開口,其中蝕刻停止於第一層間導體的第一上表面。於第一開口中之第一層間導體之第一上表面上形成金屬氧化層。於層間導體之陣列的上表面與絕緣層之間可以形成擴散阻障層,擴散阻障層接觸上表面,以防止來自層間導體的擴散並停止位於層間導體之陣列之上表面的第一開口與第二開口之蝕刻。沉積與金屬氧化層以及第一開口之表面共形且接觸的第一阻障材料層,金屬氧化層位於第一層間導體上。藉由後續製造步驟以形成與接著移除位於金屬氧化層上的蝕刻遮罩,第一阻障材料層可以保護金屬氧化層免於電位損害,因而提供金屬氧化層與頂電極之間較佳的介面。第一開口之寬度可以大於第一層間導體之寬度。沉積第一阻障材料層之後蝕刻絕緣層以定義陣列中對應第二層間導體的第二開口,其中蝕刻停止於第二層間導體的第二上表面。沉積與第一開口中之第一阻障材料層共形且接觸的第二阻障材料層。使用導電材料填充第一開口。第一與第二層間導體係分別連接至存取裝置之第一與第二端子。In an embodiment, an insulating layer is formed on the array of interlayer conductors. The insulating layer is etched to define a first opening of the first interlayer conductor in the corresponding array, wherein the etching stops at the first upper surface of the first interlayer conductor. A metal oxide layer is formed on the first upper surface of the first interlayer conductor in the first opening. A diffusion barrier layer may be formed between the upper surface of the array of interlayer conductors and the insulating layer, and the diffusion barrier layer contacts the upper surface to prevent diffusion from the interlayer conductor and stop the first opening and the surface on the upper surface of the array of interlayer conductors Etching of the second opening. Depositing a first barrier material layer conformal and in contact with the metal oxide layer and the surface of the first opening, the metal oxide layer being on the first interlayer conductor. The first barrier material layer can protect the metal oxide layer from potential damage by a subsequent fabrication step to form and subsequently remove the etch mask on the metal oxide layer, thereby providing a better between the metal oxide layer and the top electrode. interface. The width of the first opening may be greater than the width of the first interlayer conductor. After depositing the first barrier material layer, the insulating layer is etched to define a second opening of the corresponding second interlayer conductor in the array, wherein the etching stops at the second upper surface of the second interlayer conductor. A second barrier material layer is deposited that is conformal and in contact with the first barrier material layer in the first opening. The first opening is filled with a conductive material. The first and second interlayer conducting systems are respectively connected to the first and second terminals of the access device.

【0009】【0009】

當蝕刻以定義第一開口時,可以使用第一蝕刻遮罩於絕緣層上,其中第一蝕刻遮罩具有對應第二層間導體的遮罩區域以及對應第一開口的間隔區。蝕刻以定義第二開口時,可以使用第二蝕刻遮罩於絕緣層上,其中第二蝕刻遮罩具有對應第一開口的遮罩區域以及對應第二開口的間隔區。When etching to define the first opening, a first etch mask may be used on the insulating layer, wherein the first etch mask has a mask region corresponding to the second interlayer conductor and a spacer region corresponding to the first opening. When etching to define the second opening, a second etch mask may be used on the insulating layer, wherein the second etch mask has a mask region corresponding to the first opening and a spacer region corresponding to the second opening.

【0010】[0010]

沉積與第二開口中之第二層間導體之第二上表面以及第二開口的表面共形且接觸的第二阻障材料層,亦可以使用導電材料填充第二開口,其中金屬氧化層不存在於第二上表面與第二阻障材料層之間。Depositing a second barrier material layer conformally and in contact with the second upper surface of the second interlayer conductor of the second opening and the surface of the second opening, and filling the second opening with a conductive material, wherein the metal oxide layer does not exist Between the second upper surface and the second barrier material layer.

【0011】[0011]

可以形成電性連接至金屬氧化層且可以做為位元線的第一存取線路。可以形成電性連接至第二層間導體且可以做為源極線的第二存取線路。A first access line electrically connected to the metal oxide layer and which can be used as a bit line can be formed. A second access line electrically connected to the second interlayer conductor and which can serve as a source line can be formed.

【0012】[0012]

可以形成耦合至層間導體之陣列的存取裝置陣列,存取裝置陣列包括前述的第一存取裝置。前述的第一存取裝置可以包括二極體或電晶體。於前述的第一存取裝置包括電晶體的實施例中,可以形成電性連接至電晶體之閘極端子的第三存取線路。An array of access devices coupled to an array of interlayer conductors can be formed, the access device array including the aforementioned first access device. The aforementioned first access device may comprise a diode or a transistor. In the foregoing embodiment in which the first access device comprises a transistor, a third access line electrically connected to the gate terminal of the transistor may be formed.

【0013】[0013]

金屬氧化層的特徵可以在於具有可程式的電阻。第一層間導體可以實質上由金屬所組成,而金屬氧化層可以包括金屬的氧化物。第一層間導體可以實質上由過渡金屬所組成,而金屬氧化層可以包括過渡金屬的氧化物。The metal oxide layer can be characterized by having a programmable resistance. The first interlayer conductor may consist essentially of a metal, and the metal oxide layer may comprise an oxide of a metal. The first interlayer conductor may consist essentially of a transition metal, and the metal oxide layer may comprise an oxide of a transition metal.

【0014】[0014]

藉由圖式可以理解本技術的其他方面與優點,詳細的敘述與申請專利範圍如下。Other aspects and advantages of the present technology can be understood by the drawings, and the detailed description and claims are as follows.

【0074】[0074]

100‧‧‧記憶胞
111‧‧‧第一端子
112‧‧‧第二端子
120‧‧‧介電層
131、941M、1141M、1341M‧‧‧第一層間導體
131T‧‧‧第一上表面
132、941A、941B、1141A、1141B、1341A‧‧‧第二層間導體
132T‧‧‧第二上表面
140‧‧‧擴散阻障層
150‧‧‧絕緣層
161‧‧‧第一開口
162‧‧‧第二開口
170‧‧‧金屬氧化層
180‧‧‧第一阻障層
181‧‧‧第一阻障材料層
182‧‧‧第二阻障材料層
185‧‧‧導電材料
310‧‧‧第一蝕刻遮罩
610‧‧‧第二蝕刻遮罩
900、1100、1300、1500‧‧‧RRAM陣列
901、902、903、904、1101、1102、1103、1301、1302、1303、1304、1305、1306、1307、1308、1544‧‧‧記憶胞
901A、1101A‧‧‧第一電晶體
901B、1101B‧‧‧第二電晶體
901M、1101M、1301M、1541M、1542M、1543M、1544M‧‧‧記憶元件
911、912、913、1111、1112、1113、1311、1312、1313、1314‧‧‧第一存取線路
921、922、923、1121、1122、1123、1321、1322、1323、1324‧‧‧第二存取線路
931、932、933、934、935、936、1131、1132、1133、1134、1135、1136、1331、1332、1333、1334‧‧‧第三存取線路
1301A‧‧‧電晶體
1511、1512、1513、1514‧‧‧位元線
1531、1532、1533、1534‧‧‧字元線
1544D‧‧‧二極體
1510‧‧‧位元線解碼器
1530‧‧‧字元線解碼器
1551、1552、1553、1554‧‧‧接點
1701、1702、1703、1704、1705、1706、1707‧‧‧步驟
W1、W2‧‧‧寬度
100‧‧‧ memory cells
111‧‧‧First terminal
112‧‧‧second terminal
120‧‧‧ dielectric layer
131, 941M, 1141M, 1341M‧‧‧ first interlayer conductor
131T‧‧‧ first upper surface
132, 941A, 941B, 1141A, 1141B, 1341A‧‧‧ second interlayer conductor
132T‧‧‧Second upper surface
140‧‧‧Diffusion barrier
150‧‧‧Insulation
161‧‧‧ first opening
162‧‧‧ second opening
170‧‧‧metal oxide layer
180‧‧‧First barrier layer
181‧‧‧First barrier material layer
182‧‧‧Second barrier material layer
185‧‧‧Electrical materials
310‧‧‧First etching mask
610‧‧‧Second etching mask
900, 1100, 1300, 1500‧‧‧ RRAM arrays
901, 902, 903, 904, 1101, 1102, 1103, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1544‧‧‧ memory cells
901A, 1101A‧‧‧ first transistor
901B, 1101B‧‧‧second transistor
901M, 1101M, 1301M, 1541M, 1542M, 1543M, 1544M‧‧‧ memory components
911, 912, 913, 1111, 1112, 1113, 1311, 1312, 1313, 1314‧‧‧ first access line
921, 922, 923, 1121, 1122, 1123, 1321, 1322, 1323, 1324‧‧‧ second access line
931, 932, 933, 934, 935, 936, 1131, 1132, 1133, 1134, 1135, 1136, 1331, 1332, 1333, 1334‧‧‧ third access line
1301A‧‧‧Optoelectronics
1511, 1512, 1513, 1514‧‧ ‧ bit line
1531, 1532, 1533, 1534‧‧‧ character lines
1544D‧‧‧ diode
1510‧‧‧ bit line decoder
1530‧‧‧ character line decoder
1551, 1552, 1553, 1554‧‧‧ joints
1701, 1702, 1703, 1704, 1705, 1706, 1707‧‧ steps
W1, W2‧‧‧ width

【0015】[0015]

第1圖繪示依照一實施例之記憶胞的剖面圖。
第2-8圖繪示製造如第1圖所示之記憶胞的範例步驟。
第9圖繪示依照一實施例之電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)陣列的電路圖。
第10圖繪示依照第9圖所示之實施例之記憶胞的簡化設計圖。
第11圖繪示依照第二實施例之RRAM陣列的電路圖。
第12圖繪示依照第11圖所示之第二實施例之記憶胞的簡化設計圖。
第13圖繪示依照第三實施例之RRAM陣列的電路圖。
第14圖繪示依照第13圖所示之第三實施例之記憶胞的簡化設計圖。
第15圖繪示依照使用二極體做為存取裝置之實施例之RRAM陣列的電路圖。
第16圖繪示依照第15圖所示使用二極體做為存取裝置之實施例之記憶胞的簡化設計圖。
第17圖繪示用於製造記憶體裝置之方法實施例的簡化流程圖。
1 is a cross-sectional view of a memory cell in accordance with an embodiment.
Figures 2-8 illustrate exemplary steps for fabricating a memory cell as shown in Figure 1.
FIG. 9 is a circuit diagram of a Resistive Random Access Memory (RRAM) array according to an embodiment.
Figure 10 is a simplified diagram of a memory cell in accordance with the embodiment of Figure 9.
Figure 11 is a circuit diagram of an RRAM array in accordance with a second embodiment.
Fig. 12 is a simplified diagram showing the memory cells of the second embodiment shown in Fig. 11.
Figure 13 is a circuit diagram showing an RRAM array in accordance with a third embodiment.
Fig. 14 is a view showing a simplified design of the memory cell according to the third embodiment shown in Fig. 13.
Figure 15 is a circuit diagram of an RRAM array in accordance with an embodiment using a diode as an access device.
Figure 16 is a simplified diagram of a memory cell in accordance with an embodiment of the use of a diode as an access device as shown in Figure 15.
Figure 17 is a simplified flow diagram of an embodiment of a method for fabricating a memory device.

【0016】[0016]

配合圖式提供本技術之實施例的詳細描述。應該理解的是,無意將本揭露限制到具體揭露的實施例和方法,可以使用其它特徵,元件,方法和實施例來實踐本揭露。描述較佳的實施例以說明本揭露,而不是限制其範圍,此範圍由申請專利範圍定義。本發明所屬技術領域具有通常知識者將理解到下列敘述的各種等效的變化。在各個實施例中類似的元素通常具有類似的元件符號。A detailed description of embodiments of the present technology is provided in conjunction with the drawings. It should be understood that the present disclosure is not limited to the specific embodiments and methods disclosed herein. The preferred embodiments are described to illustrate the disclosure, and not to limit the scope thereof, which is defined by the scope of the claims. Various equivalent variations to the following description will be apparent to those of ordinary skill in the art. Similar elements in various embodiments typically have similar component symbols.

【0017】[0017]

第1圖繪示依照一實施例之記憶胞(例如100)的剖面圖。於層間導體(例如131、132)之陣列上配置圖案化絕緣層(例如150)。圖案化絕緣層(例如150)包括對應陣列中之第一層間導體(例如131)之第一開口(例如161)以及對應陣列中之第二層間導體(例如132)之第二開口(例如162)。第一開口與第二開口延伸通過圖案化絕緣層,且停止於第一層間導體(例如131)之第一上表面(例如131T)與第二層間導體(例如132)之第二上表面(例如132T)。1 is a cross-sectional view of a memory cell (e.g., 100) in accordance with an embodiment. A patterned insulating layer (e.g., 150) is disposed on the array of interlayer conductors (e.g., 131, 132). The patterned insulating layer (e.g., 150) includes a first opening (e.g., 161) of a first inter-layer conductor (e.g., 131) in a corresponding array and a second opening (e.g., 162) of a second inter-layer conductor (e.g., 132) in a corresponding array. ). The first opening and the second opening extend through the patterned insulating layer and stop at a first upper surface (eg, 131T) of the first interlayer conductor (eg, 131) and a second upper surface of the second interlayer conductor (eg, 132) ( For example, 132T).

【0018】[0018]

第一層間導體(例如131)與第二層間導體(例如132)包括導電元件。舉例來說,層間導體可選自由鈦(Ti)、鎢(W)、鉬(Mo)、鋁(Al)、鉿(Hf)、鉭(Ta)、銅(Cu)、鉑(Pt)、銥(Ir)、鑭(La)、鎳(Ni)、氮(N)、氧(O)和釕(Ru)所組成之群組中的一或多種元素及其組合物,於某些實施例中可包括多於一層。於一實施方案中,第一與第二層間導體實質上可以由金屬所組成,且金屬氧化層可以包括金屬的氧化物。於另一實施方案中,第一與第二層間導體實質上可以由過渡金屬所組成,且金屬氧化層可以包括過渡金屬的氧化物。The first interlayer conductor (e.g., 131) and the second interlayer conductor (e.g., 132) include conductive elements. For example, the interlayer conductor may be selected from titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), hafnium (Hf), tantalum (Ta), copper (Cu), platinum (Pt), tantalum. One or more elements of the group consisting of (Ir), lanthanum (La), nickel (Ni), nitrogen (N), oxygen (O), and ruthenium (Ru), and combinations thereof, in some embodiments More than one layer can be included. In one embodiment, the first and second interlayer conductors may consist essentially of a metal, and the metal oxide layer may comprise an oxide of a metal. In another embodiment, the first and second interlayer conductors may consist essentially of a transition metal, and the metal oxide layer may comprise an oxide of a transition metal.

【0019】[0019]

金屬氧化層(例如170)係配置於第一層間導體(例如131)之第一上表面(例如131T)上,而金屬氧化層並未存在於第二層間導體(例如132)之第二上表面(例如132T)上。金屬氧化層的特徵可以在於具有可程式的電阻,使得金屬氧化層可程式至至少兩種電阻狀態。舉例來說,金屬氧化層可包括一或多種鎢-氧化合物(WO X),如WO 3、W 2O 5、WO 2中的一或多種。金屬氧化層可以具有包括WO 3 The metal oxide layer (eg, 170) is disposed on a first upper surface (eg, 131T) of the first interlayer conductor (eg, 131), and the metal oxide layer is not present on the second layer of the second interlayer conductor (eg, 132) On the surface (eg 132T). The metal oxide layer can be characterized by a programmable resistance such that the metal oxide layer can be programmed to at least two resistive states. For example, the metal oxide layer can include one or more tungsten-oxygen compounds (WO X ), such as one or more of WO 3 , W 2 O 5 , and WO 2 . The metal oxide layer may have a WO 3 including

、W 2O 5和WO 2的梯度圖,這樣金屬氧化層中的氧比例自第一開口(例如161)向第一層間導體(例如131)降低。 A gradient map of W 2 O 5 and WO 2 such that the proportion of oxygen in the metal oxide layer decreases from the first opening (e.g., 161) to the first interlayer conductor (e.g., 131).

【0020】[0020]

實施例中繪示,藉由氧化第一層間導體131之上表面形成之金屬氧化層170可以係單一層,因此金屬氧化層170係自對準於第一層間導體131。因為形成金屬氧化層之過程中的體積膨脹,金屬氧化層可以自第一層間導體之第一上表面突出至第一開口。於替代的實施例中,金屬氧化層170可包括其他金屬氧化物,舉例來說選自氧化鎳、氧化鋁、氧化鎂、氧化鈷、氧化鈦、氧化鈦-鎳、氧化鋯、和氧化銅群組中的金屬氧化物。In the embodiment, the metal oxide layer 170 formed by oxidizing the upper surface of the first interlayer conductor 131 may be a single layer, and thus the metal oxide layer 170 is self-aligned to the first interlayer conductor 131. The metal oxide layer may protrude from the first upper surface of the first interlayer conductor to the first opening due to volume expansion during the formation of the metal oxide layer. In an alternative embodiment, the metal oxide layer 170 may comprise other metal oxides, for example selected from the group consisting of nickel oxide, aluminum oxide, magnesium oxide, cobalt oxide, titanium oxide, titanium oxide-nickel, zirconium oxide, and copper oxide. Metal oxides in the group.

【0021】[0021]

於層間導體之陣列的上表面與圖案化絕緣層之間可以配置擴散阻障層(例如140)。擴散阻障層(例如140)可以防止來自層間導體的擴散。舉例來說,層間導體可以包括高擴散性的材料如銅(copper, Cu),這可能導致可靠度問題。擴散阻障層(例如140)可以包括氮化矽(silicon nitride, SiN)。於層間導體之陣列的上表面,擴散阻障層(例如140)亦可以停止第一開口與第二開口之蝕刻。較厚的擴散阻障層可增加RRAM記憶胞的電容,而較薄的擴散阻障層可能不足以防止來自層間導體的擴散或可能無法停止層間導體之上表面的第一與第二開口之蝕刻。於一實施例中,在10奈米(nanometer, nm)至100 nm之範圍內,擴散阻障層(例如140)可以具有約30 nm的厚度,以防止來自層間導體的擴散,同時並未造成過大的電容。A diffusion barrier layer (e.g., 140) may be disposed between the upper surface of the array of interlayer conductors and the patterned insulating layer. A diffusion barrier layer (e.g., 140) can prevent diffusion from the interlayer conductors. For example, the interlayer conductors may include highly diffusible materials such as copper (cop), which may cause reliability issues. The diffusion barrier layer (eg, 140) may comprise silicon nitride (SiN). The diffusion barrier layer (e.g., 140) may also stop etching of the first opening and the second opening on the upper surface of the array of interlayer conductors. A thicker diffusion barrier layer can increase the capacitance of the RRAM memory cell, while a thinner diffusion barrier layer may not be sufficient to prevent diffusion from the interlayer conductor or may not stop etching the first and second openings on the upper surface of the interlayer conductor. . In one embodiment, the diffusion barrier layer (eg, 140) may have a thickness of about 30 nm in the range of 10 nanometers (nm) to 100 nm to prevent diffusion from the interlayer conductors without causing Excessive capacitance.

【0022】[0022]

於第一層間導體上與第一開口之表面上,配置與金屬氧化層(例如170)共形且接觸的第一阻障層(例如180),其中第一開口之表面包括第一開口的側面與底面。第一阻障層(例如180)可以包括第一阻障材料層(例如181)以及共形且接觸第一阻障材料層的第二阻障材料層(例如182)。於一實施例中,在1 nm至50 nm之範圍內,第一阻障層的第一阻障材料層(例如181)以及第二阻障材料層(例如182)可以具有約10 nm的厚度。Disposing a first barrier layer (eg, 180) conformal and in contact with the metal oxide layer (eg, 170) on the first interlayer conductor and the surface of the first opening, wherein the surface of the first opening includes the first opening Side and bottom. The first barrier layer (eg, 180) can include a first barrier material layer (eg, 181) and a second barrier material layer (eg, 182) that conforms and contacts the first barrier material layer. In one embodiment, the first barrier material layer (eg, 181) and the second barrier material layer (eg, 182) of the first barrier layer may have a thickness of about 10 nm in the range of 1 nm to 50 nm. .

【0023】[0023]

第二阻障層可以包括第二阻障材料層(例如182),於第二開口中配置第二阻障層與第二層間導體(例如132)的第二上表面(例如132T)共形且接觸,且配置第二阻障層與第二開口之側面及底面共形且接觸。第二阻障層的厚度小於第一阻障層180的厚度。於一實施例中,包括第二阻障材料層(例如182)之第二阻障層在1 nm至50 nm之範圍內,可以具有約10 nm的厚度。The second barrier layer may include a second barrier material layer (eg, 182), the second barrier layer being disposed in the second opening being conformal to the second upper surface (eg, 132T) of the second interlayer conductor (eg, 132) Contacting, and configuring the second barrier layer to conform and contact the sides and the bottom surface of the second opening. The thickness of the second barrier layer is less than the thickness of the first barrier layer 180. In one embodiment, the second barrier layer comprising the second barrier material layer (eg, 182) may have a thickness of about 10 nm in the range of 1 nm to 50 nm.

【0024】[0024]

使用導電材料(例如185)填充第一開口,於第一開口中導電材料(例如185)接觸第一阻障層(例如180)。使用導電材料(例如185)填充第二開口,於第二開口中導電材料(例如185)接觸第二阻障層。第一阻障材料層(例如181)與第二阻障材料層(例如182)可以包括不同材料的一或多層,不同材料包括選自由鈦(Ti)、氮化鈦(TiN)、鎢(W)、鋁銅合金(AlCu)、氮化鉭(TaN)、銅(Cu)、鉿(Hf)、鉭(Ta)、金(Au)、鉑(Pt)、銀(Ag)以及其他與CMOS相容且不會造成金屬氧化層之變動電阻性質的金屬所組成的群組中的一或多種元素。The first opening is filled with a conductive material (eg, 185) in which a conductive material (eg, 185) contacts the first barrier layer (eg, 180). The second opening is filled with a conductive material (eg, 185) in which the conductive material (eg, 185) contacts the second barrier layer. The first barrier material layer (eg, 181) and the second barrier material layer (eg, 182) may comprise one or more layers of different materials including different materials selected from the group consisting of titanium (Ti), titanium nitride (TiN), tungsten (W). ), Al-Cu, Al Tan, TaN, Cu, Cu, Ta, Au, Platinum One or more elements in a group of metals that do not cause a varying resistance property of the metal oxide layer.

【0025】[0025]

第一層間導體(例如131)與第二層間導體(例如132)係分別連接至存取裝置之第一端子(例如111)與第二端子(例如112)。存取裝置之第一端子與第二端子係配置於介電層之相對於第一開口與第二開口的一側。The first interlayer conductor (e.g., 131) and the second interlayer conductor (e.g., 132) are respectively coupled to a first terminal (e.g., 111) and a second terminal (e.g., 112) of the access device. The first terminal and the second terminal of the access device are disposed on a side of the dielectric layer opposite to the first opening and the second opening.

【0026】[0026]

層間導體之陣列延伸通過介電層(例如120)。介電層(例如120)可以包括氧化物材料如電漿輔助(plasma enhanced, PE)氧化物、電漿輔助四乙氧基矽烷(plasma enhanced tetraethyl orthosilicate, PETEOS)氧化物、低壓四乙氧基矽烷(low pressure tetraethyl orthosilicate, LPTEOS)氧化物、高密度電漿(high density plasma, HDP)氧化物、硼磷矽玻璃薄膜(borophosphosilicate glass film, BPSG)、磷矽酸鹽玻璃薄膜(phosphosilicate glass film, PSG)、氟矽酸鹽玻璃薄膜(fluorosilicate glass film, FSG)、低介電常數(low k)材料等等。The array of interlayer conductors extends through a dielectric layer (e.g., 120). The dielectric layer (eg, 120) may comprise an oxide material such as a plasma enhanced (PE) oxide, a plasma enhanced tetraethyl orthosilicate (PETEOS) oxide, a low pressure tetraethoxy decane. (low pressure tetraethyl orthosilicate, LPTEOS) oxide, high density plasma (HDP) oxide, borophosphosilicate glass film (BPSG), phosphosilicate glass film (PSG) ), fluorosilicate glass film (FSG), low dielectric constant (low k) material, and the like.

【0027】[0027]

舉例來說,透過填充於第一開口中的導電材料可以電性連接第一存取線路(未繪示)至金屬氧化層,且第一存取線路可以做為記憶胞的位元線。舉例來說,透過填充於第二開口中的導電材料可以電性連接第二存取線路(未繪示)至第二層間導體,且第二存取線路可以做為記憶胞的源極線。第一存取線路與第二存取線路可以包括一或多種元素,此些元素包括鈦(Ti)、鎢(W)、鋁(Al)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉿(Hf)、鉭(Ta)以及鎳(Ni)。第一存取線路可以包括與第二存取線路相同或不同的材料。填充於第一開口(例如161)與第二開口(例如162)中的導電材料可以形成於金屬層1(ML1),而第一與第二存取線路可以形成於金屬層2、3、4或n(ML2、ML3、ML4或…MLn)。再者,第一與第二存取線路可以形成於不同的金屬層。舉例來說,第一存取線路可以形成於金屬層3(ML3),而第二存取線路可以形成於金屬層4(ML4)。For example, the first access line (not shown) can be electrically connected to the metal oxide layer through the conductive material filled in the first opening, and the first access line can be used as the bit line of the memory cell. For example, the second access line (not shown) can be electrically connected to the second interlayer conductor through the conductive material filled in the second opening, and the second access line can be used as the source line of the memory cell. The first access line and the second access line may include one or more elements including titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), tantalum nitride. (TaN), hafnium (Hf), tantalum (Ta), and nickel (Ni). The first access line may comprise the same or a different material than the second access line. A conductive material filled in the first opening (eg, 161) and the second opening (eg, 162) may be formed on the metal layer 1 (ML1), and the first and second access lines may be formed on the metal layers 2, 3, 4 Or n (ML2, ML3, ML4 or ... MLn). Furthermore, the first and second access lines may be formed in different metal layers. For example, the first access line may be formed on the metal layer 3 (ML3), and the second access line may be formed on the metal layer 4 (ML4).

【0028】[0028]

存取裝置可以包括二極體或電晶體。於存取裝置包括電晶體的一實施例中,第三存取線路(未繪示)可以電性連接至電晶體之閘極端子,且第三存取線路可以做為記憶胞之字元線。The access device can include a diode or a transistor. In an embodiment where the access device includes a transistor, the third access line (not shown) can be electrically connected to the gate terminal of the transistor, and the third access line can be used as the word line of the memory cell. .

【0029】[0029]

在操作過程中,通過金屬氧化層170與第一阻障層180,施加於第一存取線路與第一層間導體131之間的電壓將造成電流流動於第一存取線路與第一層間導體131之間。此電流可以促使金屬氧化層170之電阻中的可程式變化,此電阻表示儲存於記憶胞100中的資料值。於一些實施例中,記憶胞100之金屬氧化層170可以儲存兩個或更多位元的資料。During operation, a voltage applied between the first access line and the first interlayer conductor 131 through the metal oxide layer 170 and the first barrier layer 180 causes current to flow to the first access line and the first layer. Between the conductors 131. This current can cause a programmable change in the resistance of the metal oxide layer 170, which represents the value of the data stored in the memory cell 100. In some embodiments, the metal oxide layer 170 of the memory cell 100 can store two or more bits of data.

【0030】[0030]

第2-8圖繪示製造如第1圖所示之記憶胞的範例步驟。第2圖以剖面圖繪示形成延伸通過介電層之層間導體的陣列以及形成絕緣層(例如150)於層間導體之陣列上的結果,其中層間導體包括第一層間導體(例如131)與第二層間導體(例如132)。於實施例中,擴散阻障層(例如140)可以形成於絕緣層與介電層之間,且接觸層間導體之陣列的上表面(例如131T、132T)以停止位於層間導體之陣列上表面的第一開口與第二開口之蝕刻並保護層間導體之上表面免於氧化。介電層可以包括二氧化矽。絕緣層將被圖案化來形成記憶胞之頂電極。第一與第二層間導體係連接至存取裝置之第一端子與第二端子(例如第1圖中的111與112),其中第一端子與第二端子位於介電層之相對於絕緣層的一側。Figures 2-8 illustrate exemplary steps for fabricating a memory cell as shown in Figure 1. 2 is a cross-sectional view showing the result of forming an array of interlayer conductors extending through the dielectric layer and forming an insulating layer (eg, 150) on the array of interlayer conductors, wherein the interlayer conductor includes a first interlayer conductor (eg, 131) and A second interlayer conductor (e.g., 132). In an embodiment, a diffusion barrier layer (eg, 140) may be formed between the insulating layer and the dielectric layer and contact the upper surface of the array of interlayer conductors (eg, 131T, 132T) to stop the upper surface of the array of interlayer conductors. The first opening and the second opening are etched and protect the upper surface of the interlayer conductor from oxidation. The dielectric layer can include hafnium oxide. The insulating layer will be patterned to form the top electrode of the memory cell. The first and second interlayer conducting systems are coupled to the first terminal and the second terminal of the access device (eg, 111 and 112 in FIG. 1), wherein the first terminal and the second terminal are located opposite to the insulating layer of the dielectric layer One side.

【0031】[0031]

第3圖繪示蝕刻絕緣層以定義陣列中對應第一層間導體(例如131)的第一開口(例如161),其中蝕刻停止於第一層間導體之第一上表面(例如131T)。於形成擴散阻障層的實施例中,用以定義第一開口的蝕刻亦蝕刻通過擴散阻障層且停止於第一開口中之第一層間導體之上表面。於此製造步驟,對應層間導體之陣列中的第二層間導體的開口並不存在於絕緣層中。舉例來說,蝕刻以定義第一開口時,可以使用第一蝕刻遮罩(例如310)如抗光蝕遮罩於絕緣層上,其中第一蝕刻遮罩具有對應第二層間導體的遮罩區域以及對應第一開口(例如161)的間隔區。3 depicts an etched insulating layer to define a first opening (eg, 161) of a corresponding first interlayer conductor (eg, 131) in the array, wherein the etch stops at a first upper surface (eg, 131T) of the first interlayer conductor. In an embodiment in which the diffusion barrier layer is formed, the etch to define the first opening also etches through the diffusion barrier layer and stops at the upper surface of the first interlayer conductor in the first opening. In this manufacturing step, the opening of the second interlayer conductor in the array of corresponding interlayer conductors is not present in the insulating layer. For example, when etching to define the first opening, a first etch mask (eg, 310) such as a photoresist mask can be used on the insulating layer, wherein the first etch mask has a mask region corresponding to the second interlayer conductor And a spacer corresponding to the first opening (eg, 161).

【0032】[0032]

第4圖繪示於第一開口中之第一層間導體之第一上表面(例如131T)上形成金屬氧化層。可使用各種的沉積與氧化技術形成金屬氧化層,如快速熱氧化(Rapid Thermal Oxidation, RTO)、光氧化(photo-oxidation)、直接電漿氧化、吹式電漿(down-stream oxidation)氧化、濺鍍以及反應性濺鍍。舉例來說,使用RTO以氧化鎢(tungsten, W)或銅(copper, Cu),於氧氣或氧氣/氮氣的環境中溫度可以從200℃至1100℃,處理時間可以從5秒至500秒,典型地為30秒至60秒。於第一層間導體包括鎢(tungsten, W)的實施例中,電漿氧化可以造成具有梯度的W XO Y,其具有隨著與暴露以氧化之表面距離變動的鎢-氧化合物濃度分佈。舉例來說,金屬氧化物(例如170)可以具有包括WO 3、W 2O 5、WO 2的梯度圖,這樣金屬氧化物層中的氧比例自第一開口(例如161)向第一層間導體(例如131)降低。因為形成金屬氧化層之過程中的體積膨脹,金屬氧化層可以自第一層間導體之第一上表面突出至第一開口。 Figure 4 illustrates the formation of a metal oxide layer on the first upper surface (e.g., 131T) of the first interlayer conductor in the first opening. Metal oxide layers can be formed using a variety of deposition and oxidation techniques, such as Rapid Thermal Oxidation (RTO), photo-oxidation, direct plasma oxidation, down-stream oxidation, Sputtering and reactive sputtering. For example, using RTO as tungsten oxide (Tungsten, W) or copper (copper, Cu), in an oxygen or oxygen/nitrogen environment, the temperature can be from 200 ° C to 1100 ° C, and the processing time can be from 5 seconds to 500 seconds. Typically it is 30 seconds to 60 seconds. In an embodiment where the first interlayer conductor comprises tungsten, the plasma oxidation can result in a gradient W X O Y having a tungsten-oxygen concentration profile that varies with surface distance from exposure to oxidation. . For example, the metal oxide (eg, 170) may have a gradient map including WO 3 , W 2 O 5 , WO 2 such that the proportion of oxygen in the metal oxide layer is from the first opening (eg, 161) to the first layer The conductor (eg 131) is lowered. The metal oxide layer may protrude from the first upper surface of the first interlayer conductor to the first opening due to volume expansion during the formation of the metal oxide layer.

【0033】[0033]

使用RTO氧化技術的實施方案中,金屬氧化層在1 nm至300 nm之範圍內可以具有約50 nm的厚度。使用電漿氧化技術的另一實施方案中,金屬氧化層在1 nm至50 nm之範圍內可以具有約5 nm的厚度。In embodiments using the RTO oxidation technique, the metal oxide layer can have a thickness of about 50 nm in the range of 1 nm to 300 nm. In another embodiment using a plasma oxidation technique, the metal oxide layer can have a thickness of about 5 nm in the range of 1 nm to 50 nm.

【0034】[0034]

第5圖繪示沉積第一阻障材料層(例如181)於第一開口(例如161)中的結果,第一阻障材料層與金屬氧化層共形並接觸,且第一阻障材料層與第一開口的側面以及底面共形並接觸,其中金屬氧化層位於第一層間導體之第一上表面上。於一實施例中,第一阻障材料層(例如181)在1 nm至50 nm之範圍內,可以具有約10 nm的厚度。第一阻障材料層(例如181)可以包括不同材料的一或多層,不同材料包括選自由鈦、氮化鈦、鎢、鋁銅合金、氮化鉭、銅、鉿、鉭、金、鉑、銀以及其他與CMOS相容且不會造成金屬氧化層之變動電阻性質的金屬所組成的群組中的一或多種元素。藉由後續製造步驟以形成與接著移除位於金屬氧化層上的蝕刻遮罩,第一阻障材料層可以保護金屬氧化層免於電位損害,因而提供金屬氧化層與頂電極之間較佳的介面。Figure 5 illustrates the deposition of a first barrier material layer (e.g., 181) in a first opening (e.g., 161), the first barrier material layer conforming to and in contact with the metal oxide layer, and the first barrier material layer And conforming and contacting the side surface and the bottom surface of the first opening, wherein the metal oxide layer is located on the first upper surface of the first interlayer conductor. In one embodiment, the first barrier material layer (eg, 181) may have a thickness of about 10 nm in the range of 1 nm to 50 nm. The first barrier material layer (eg, 181) may comprise one or more layers of different materials including different materials selected from the group consisting of titanium, titanium nitride, tungsten, aluminum copper alloy, tantalum nitride, copper, ruthenium, iridium, gold, platinum, One or more elements of the group consisting of silver and other metals that are compatible with CMOS and do not cause the varying resistance properties of the metal oxide layer. The first barrier material layer can protect the metal oxide layer from potential damage by a subsequent fabrication step to form and subsequently remove the etch mask on the metal oxide layer, thereby providing a better between the metal oxide layer and the top electrode. interface.

【0035】[0035]

第一開口的最小寬度基於製造技術。第一開口(例如161)的寬度(例如W1)可以大於第一層間導體(例如131)的寬度(例如W2)。舉例來說,若第一層間導體包括鎢(tungsten, W)且具有約100 nm的寬度,則第一開口可以具有大於120 nm的寬度。The minimum width of the first opening is based on manufacturing techniques. The width of the first opening (eg, 161) (eg, W1) may be greater than the width of the first interlayer conductor (eg, 131) (eg, W2). For example, if the first interlayer conductor includes tungsten (tungsten, W) and has a width of about 100 nm, the first opening may have a width greater than 120 nm.

【0036】[0036]

第6圖繪示蝕刻絕緣層(例如150)以定義對應層間導體之陣列中的第二層間導體(例如132)的第二開口(例如162),其中蝕刻停止於第二層間導體之第二上表面(例如132T)。沉積如第5圖所示之第一阻障材料層之後進行用以定義第二開口的此蝕刻步驟,且蝕刻通過第一阻障材料層(例如181)。形成擴散阻障層的實施例中,用以定義第二開口的蝕刻亦蝕刻通過擴散阻障層,且停止於第二開口中之第二層間導體之上表面。於一實施方案中,第二開口(例如162)的寬度可以匹配第一開口(例如161)的寬度。Figure 6 illustrates an etched insulating layer (e.g., 150) to define a second opening (e.g., 162) of a second interlayer conductor (e.g., 132) in an array of corresponding interlayer conductors, wherein etching stops on the second of the second interlayer conductors Surface (eg 132T). This etching step for defining the second opening is performed after depositing the first barrier material layer as shown in FIG. 5, and etching through the first barrier material layer (eg, 181). In an embodiment in which the diffusion barrier layer is formed, an etch to define the second opening is also etched through the diffusion barrier layer and stops at the upper surface of the second interlayer conductor in the second opening. In an embodiment, the width of the second opening (eg, 162) can match the width of the first opening (eg, 161).

【0037】[0037]

於第二層間導體之第二上表面上形成金屬氧化層的先前方法中,需藉由製程如濺鍍移除金屬氧化層,因而可能造成絕緣層中第二開口之側壁的汙染。舉例來說,若第二層間導體包括銅(copper, Cu)且金屬氧化層包括氧化銅(CuO x),移除金屬氧化層時,銅可能被濺鍍至第二開口之側壁上。 In the prior method of forming a metal oxide layer on the second upper surface of the second interlayer conductor, the metal oxide layer is removed by a process such as sputtering, which may cause contamination of the sidewall of the second opening in the insulating layer. For example, if the second interlayer conductor comprises copper (copper, Cu) and the metal oxide layer comprises copper oxide (CuO x), removal of the metal oxide layer, the copper may be sputtered onto the sidewalls of the second opening.

【0038】[0038]

於本技術之實施例中,因為金屬氧化層並不存在於第二層間導體(例如132)之第二上表面(例如132T)上且蝕刻停止於第二層間導體(例如132)之第二上表面(例如132T),伴隨著先前方法可能發生之絕緣層中第二開口之側壁的汙染可以被降到最低。In an embodiment of the present technology, since the metal oxide layer is not present on the second upper surface (eg, 132T) of the second interlayer conductor (eg, 132) and the etch stops on the second of the second interlayer conductor (eg, 132) The surface (e.g., 132T), with the contamination of the sidewalls of the second opening in the insulating layer that may have occurred with previous methods, can be minimized.

【0039】[0039]

用以定義第二開口之製造步驟中,可以使用第二蝕刻遮罩(例如610)如抗光蝕遮罩於絕緣層(例如150)與第一阻障材料層(例如181)上,其中第二蝕刻遮罩具有對應第一開口(例如161)的遮罩區域以及對應第二開口(例如162)的間隔區。因此,於此製造步驟中,藉由第一阻障材料層與第二蝕刻遮罩中的遮罩區域保護第一開口中的金屬氧化層(例如170)。In the manufacturing step for defining the second opening, a second etch mask (eg, 610) such as a photoresist mask may be used on the insulating layer (eg, 150) and the first barrier material layer (eg, 181), wherein The second etch mask has a mask region corresponding to the first opening (eg, 161) and a spacer region corresponding to the second opening (eg, 162). Thus, in this fabrication step, the metal oxide layer (e.g., 170) in the first opening is protected by the first barrier material layer and the mask region in the second etch mask.

【0040】[0040]

第7圖繪示使用第二蝕刻遮罩定義第二開口(例如162)之後,剝離如第6圖所示之第二蝕刻遮罩(例如610)的結果。剝離過程中,藉由第一阻障材料層(例如181)保護第一開口中的金屬氧化層(例如170)。FIG. 7 illustrates the result of stripping the second etch mask (eg, 610) as shown in FIG. 6 after defining the second opening (eg, 162) using the second etch mask. During the stripping process, the metal oxide layer (e.g., 170) in the first opening is protected by a first barrier material layer (e.g., 181).

【0041】[0041]

沉積第二阻障材料層的預備過程中,通過使用自氣體物質產生之有能量的電漿,可以使用電漿清潔以自第二層間導體之第二上表面(例如132T)移除雜質、汙染物以及天然的氧化物。舉例來說,氣體物質可以包括氬氣,且電漿清潔可以蝕刻自約1 nm至20 nm的深度。電漿清潔過程中,藉由第一阻障材料層(例如181)保護第一開口中的金屬氧化層(例如170)。During the preparation of the second barrier material layer, by using an energetic plasma generated from the gaseous species, plasma cleaning can be used to remove impurities, contamination from the second upper surface of the second interlayer conductor (eg, 132T). And natural oxides. For example, the gaseous species can include argon, and the plasma cleaning can be etched from a depth of from about 1 nm to 20 nm. During the plasma cleaning process, the metal oxide layer (e.g., 170) in the first opening is protected by a first barrier material layer (e.g., 181).

【0042】[0042]

第8圖繪示於第一開口與第二開口中沉積第二阻障材料層(例如182)的結果。第一開口中之第二阻障材料層與第一阻障材料層(例如181)共形且接觸,第二開口中之第二阻障材料層與第二層間導體之第二上表面(例如132T) 共形且接觸,且第二阻障材料層與第二開口的側面以及底面共形且接觸。於一實施例中,第二阻障材料層(例如182)在1 nm至50 nm之範圍內,可以具有約10 nm的厚度。第一阻障材料層(例如181)與第二阻障材料層(例如182)可以包括不同材料的一或多層,不同材料包括選自由鈦、氮化鈦、鎢、鋁銅合金、氮化鉭、銅、鉿、鉭、金、鉑、銀以及其他與CMOS相容且不會造成金屬氧化層之變動電阻性質的金屬所組成的群組中的一或多種元素。Figure 8 illustrates the result of depositing a second barrier material layer (e.g., 182) in the first opening and the second opening. The second barrier material layer in the first opening is conformal and in contact with the first barrier material layer (eg, 181), the second barrier material layer of the second opening and the second upper surface of the second interlayer conductor (eg 132T) conformal and in contact, and the second barrier material layer conforms and contacts the sides and bottom surface of the second opening. In one embodiment, the second barrier material layer (eg, 182) may have a thickness of about 10 nm in the range of 1 nm to 50 nm. The first barrier material layer (eg, 181) and the second barrier material layer (eg, 182) may comprise one or more layers of different materials, including different materials selected from the group consisting of titanium, titanium nitride, tungsten, aluminum copper alloy, tantalum nitride. One or more elements of the group consisting of copper, ruthenium, rhodium, gold, platinum, silver, and other metals that are compatible with CMOS and do not cause the varying resistance properties of the metal oxide layer.

【0043】[0043]

接著可以填充導電材料(例如185)於第一開口以及第二開口中。舉例來說,透過填充於第一開口中的導電材料可以形成電性連接至金屬氧化層的第一存取線路(未繪示),且第一存取線路可以做為記憶胞的位元線。舉例來說,透過填充於第二開口中的導電材料可以形成電性連接至第二層間導體的第二存取線路(未繪示),且第二存取線路可以做為記憶胞的源極線。填充於第一開口(例如161)與第二開口(例如162)中的導電材料可以形成於金屬層1(ML1),而第一與第二存取線路可以形成於金屬層2、3、4或n(ML2、ML3、ML4或…MLn)。再者,第一與第二存取線路可以形成於不同的金屬層。舉例來說,第一存取線路可以形成於金屬層3(ML3),而第二存取線路可以形成於金屬層4(ML4)。A conductive material (eg, 185) can then be filled in the first opening and the second opening. For example, a first access line (not shown) electrically connected to the metal oxide layer may be formed through the conductive material filled in the first opening, and the first access line may be used as a bit line of the memory cell. . For example, a second access line (not shown) electrically connected to the second interlayer conductor can be formed through the conductive material filled in the second opening, and the second access line can be used as the source of the memory cell. line. A conductive material filled in the first opening (eg, 161) and the second opening (eg, 162) may be formed on the metal layer 1 (ML1), and the first and second access lines may be formed on the metal layers 2, 3, 4 Or n (ML2, ML3, ML4 or ... MLn). Furthermore, the first and second access lines may be formed in different metal layers. For example, the first access line may be formed on the metal layer 3 (ML3), and the second access line may be formed on the metal layer 4 (ML4).

【0044】[0044]

第9圖繪示依照一實施例之電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)陣列的電路圖。RRAM 陣列900包括記憶胞(例如901、902、903)的列與欄,其中各記憶胞包括第一電晶體(例如901A)、第二電晶體(例如901B)以及連接至位元線的記憶元件(例如901M)。第一與第二電晶體可以係N型金氧半導體(N-type metal oxide semiconductor, NMOS)電晶體。記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示金屬氧化層170上的第一阻障材料層181與第二阻障材料層182。記憶胞中之第一與第二電晶體的第一端子係連接至記憶胞中記憶元件的一端。繪示的三個記憶胞901、902與903表示記憶體陣列的一個小區塊,記憶體陣列可以包括數千或數百萬的記憶胞。FIG. 9 is a circuit diagram of a Resistive Random Access Memory (RRAM) array according to an embodiment. The RRAM array 900 includes columns and columns of memory cells (e.g., 901, 902, 903), wherein each memory cell includes a first transistor (e.g., 901A), a second transistor (e.g., 901B), and a memory element coupled to the bit line. (eg 901M). The first and second transistors may be N-type metal oxide semiconductor (NMOS) transistors. The memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer 170 as shown in FIG. A first terminal of the first and second transistors in the memory cell is coupled to one end of the memory element in the memory cell. The three memory cells 901, 902, and 903 are shown as one block of the memory array, and the memory array may include thousands or millions of memory cells.

【0045】[0045]

多個第一存取線路(例如911、912與913)沿著第一方向延伸且與位元線解碼器(未繪示)以及記憶胞之記憶元件電性通訊。通過配置於記憶元件(例如901M)下的第一層間導體(例如941M),記憶胞中之記憶元件的一端係連接至多個第一存取線路中的一第一存取線路,而另一端連接至記憶胞中之第一與第二電晶體的第一端子。第一層間導體(例如131)的剖面圖係繪示於第8圖中。多個第一存取線路可以做為位元線。A plurality of first access lines (eg, 911, 912, and 913) extend in a first direction and are in electrical communication with a bit line decoder (not shown) and a memory element of the memory cell. One end of the memory element in the memory cell is connected to a first one of the plurality of first access lines, and the other end is connected by a first interlayer conductor (eg, 941M) disposed under the memory element (eg, 901M) Connected to the first terminals of the first and second transistors in the memory cell. A cross-sectional view of the first interlayer conductor (e.g., 131) is shown in FIG. A plurality of first access lines can be used as bit lines.

【0046】[0046]

多個第二存取線路(例如921、922與923)沿著第一方向延伸,且終止於源極線終端電路(未繪示)。通過第二層間導體(例如941A與941B),第二存取線路(例如921)與記憶胞中之第一與第二電晶體(例如901A與901B)的第二端子電性通訊。第二層間導體(例如132)的剖面圖係繪示於第8圖中。多個第二存取線路可以做為源極線。A plurality of second access lines (eg, 921, 922, and 923) extend in a first direction and terminate in a source line termination circuit (not shown). A second access line (e.g., 921) is in electrical communication with a second terminal of the first and second transistors (e.g., 901A and 901B) in the memory cell by a second interlayer conductor (e.g., 941A and 941B). A cross-sectional view of the second interlayer conductor (e.g., 132) is shown in FIG. A plurality of second access lines can be used as source lines.

【0047】[0047]

多個第三存取線路(例如931至936)沿著正交於第一方向的第二方向延伸。第三存取線路與字元線解碼器(未繪示)電性通訊,且可以做為字元線。記憶胞中之第一與第二電晶體(例如901A與901B)的閘極端子係各自連接至第三存取線路。位元線解碼器與字元線解碼器可以包括互補式金氧半導體(Complementary Metal Oxide Semiconductor, CMOS)電路。A plurality of third access lines (eg, 931 through 936) extend along a second direction that is orthogonal to the first direction. The third access line is in electrical communication with a word line decoder (not shown) and can be used as a word line. The gate terminals of the first and second transistors (e.g., 901A and 901B) in the memory cell are each connected to a third access line. The bit line decoder and word line decoder may comprise complementary metal oxide semiconductor (CMOS) circuits.

【0048】[0048]

第10圖繪示依照第9圖所示實施例之記憶胞的簡化設計圖。以與第9圖中相似的元件符號表示第10圖中相似的元件。記憶胞的佈局可以在垂直與水平方向重複。為了簡化,並未繪示絕緣材料,舉例來說,位於第一、第二與第三存取線路之間的絕緣材料。Figure 10 is a simplified diagram of a memory cell in accordance with the embodiment of Figure 9. Similar elements in Fig. 10 are denoted by like reference numerals in Fig. 9. The layout of the memory cells can be repeated in the vertical and horizontal directions. For the sake of simplicity, the insulating material is not shown, for example, an insulating material between the first, second and third access lines.

【0049】[0049]

此設計圖繪示第一存取線路911與912做為位元線(Bit Lines, BL)、第二存取線路921與922做為源極線(Source Lines, SL),第三存取線路931、932與933做為字元線(Word Lines, WL)。於一實施方案中,於金屬層1中可以配置第一存取線路與第二存取線路。第一、第二與第三存取線路係連接至記憶胞(例如901與904),如第9圖所描述。記憶胞包括記憶元件(例如901M),記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示金屬氧化層上的第一阻障材料層181與第二阻障材料層182。The design shows the first access lines 911 and 912 as bit lines (BL), the second access lines 921 and 922 as source lines (SL), and the third access line. 931, 932 and 933 are used as word lines (WL Line). In an embodiment, the first access line and the second access line may be disposed in the metal layer 1. The first, second and third access lines are connected to memory cells (e.g., 901 and 904) as described in FIG. The memory cell includes a memory element (e.g., 901M) and the memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG.

【0050】[0050]

第11圖繪示依照第二實施例之電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)陣列的電路圖。RRAM 陣列1100包括記憶胞(例如1101、1102與1103)的列與欄,其中各記憶胞包括第一電晶體(例如1101A)、第二電晶體(例如1101B)以及記憶元件(例如1101M)。第一與第二電晶體可以係N型金氧半導體(N-type metal oxide semiconductor, NMOS)電晶體。記憶胞可以包括如第1圖所示記憶元件上的第一阻障材料層181與第二阻障材料層182。記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞中之第一與第二電晶體的第一端子係連接至記憶胞中記憶元件的一端,而記憶胞中第一與第二電晶體的第二端子係連接至源極線(例如1121)。繪示的三個記憶胞1101、1102與1103表示記憶體陣列的一個小區塊,記憶體陣列可以包括數千或數百萬的記憶胞。11 is a circuit diagram of a Resistive Random Access Memory (RRAM) array according to a second embodiment. The RRAM array 1100 includes columns and columns of memory cells (e.g., 1101, 1102, and 1103), wherein each memory cell includes a first transistor (e.g., 1101A), a second transistor (e.g., 1101B), and a memory element (e.g., 1101M). The first and second transistors may be N-type metal oxide semiconductor (NMOS) transistors. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG. The memory element can include a metal oxide layer 170 as shown in FIG. a first terminal of the first and second transistors in the memory cell is coupled to one end of the memory element in the memory cell, and a second terminal of the first and second transistor in the memory cell is coupled to the source line (eg, 1121) ). The three memory cells 1101, 1102, and 1103 represent one block of a memory array, and the memory array can include thousands or millions of memory cells.

【0051】[0051]

多個第一存取線路(例如1111、1112與1113)沿著第一方向延伸,且與位元線解碼器(未繪示)電性通訊。多個第一存取線路可以做為位元線。多個第二存取線路(例如1121、1122與1123)沿著正交於第一方向的第二方向延伸,且終止於源極線終端電路(未繪示)。多個第二存取線路可以做為源極線。A plurality of first access lines (eg, 1111, 1112, and 1113) extend in a first direction and are in electrical communication with a bit line decoder (not shown). A plurality of first access lines can be used as bit lines. A plurality of second access lines (eg, 1121, 1122, and 1123) extend in a second direction orthogonal to the first direction and terminate in a source line termination circuit (not shown). A plurality of second access lines can be used as source lines.

【0052】[0052]

記憶胞包括配置於記憶元件(例如1101M)下的第一層間導體(例如1141M),第一層間導體(例如1141M)連接記憶元件(例如1101M)至第一與第二電晶體(例如1101A與1101B)的第一端子,而第二層間導體(例如1141A與1141B)連接第一與第二電晶體之第二端子至源極線(例如1121)。第一層間導體(例如131)與第二層間導體(例如132)的剖面圖係繪示於第8圖中。The memory cell includes a first interlayer conductor (eg, 1141M) disposed under a memory element (eg, 1101M), the first interlayer conductor (eg, 1141M) connecting the memory element (eg, 1101M) to the first and second transistors (eg, 1101A) And a first terminal of 1101B), and a second interlayer conductor (eg, 1141A and 1141B) connects the second terminal of the first and second transistors to the source line (eg, 1121). A cross-sectional view of the first interlayer conductor (e.g., 131) and the second interlayer conductor (e.g., 132) is shown in FIG.

【0053】[0053]

多個第三存取線路(例如1131至1136)沿著第一方向延伸。第三存取線路與字元線解碼器(未繪示)電性通訊,且可以做為字元線。記憶胞中之第一與第二電晶體(例如1101A與1101B)的閘極端子係各自連接至第三存取線路。位元線解碼器與字元線解碼器可以包括互補式金氧半導體(Complementary Metal Oxide Semiconductor, CMOS)電路。A plurality of third access lines (eg, 1131 to 1136) extend along the first direction. The third access line is in electrical communication with a word line decoder (not shown) and can be used as a word line. The gate terminal of the first and second transistors (e.g., 1101A and 1101B) in the memory cell are each connected to a third access line. The bit line decoder and word line decoder may comprise complementary metal oxide semiconductor (CMOS) circuits.

【0054】[0054]

第12圖繪示依照第11圖所示第二實施例之記憶胞的簡化設計圖。以與第11圖中相似的元件符號表示第12圖中相似的元件。記憶胞的佈局可以在垂直與水平方向重複。為了簡化,並未繪示絕緣材料,舉例來說,位於第一、第二與第三存取線路之間的絕緣材料。Fig. 12 is a simplified diagram showing the memory cell according to the second embodiment shown in Fig. 11. Similar elements in Fig. 12 are denoted by like reference numerals in Fig. 11. The layout of the memory cells can be repeated in the vertical and horizontal directions. For the sake of simplicity, the insulating material is not shown, for example, an insulating material between the first, second and third access lines.

【0055】[0055]

此設計圖繪示第一存取線路(例如1111)做為位元線(Bit Lines, BL)、第二存取線路(例如1121、1122與1123)做為源極線(Source Lines, SL),第三存取線路(例如1131、1132與1133)做為字元線(Word Lines, WL)。於一實施方案中,於金屬層1中可以配置第二存取線路,而可以配置第一存取線路於金屬層1上的金屬層2。第一、第二與第三存取線路係連接至記憶胞(例如1101、1102與1103),如第11圖所描述。記憶胞包括記憶元件(例如1101M),記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示金屬氧化層上的第一阻障材料層181與第二阻障材料層182。This design diagram shows the first access line (for example, 1111) as the bit line (Bit Lines, BL) and the second access line (for example, 1121, 1122, and 1123) as the source line (Source Lines, SL). The third access lines (eg, 1131, 1132, and 1133) are used as word lines (WL Lines). In one embodiment, a second access line may be disposed in the metal layer 1, and the first access line may be disposed on the metal layer 2 on the metal layer 1. The first, second, and third access lines are coupled to memory cells (e.g., 1101, 1102, and 1103) as depicted in FIG. The memory cell includes a memory element (e.g., 1101M) and the memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG.

【0056】[0056]

第13圖繪示依照第三實施例之電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)陣列的電路圖。RRAM 陣列1300包括記憶胞(例如1301、1302、1303、1304、1305、1306、1307與1308)的列與欄,其中各記憶胞包括一電晶體(例如1301A)以及記憶元件(例如1301M)。電晶體可以係N型金氧半導體(N-type metal oxide semiconductor, NMOS)電晶體。記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示金屬氧化層170上的第一阻障材料層181與第二阻障材料層182。記憶胞中之電晶體的第一端子係連接至記憶胞中記憶元件的一端。繪示的記憶胞表示記憶體陣列的一個小區塊,記憶體陣列可以包括數千或數百萬的記憶胞。FIG. 13 is a circuit diagram of a Resistive Random Access Memory (RRAM) array according to the third embodiment. The RRAM array 1300 includes columns and columns of memory cells (e.g., 1301, 1302, 1303, 1304, 1305, 1306, 1307, and 1308), wherein each memory cell includes a transistor (e.g., 1301A) and a memory element (e.g., 1301M). The transistor may be an N-type metal oxide semiconductor (NMOS) transistor. The memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer 170 as shown in FIG. The first terminal of the transistor in the memory cell is coupled to one end of the memory element in the memory cell. The depicted memory cells represent a block of memory arrays, which may include thousands or millions of memory cells.

【0057】[0057]

多個第一存取線路(例如1311、1312、1313與1314)沿著第一方向延伸且與位元線解碼器(未繪示)電性通訊,多個第一存取線路係連接至記憶元件的第二端,第二端相對於連接至記憶胞中電晶體之第一端子的末端。多個第一存取線路可以做為位元線。記憶胞可以包括配置於記憶元件(例如1301M)下的第一層間導體(例如1341M),第一層間導體(例如1341M)連接記憶元件至電晶體(例如1301A)的第一端子。第一層間導體(例如131)的剖面圖係繪示於第8圖中。A plurality of first access lines (eg, 1311, 1312, 1313, and 1314) extend in a first direction and are in electrical communication with a bit line decoder (not shown), and the plurality of first access lines are connected to the memory. A second end of the component, the second end being opposite the end of the first terminal connected to the transistor in the memory cell. A plurality of first access lines can be used as bit lines. The memory cell can include a first interlayer conductor (e.g., 1341M) disposed under a memory element (e.g., 1301M), the first interlayer conductor (e.g., 1341M) connecting the memory element to the first terminal of the transistor (e.g., 1301A). A cross-sectional view of the first interlayer conductor (e.g., 131) is shown in FIG.

【0058】[0058]

多個第二存取線路(例如1321、1322、1323與1324)沿著正交於第一方向的第二方向延伸,且終止於源極線終端電路(未繪示)。多個第二存取線路可以做為源極線。記憶胞可以包括連接電晶體之第二端子至源極線(例如1321)的第二層間導體(例如1341A)。第二層間導體(例如132)的剖面圖係繪示於第8圖中。A plurality of second access lines (eg, 1321, 1322, 1323, and 1324) extend in a second direction orthogonal to the first direction and terminate in a source line termination circuit (not shown). A plurality of second access lines can be used as source lines. The memory cell can include a second interlayer conductor (e.g., 1341A) that connects the second terminal of the transistor to the source line (e.g., 1321). A cross-sectional view of the second interlayer conductor (e.g., 132) is shown in FIG.

【0059】[0059]

多個第三存取線路(例如1331至1334)沿著第一方向延伸。第三存取線路與字元線解碼器(未繪示)電性通訊,且可以做為字元線。記憶胞中之電晶體(例如1301A)的閘極端子係各自連接至第三存取線路。位元線解碼器與字元線解碼器可以包括互補式金氧半導體(Complementary Metal Oxide Semiconductor, CMOS)電路。A plurality of third access lines (eg, 1331 through 1334) extend along the first direction. The third access line is in electrical communication with a word line decoder (not shown) and can be used as a word line. The gate terminals of the transistors (e.g., 1301A) in the memory cells are each connected to a third access line. The bit line decoder and word line decoder may comprise complementary metal oxide semiconductor (CMOS) circuits.

【0060】[0060]

第14圖繪示依照第13圖所示第三實施例之記憶胞的簡化設計圖。以與第13圖中相似的元件符號表示第14圖中相似的元件。記憶胞的佈局可以在垂直與水平方向重複。為了簡化,並未繪示絕緣材料,舉例來說,位於第一、第二與第三存取線路之間的絕緣材料。Fig. 14 is a view showing a simplified design of the memory cell according to the third embodiment shown in Fig. 13. Elements similar to those in Fig. 14 are denoted by like reference numerals in Fig. 13. The layout of the memory cells can be repeated in the vertical and horizontal directions. For the sake of simplicity, the insulating material is not shown, for example, an insulating material between the first, second and third access lines.

【0061】[0061]

此設計圖繪示第一存取線路1311與1312做為位元線(Bit Lines, BL)、第二存取線路1321、1322與1323做為源極線(Source Lines, SL),第三存取線路1331與1132做為字元線(Word Lines, WL)。於一實施方案中,於金屬層1中可以配置第二存取線路,而可以配置第一存取線路於金屬層1上的金屬層2中。第一、第二與第三存取線路係連接至記憶胞(例如1301至1303與1305至1306),如第13圖所描述。記憶胞包括記憶元件(例如1301M),記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示金屬氧化層上的第一阻障材料層181與第二阻障材料層182。The design shows that the first access lines 1311 and 1312 are used as bit lines (BL), and the second access lines 1321, 1322 and 1323 are used as source lines (Source Lines, SL). Lines 1331 and 1132 are taken as word lines (WL Lines). In an embodiment, a second access line may be disposed in the metal layer 1, and the first access line may be disposed in the metal layer 2 on the metal layer 1. The first, second and third access lines are connected to memory cells (e.g., 1301 to 1303 and 1305 through 1306) as described in FIG. The memory cell includes a memory element (e.g., 1301M) and the memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG.

【0062】[0062]

第15圖顯示根據使用二極體做為存取裝置之實施例的RRAM陣列的電路圖。記憶體陣列1500包括記憶胞的矩陣、多條字元線(例如1531、1532、1533與1534)以及多條位元線(例如1511、1512、1513與1514)。範例記憶體陣列1500中的各記憶胞(例如1544)在對應的字元線(例如1534)與對應的位元線(例如1511)之間依序包括存取二極體(例如1544D)與記憶元件(例如1544M)。各記憶元件係電性耦合至對應的存取二極體。Figure 15 shows a circuit diagram of an RRAM array according to an embodiment using a diode as an access device. The memory array 1500 includes a matrix of memory cells, a plurality of word lines (eg, 1531, 1532, 1533, and 1534) and a plurality of bit lines (eg, 1511, 1512, 1513, and 1514). Each memory cell (eg, 1544) in the example memory array 1500 sequentially includes an access diode (eg, 1544D) and memory between a corresponding word line (eg, 1534) and a corresponding bit line (eg, 1511). Component (eg 1544M). Each memory element is electrically coupled to a corresponding access diode.

【0063】[0063]

記憶體陣列1500中的記憶胞可以包括如第1圖所示記憶元件上的第一阻障材料層181與第二阻障材料層182。記憶胞中的記憶元件包括如第8圖所示之記憶胞中的金屬氧化層170。The memory cells in the memory array 1500 may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG. The memory element in the memory cell includes a metal oxide layer 170 in the memory cell as shown in FIG.

【0064】[0064]

包括位元線1511、1512、1513與1514的多條位元線沿著第一方向平行延伸。位元線與位元線解碼器1510電性通訊。記憶元件可以連接於二極體之陽極或陰極與位元線之間。舉例來說,記憶元件1544M係連接於二極體1544D之陰極與位元線1511之間。包括字元線1531、1532、1533與1534的多條字元線沿著第二方向平行延伸。字元線1531、1532、1533與1534與字元線解碼器1530電性通訊。二極體之陽極或陰極可連接至字元線。舉例來說,二極體1544D之陽極係連接至字元線1534。位元線解碼器與字元線解碼器可以包括互補式金氧半導體(Complementary Metal Oxide Semiconductor, CMOS)電路。應注意第15圖中的16個記憶胞係為了討論的方便而如此繪示,然而實際上記憶體陣列可包括數千或數百萬個這類的記憶胞。A plurality of bit lines including bit lines 1511, 1512, 1513, and 1514 extend in parallel along the first direction. The bit line is in electrical communication with the bit line decoder 1510. The memory element can be connected between the anode or cathode of the diode and the bit line. For example, memory element 1544M is connected between the cathode of diode 1544D and bit line 1511. A plurality of word lines including word lines 1531, 1532, 1533, and 1534 extend in parallel along the second direction. Word lines 1531, 1532, 1533, and 1534 are in electrical communication with word line decoder 1530. The anode or cathode of the diode can be connected to the word line. For example, the anode of diode 1544D is connected to word line 1534. The bit line decoder and word line decoder may comprise complementary metal oxide semiconductor (CMOS) circuits. It should be noted that the 16 memory cell lines in Figure 15 are thus depicted for convenience of discussion, although in reality the memory array may include thousands or millions of such memory cells.

【0065】[0065]

第16圖繪示依照第15圖所示使用二極體做為存取裝置之實施例之記憶胞的簡化設計圖。以與第15圖中相似的元件符號表示第16圖中相似的元件。記憶胞的佈局可以在垂直與水平方向重複。為了簡化,並未繪示絕緣材料,舉例來說,位於第一、第二與第三存取線路之間的絕緣材料。Figure 16 is a simplified diagram of a memory cell in accordance with an embodiment of the use of a diode as an access device as shown in Figure 15. Similar elements in Fig. 16 are denoted by like reference numerals in Fig. 15. The layout of the memory cells can be repeated in the vertical and horizontal directions. For the sake of simplicity, the insulating material is not shown, for example, an insulating material between the first, second and third access lines.

【0066】[0066]

此設計圖繪示第一存取線路1511、1512、1513與1514做為位元線(Bit Lines, BL)、第二存取線路1531、1532、1533與1534做為字元線(Word Lines, WL)。記憶胞中第二存取線路可以包括用於二極體(例如1544D)的主動區域,且為了字元線拾波(pickup),第二存取電路可以連接至接點(例如1551、1552、1553與1554)。於一實施方案中,於金屬層1中可以配置位元線,位於字元線上的位元線可以包括多晶矽。第一與第二存取線路係連接至記憶胞(例如1544),如第15圖所描述。記憶胞包括記憶元件(例如1541M、1542M、1543M與1544M),記憶元件可以包括如第8圖所示之金屬氧化層170。記憶胞可以包括如第1圖所示記憶元件上的第一阻障材料層181與第二阻障材料層182。The design shows that the first access lines 1511, 1512, 1513 and 1514 are used as bit lines (BL) and the second access lines 1531, 1532, 1533 and 1534 are used as word lines (Word Lines, WL). The second access line in the memory cell may include an active area for a diode (eg, 1544D), and for word line pickup, the second access circuit may be connected to the contact (eg, 1551, 1552) 1553 and 1554). In an embodiment, bit lines may be disposed in the metal layer 1, and the bit lines on the word lines may include polysilicon. The first and second access lines are connected to a memory cell (e.g., 1544) as described in FIG. The memory cells include memory elements (e.g., 1541M, 1542M, 1543M, and 1544M), and the memory element can include a metal oxide layer 170 as shown in FIG. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG.

【0067】[0067]

第17圖繪示用於製造記憶體裝置之方法實施例的簡化流程圖。於步驟1701,於層間導體之陣列上形成絕緣層。於層間導體之陣列的上表面上與絕緣層之間可以形成擴散阻障層,擴散阻障層接觸上表面。於步驟1702,蝕刻絕緣層以定義對應陣列中第一層間導體的第一開口,其中蝕刻停止於第一層間導體的第一上表面。當蝕刻以定義第一開口時,可以使用第一蝕刻遮罩(例如310)於絕緣層上,其中第一蝕刻遮罩具有對應第二層間導體的遮罩區域以及對應第一開口(例如161)的間隔區。Figure 17 is a simplified flow diagram of an embodiment of a method for fabricating a memory device. In step 1701, an insulating layer is formed on the array of interlayer conductors. A diffusion barrier layer may be formed on the upper surface of the array of interlayer conductors and the insulating layer, and the diffusion barrier layer contacts the upper surface. In step 1702, the insulating layer is etched to define a first opening of the first interlayer conductor in the corresponding array, wherein the etching stops at the first upper surface of the first interlayer conductor. When etching to define the first opening, a first etch mask (eg, 310) can be used on the insulating layer, wherein the first etch mask has a mask region corresponding to the second interlayer conductor and a corresponding first opening (eg, 161) Spacer.

【0068】[0068]

於步驟1703,於第一開口中之第一層間導體之第一上表面上形成金屬氧化層。金屬氧化層的特徵可以在於具有可程式的電阻。於步驟1704,沉積與金屬氧化層以及第一開口之表面共形且接觸的第一阻障材料層,金屬氧化層位於第一層間導體上。藉由後續製造步驟以形成與接著移除位於金屬氧化層上的蝕刻遮罩,第一阻障材料層可以保護金屬氧化層免於電位損害,因而提供金屬氧化層與頂電極之間較佳的介面。In step 1703, a metal oxide layer is formed on the first upper surface of the first interlayer conductor in the first opening. The metal oxide layer can be characterized by having a programmable resistance. In step 1704, a first barrier material layer is deposited and contacted with the metal oxide layer and the surface of the first opening, and the metal oxide layer is on the first interlayer conductor. The first barrier material layer can protect the metal oxide layer from potential damage by a subsequent fabrication step to form and subsequently remove the etch mask on the metal oxide layer, thereby providing a better between the metal oxide layer and the top electrode. interface.

【0069】[0069]

於步驟1705,沉積第一阻障材料層之後蝕刻絕緣層以定義陣列中對應第二層間導體的第二開口,其中蝕刻停止於第二層間導體的第二上表面。當蝕刻以定義第二開口時,可以使用第二蝕刻遮罩於絕緣層上,其中第二蝕刻遮罩具有對應第一開口的遮罩區域以及對應第二開口的間隔區。於步驟1706,沉積與第一開口中之第一阻障材料層共形且接觸的第二阻障材料層。舉例來說,相同步驟中亦可以沉積與第二開口中之第二層間導體之第二上表面以及第二開口的表面共形且接觸的第二阻障材料層。In step 1705, after depositing the first barrier material layer, the insulating layer is etched to define a second opening of the corresponding second interlayer conductor in the array, wherein the etching stops at the second upper surface of the second interlayer conductor. When etching to define the second opening, a second etch mask can be used on the insulating layer, wherein the second etch mask has a mask region corresponding to the first opening and a spacer region corresponding to the second opening. At step 1706, a second barrier material layer conformed to and in contact with the first barrier material layer in the first opening is deposited. For example, a second barrier material layer conformed to and in contact with the second upper surface of the second interlayer conductor of the second opening and the surface of the second opening may also be deposited in the same step.

【0070】[0070]

於步驟1707,使用導電材料填充第一開口。舉例來說,相同步驟中亦可以使用導電材料填充第二開口,其中金屬氧化層不存在於第二上表面與第二阻障材料層之間。第一開口之寬度可以大於第一層間導體之寬度。At step 1707, the first opening is filled with a conductive material. For example, the second opening may also be filled with a conductive material in the same step, wherein the metal oxide layer is not present between the second upper surface and the second barrier material layer. The width of the first opening may be greater than the width of the first interlayer conductor.

【0071】[0071]

第一與第二層間導體可以分別連接至存取裝置之第一與第二端子。存取裝置可以包括二極體或電晶體。可以形成耦合至層間導體之陣列的存取裝置陣列,層間導體包括第一與第二層間導體。The first and second interlayer conductors may be respectively connected to the first and second terminals of the access device. The access device can include a diode or a transistor. An array of access devices coupled to an array of interlayer conductors may be formed, the interlayer conductors including first and second interlayer conductors.

【0072】[0072]

將理解記憶體陣列並非受限於第12圖中繪示的陣列結構,亦可以伴隨著包括上述之頂電極層的記憶胞使用額外的陣列結構。此外,於一些實施例中,除了MOS電晶體之外,可使用雙極性電晶體或二極體做為存取裝置。It will be appreciated that the memory array is not limited to the array structure illustrated in Figure 12, and that an additional array structure can be used with the memory cells including the top electrode layer described above. Moreover, in some embodiments, a bipolar transistor or diode can be used as the access device in addition to the MOS transistor.

【0073】[0073]

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧記憶胞 100‧‧‧ memory cells

111‧‧‧第一端子 111‧‧‧First terminal

112‧‧‧第二端子 112‧‧‧second terminal

120‧‧‧介電層 120‧‧‧ dielectric layer

131‧‧‧第一層間導體 131‧‧‧First interlayer conductor

131T‧‧‧第一上表面 131T‧‧‧ first upper surface

132‧‧‧第二層間導體 132‧‧‧Second interlayer conductor

132T‧‧‧第二上表面 132T‧‧‧Second upper surface

140‧‧‧擴散阻障層 140‧‧‧Diffusion barrier

150‧‧‧絕緣層 150‧‧‧Insulation

161‧‧‧第一開口 161‧‧‧ first opening

162‧‧‧第二開口 162‧‧‧ second opening

170‧‧‧金屬氧化層 170‧‧‧metal oxide layer

180‧‧‧第一阻障層 180‧‧‧First barrier layer

181‧‧‧第一阻障材料層 181‧‧‧First barrier material layer

182‧‧‧第二阻障材料層 182‧‧‧Second barrier material layer

185‧‧‧導電材料 185‧‧‧Electrical materials

Claims (22)

【第1項】[Item 1] 一種製造記憶體的方法,包括:
形成一絕緣層於複數個層間導體之一陣列上;
蝕刻該絕緣層以定義一第一開口,該第一開口對應該陣列中的一第一層間導體,蝕刻停止於該第一層間導體之一第一上表面;
形成一金屬氧化層於該第一開口中之該第一層間導體的該第一上表面上;
沉積一第一阻障材料層,該第一阻障材料層與該第一層間導體上之該金屬氧化層共形且接觸,且該第一阻障材料層與該第一開口之複數個表面共形且接觸,其中該第一開口的寬度大於該第一層間導體的寬度;
在前述沉積該第一阻障材料層之後蝕刻該絕緣層以定義一第二開口,該第二開口對應該陣列中的一第二層間導體,蝕刻停止於該第二層間導體之一第二上表面;
沉積一第二阻障材料層,該第二阻障材料層與該第一開口中之該第一阻障材料層共形且接觸;以及
使用一導電材料填充該第一開口;
其中該第一層間導體與該第二層間導體係分別連接至一存取裝置之一第一端子與一第二端子。
A method of making a memory, comprising:
Forming an insulating layer on one of the plurality of interlayer conductors;
Etching the insulating layer to define a first opening, the first opening corresponding to a first interlayer conductor in the array, etching stops at a first upper surface of the first interlayer conductor;
Forming a metal oxide layer on the first upper surface of the first interlayer conductor in the first opening;
Depositing a first barrier material layer, the first barrier material layer is conformal and in contact with the metal oxide layer on the first interlayer conductor, and the first barrier material layer and the first opening are plural The surface is conformal and in contact, wherein a width of the first opening is greater than a width of the first interlayer conductor;
Etching the insulating layer to form a second opening after the depositing the first barrier material layer, the second opening corresponds to a second interlayer conductor in the array, and etching stops on one of the second interlayer conductors surface;
Depositing a second barrier material layer, the second barrier material layer conforming and contacting the first barrier material layer in the first opening; and filling the first opening with a conductive material;
The first interlayer conductor and the second interlayer conduction system are respectively connected to one of the first terminal and the second terminal of an access device.
【第2項】[Item 2] 如申請專利範圍第1項所述之方法,更包括:
形成一擴散阻障層於該些層間導體之該陣列之複數個上表面與該絕緣層之間,該擴散阻障層接觸該些上表面。
For example, the method described in claim 1 of the patent scope further includes:
Forming a diffusion barrier layer between the plurality of upper surfaces of the array of the interlayer conductors and the insulating layer, the diffusion barrier layer contacting the upper surfaces.
【第3項】[Item 3] 如申請專利範圍第1項所述之方法,前述蝕刻以定義該第一開口之步驟,包括:
使用一第一蝕刻遮罩於該絕緣層上,該第一蝕刻遮罩具有對應該第二開口之一遮罩區域以及對應該第一開口之一間隔區。
The method of claim 1, wherein the etching is to define the first opening comprises:
A first etch mask is used on the insulating layer, the first etch mask having a mask region corresponding to one of the second openings and a spacer region corresponding to the first opening.
【第4項】[Item 4] 如申請專利範圍第1項所述之方法,前述蝕刻以定義該第二開口之步驟,包括:
使用一第二蝕刻遮罩於該絕緣層上,該第二蝕刻遮罩具有對應該第一開口之一遮罩區域以及對應該第二開口之一間隔區。
The method of claim 1, wherein the etching comprises to define the second opening comprises:
A second etch mask is used on the insulating layer, the second etch mask having a mask region corresponding to one of the first openings and a spacer region corresponding to the second opening.
【第5項】[Item 5] 如申請專利範圍第1項所述之方法,前述沉積該第二阻障材料層之步驟,包括:
沉積該第二阻障材料層,該第二阻障材料層與該第二開口中之該第二層間導體之該第二上表面共形並接觸,且該第二阻障材料層與該第二開口之複數個表面共形並接觸;以及
使用該導電材料填充該第二開口。
The method of depositing the second barrier material layer according to the method of claim 1, wherein:
Depositing the second barrier material layer, the second barrier material layer conforms to and contacts the second upper surface of the second interlayer conductor of the second opening, and the second barrier material layer and the first A plurality of surfaces of the two openings are conformal and in contact; and the second opening is filled with the conductive material.
【第6項】[Item 6] 如申請專利範圍第1項所述之方法,包括:
形成一第一存取線路,該第一存取線路電性連接至該金屬氧化層;以及
形成一第二存取線路,該第二存取線路電性連接至該第二層間導體。
For example, the method described in claim 1 includes:
Forming a first access line electrically connected to the metal oxide layer; and forming a second access line electrically connected to the second interlayer conductor.
【第7項】[Item 7] 如申請專利範圍第1項所述之方法,包括:
形成複數個存取裝置之一陣列,該陣列耦合至該些層間導體之該陣列,且該些存取裝置之該陣列包括第一次提到的該存取裝置。
For example, the method described in claim 1 includes:
An array of a plurality of access devices is formed, the array being coupled to the array of the interlayer conductors, and the array of access devices includes the first mentioned access device.
【第8項】[Item 8] 如申請專利範圍第1項所述之方法,其中第一次提到的該存取裝置包括一二極體。The method of claim 1, wherein the first access device comprises a diode. 【第9項】[Item 9] 如申請專利範圍第1項所述之方法,其中第一次提到的該存取裝置包括一電晶體,包括:
形成一第三存取線路,該第三存取線路電性連接至該電晶體之一閘極端子。
The method of claim 1, wherein the first access device comprises a transistor, comprising:
A third access line is formed, the third access line being electrically connected to one of the gate terminals of the transistor.
【第10項】[Item 10] 如申請專利範圍第1項所述之方法,其中該金屬氧化層的特徵為具有可程式的一電阻。The method of claim 1, wherein the metal oxide layer is characterized by a programmable resistance. 【第11項】[Item 11] 如申請專利範圍第1項所述之方法,其中該第一層間導體實質上由一金屬所組成,且該金屬氧化層包括該金屬之一氧化物。The method of claim 1, wherein the first interlayer conductor consists essentially of a metal and the metal oxide layer comprises an oxide of the metal. 【第12項】[Item 12] 如申請專利範圍第1項所述之方法,其中該第一層間導體實質上由一過渡金屬所組成,且該金屬氧化層包括該過渡金屬之一氧化物。The method of claim 1, wherein the first interlayer conductor consists essentially of a transition metal, and the metal oxide layer comprises an oxide of the transition metal. 【第13項】[Item 13] 一種記憶體,包括:
一圖案化絕緣層,位於複數個層間導體之一陣列上,該圖案化絕緣層包括一第一開口與一第二開口,該第一開口對應該陣列中的一第一層間導體,該第二開口對應該陣列中的一第二層間導體;
一金屬氧化層,位於該第一層間導體之一第一上表面上;
一第一阻障層,與該第一層間導體上之該金屬氧化層共形並接觸,且該第一阻障層與該第一開口之複數個表面共形且接觸,其中該第一開口的寬度大於該第一層間導體的寬度;
一第二阻障層,位於該第二開口上,其中該第二阻障層的厚度小於該第一阻障層的厚度;以及
一導電材料,填充於該第一開口中;
其中該第一層間導體與該第二層間導體係分別連接至一存取裝置之一第一端子與一第二端子。
A memory that includes:
a patterned insulating layer on an array of a plurality of interlayer conductors, the patterned insulating layer including a first opening and a second opening, the first opening corresponding to a first interlayer conductor in the array, the first The two openings correspond to a second interlayer conductor in the array;
a metal oxide layer on a first upper surface of one of the first interlayer conductors;
a first barrier layer conformally and in contact with the metal oxide layer on the first interlayer conductor, and the first barrier layer conforms and contacts a plurality of surfaces of the first opening, wherein the first layer The width of the opening is greater than the width of the first interlayer conductor;
a second barrier layer is disposed on the second opening, wherein the second barrier layer has a thickness smaller than a thickness of the first barrier layer; and a conductive material is filled in the first opening;
The first interlayer conductor and the second interlayer conduction system are respectively connected to one of the first terminal and the second terminal of an access device.
【第14項】[Item 14] 如申請專利範圍第13項所述之記憶體,更包括:
一擴散阻障層,位於該些層間導體之該陣列之複數個上表面與該圖案化絕緣層之間,且該擴散阻障層接觸該些上表面。
For example, the memory described in claim 13 of the patent scope further includes:
a diffusion barrier layer is disposed between the plurality of upper surfaces of the array of the interlayer conductors and the patterned insulating layer, and the diffusion barrier layer contacts the upper surfaces.
【第15項】[Item 15] 如申請專利範圍第13項所述之記憶體,更包括:
該第二阻障層,與該第二開口中之該第二層間導體之一第二上表面共形並接觸,且該第二阻障層與該第二開口之複數個表面共形並接觸;以及
該導電材料,填充該第二開口。
For example, the memory described in claim 13 of the patent scope further includes:
The second barrier layer is conformal and in contact with a second upper surface of the second interlayer conductor of the second opening, and the second barrier layer conforms and contacts with a plurality of surfaces of the second opening And the conductive material filling the second opening.
【第16項】[Item 16] 如申請專利範圍第13項所述之記憶體,更包括:
一第一存取線路,電性連接至該金屬氧化層;以及
一第二存取線路,電性連接至該第二層間導體。
For example, the memory described in claim 13 of the patent scope further includes:
a first access line electrically connected to the metal oxide layer; and a second access line electrically connected to the second interlayer conductor.
【第17項】[Item 17] 如申請專利範圍第13項所述之記憶體,更包括:
複數個存取裝置之一陣列,耦合至該些層間導體之該陣列,且該些存取裝置之該陣列包括第一次提到的該存取裝置。
For example, the memory described in claim 13 of the patent scope further includes:
An array of one of a plurality of access devices coupled to the array of the interlayer conductors, and the array of access devices includes the first mentioned access device.
【第18項】[Item 18] 如申請專利範圍第13項所述之記憶體,其中第一次提到的該存取裝置包括一二極體。The memory of claim 13, wherein the first access device comprises a diode. 【第19項】[Item 19] 如申請專利範圍第13項所述之記憶體,其中第一次提到的該存取裝置包括一電晶體,該記憶體包括:
一第三存取線路,電性連接至該電晶體之一閘極端子。
The memory of claim 13, wherein the first access device comprises a transistor, the memory comprising:
A third access line is electrically connected to one of the gate terminals of the transistor.
【第20項】[Item 20] 如申請專利範圍第13項所述之記憶體,其中該金屬氧化層的特徵為具有可程式的一電阻。The memory of claim 13, wherein the metal oxide layer is characterized by a programmable resistance. 【第21項】[Item 21] 如申請專利範圍第13項所述之記憶體,其中該第一層間導體實質上由一金屬所組成,且該金屬氧化層包括該金屬之一氧化物。The memory of claim 13, wherein the first interlayer conductor consists essentially of a metal, and the metal oxide layer comprises an oxide of the metal. 【第22項】[Item 22] 如申請專利範圍第13項所述之記憶體,其中該第一層間導體實質上由一過渡金屬所組成,且該金屬氧化層包括該過渡金屬之一氧化物。The memory of claim 13, wherein the first interlayer conductor consists essentially of a transition metal, and the metal oxide layer comprises an oxide of the transition metal.
TW104109778A 2015-03-26 2015-03-26 Damascene process of rram top electrodes TWI550610B (en)

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US20150044832A1 (en) * 2010-07-15 2015-02-12 Micron Technology, Inc. Resistive random access memory
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