CN105098067B - The manufacture method of semiconductor structure, resistive memory cell structure and semiconductor structure - Google Patents
The manufacture method of semiconductor structure, resistive memory cell structure and semiconductor structure Download PDFInfo
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- CN105098067B CN105098067B CN201410217468.6A CN201410217468A CN105098067B CN 105098067 B CN105098067 B CN 105098067B CN 201410217468 A CN201410217468 A CN 201410217468A CN 105098067 B CN105098067 B CN 105098067B
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Abstract
The invention discloses the manufacture method of a kind of semiconductor structure, resistive memory cell structure and semiconductor structure.Semiconductor structure includes insulation system, barrier layer (stop layer), metal oxide layer, electric resistance structure (resistance structure) and electrode material layer.Insulation system has through hole (via), and barrier layer is formed in through hole.Metal oxide layer is formed on barrier layer.Electric resistance structure is formed at a bottom of an outer wall of metal oxide layer.Electrode material layer is formed on metal oxide layer.
Description
Technical field
The invention relates to the manufacturer of a kind of semiconductor structure, resistive memory cell structure and semiconductor structure
Method, and in particular to the system of a kind of semiconductor structure of superperformance, resistive memory cell structure and semiconductor structure
Make method.
Background technology
With the development of semiconductor technology, various semiconductor element is constantly weeded out the old and bring forth the new.For example, memory, crystal
The elements such as pipe, diode are widely used in various electronic installation.
In the development of memory technology, researcher constantly carries out various types of research and development with improving, wherein resistance
Formula memory is a type therein.Therefore, researcher is directed to studying the electricity for how making resistance-type memory
Resistance can obtain good control to reach good characteristic.
The content of the invention
The invention relates to the manufacturer of a kind of semiconductor structure, resistive memory cell structure and semiconductor structure
Method.In embodiment, the barrier layer of semiconductor structure can be with the over oxidation of barrier oxidation technique, and then can make semiconductor structure
With preferably characteristic.
It is to propose a kind of semiconductor structure according to one embodiment of the invention.Semiconductor structure includes insulation system, stopped
Layer (stop layer), metal oxide layer, electric resistance structure (resistance structure) and electrode material layer.Insulation
Structure has a through hole (via), and barrier layer is formed in through hole.Metal oxide layer is formed on barrier layer.Resistance junction configuration
Into a bottom of the outer wall in metal oxide layer.Electrode material layer is formed on metal oxide layer.
According to another embodiment of the present invention, it is to propose a kind of resistive memory cell structure.Resistive memory cell knot
Structure includes insulation system, barrier layer, memory element (memory element), electric resistance structure and top electrode layer.Insulation system
With through hole, barrier layer is formed in through hole.Memory element is formed on barrier layer.Electric resistance structure is formed at the one of memory element
One bottom of outer wall.Top electrode layer is formed on memory element.
It is to propose a kind of manufacture method of semiconductor structure according to one more embodiment of the present invention.The system of semiconductor structure
The method of making comprises the following steps：An insulation system is formed, with a through hole (via)；A barrier layer is formed in the through hole and is somebody's turn to do
On the side wall of through hole；A metal level is formed on the barrier layer；Remove a part of resistance on the inwall of the through hole
Barrier；An oxidation technology is carried out to aoxidize the metal level to form a metal oxide layer on the barrier layer and forming an electricity
Structure is hindered in a bottom of an outer wall of the metal oxide layer；And an electrode material layer is formed in the metal oxide layer
On.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, are described in detail below：
Brief description of the drawings
Fig. 1 illustrates the diagrammatic cross-section of the semiconductor structure according to one embodiment of the invention.
Fig. 2 illustrates the diagrammatic cross-section of the semiconductor structure according to another embodiment of the present invention.
Fig. 3 illustrates the diagrammatic cross-section of the semiconductor structure according to another embodiment of the present invention.
Fig. 4 A~Fig. 4 D illustrate the flow chart of the manufacture method of the semiconductor structure according to one embodiment of the invention.
Fig. 5 A~Fig. 5 F illustrate the flow chart of the manufacture method of the semiconductor structure according to another embodiment of the present invention.
Fig. 6 A~Fig. 6 G illustrate the flow chart of the manufacture method of the semiconductor structure according to another embodiment of the present invention.
Fig. 7 illustrates resistance-voltage curve of the semiconductor structure according to one embodiment of the invention and a comparative example.
【Symbol description】
100、200、300：Semiconductor structure
110、210：Insulation system
110a、130a、130a’、140a、150a-1、150b-1、210a、340a、440a：Top surface
110r：Upper part
110s：Side wall
110v、210v：Through hole
120、220：Conductive structure
220a：Conductive material layer
130、130’：Barrier layer
140：Metal oxide layer
140s：Outer wall
150：Electric resistance structure
150a：Metal oxide structures
150b：Space
160：Electrode material layer
210s：Inwall
211：Clearance wall
213：Interlayer dielectric layer
213r：Perforation
340、340’、440：Metal level
413：Interlayer dielectric material layers
D1：Depth
H1：Highly
I、II：Curve
T1、T2：Thickness
W1、W2：Width
Embodiment
It is to propose a kind of semiconductor structure, resistive memory cell structure and semiconductor junction in the embodiment invented at this
The manufacture method of structure.In embodiment, the barrier layer of semiconductor structure can be with the over oxidation of barrier oxidation technique, and then can make
Semiconductor structure has preferably characteristic.However, embodiment as example only to illustrate, the present invention can't be limited and be intended to protect
Scope.In addition, the schema in embodiment is to omit the element that part is wanted, to clearly show that the technical characterstic of the present invention.
Fig. 1 illustrates the diagrammatic cross-section of the semiconductor structure 100 according to one embodiment of the invention.Semiconductor structure 100
Including insulation system 110, barrier layer (stop layer) 130, metal oxide layer 140, electric resistance structure (resistance
Structure) 150 and electrode material layer 160.Insulation system 110 has through hole (via) 110v, and barrier layer 130 is formed at logical
In the 110v of hole.Metal oxide layer 140 is formed on barrier layer 130.Electric resistance structure 150 is formed at metal oxide layer 140
Outer wall 140s bottom, electrode material layer 160 is formed on metal oxide layer 140.
In embodiment, the material of insulation system 110 may include insulating materials, e.g. silicon nitride (SiN) and/or oxidation
Silicon.However, the material of foregoing insulation system 110 can do appropriate selection according to practical application, it is not limited with previous example.
In embodiment, barrier layer 130 has high conductivity and is difficult to oxidized characteristic, can be used for stopping to be formed
The over oxidation of the oxidation technology of metal oxide layer 140, e.g. barrier oxidation technique aoxidize other of semiconductor structure 100
Element, and then can make semiconductor structure 100 that there is preferably characteristic.
In embodiment, barrier layer 130 may include metal nitride or inert metal (inert metal) at least within it
One.For example, the material on barrier layer 130 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), golden (Au) and
At least one of platinum (Pt).However, the selection of foregoing material can do appropriate selection according to practical application, not in the past
Example is stated to be limited.
In embodiment, the thickness T1 on barrier layer 130 is, for example, aboutThe thickness T2 of metal oxide layer 140
E.g. about
In embodiment, the material of metal oxide layer 140 may include tungsten oxide (WOx), titanium nitride (TiN), tantalum nitride
(TaN) and gasification hafnium (Hf02) at least one.
In embodiment, semiconductor structure 100 more may include a conductive structure 120.As shown in figure 1, conductive structure 120 is formed
Between barrier layer 130 and metal oxide layer 140.The material of conductive structure 120 may include a conductive material, e.g. tungsten
Metal (W).However, the material of foregoing conductive structure 120 can do appropriate selection according to practical application, not with previous example
It is limited.
Embodiments in accordance with the present invention, as shown in figure 1, electric resistance structure 150 is formed at the outer wall of metal oxide layer 140
140s bottom, in other words, the top surface system of electric resistance structure 150 are less than the top surface 140a of metal oxide layer 140.More enter one
For step, the electric resistance structure 150 with high resistance can be formed at the outer wall 140s's and through hole 110v of metal oxide layer 140
Between the wall 110s of side, consequently, it is possible to which the conducting element that electrode material layer 160 is located at other under electric resistance structure 150 can be made
Between have better insulating properties, further prevent between electrode material layer 160 and other conducting elements occur short circuit.Lift
For example, the electric resistance structure 150 with high resistance can be made between conductive structure 120 and electrode material layer 160 with better
Good insulating properties, further prevents that short circuit occurs between conductive structure 120 and electrode material layer 160.
As shown in figure 1, electric resistance structure 150 may include metal oxide structures 150a or space (void) 150b at least its
One of.In other words, electric resistance structure 150 may include metal oxide structures 150a or space 150b, or include metal oxygen simultaneously
Compound structure 150a and space 150b.In embodiment, metal oxide structures 150a top surface 150a-1's and space 150b
Top surface 150b-1 is below the top surface 140a of metal oxide layer 140.
In embodiment, metal oxide structures 150a can be any metal oxide with high resistance, be, for example,
Titanium oxynitrides (TiON)；Space 150b is, for example, the air gap (air gap), the same property with high resistance.However, preceding
The type for the electric resistance structure 150 stated can do appropriate selection according to practical application, be not limited with previous example.
In embodiment, the material of electrode material layer 160 includes a conductive material, for example can be tungsten (W), platinum (Pt),
At least one of tantalum nitride (TaN) and nickel (Ni).However, the material of foregoing electrode material layer 160 can be according to reality
Using appropriate selection is done, as long as can be applied to electrode, it is not limited with previous example.
Fig. 2 illustrates the diagrammatic cross-section of the semiconductor structure 200 according to another embodiment of the present invention.In the present embodiment with
Previous embodiment identical element is to continue to use same element numbers, and similar elements related description refer to it is foregoing, herein
Repeat no more.
As shown in Fig. 2 semiconductor structure 200 includes insulation system 110, conductive structure 220, barrier layer 130, metal oxidation
Nitride layer 140, electric resistance structure 150 and electrode material layer 160.Insulation system 110 has through hole 110v, and conductive structure 220 is formed
In through hole 110v.Barrier layer 130 is formed on conductive structure 220, and metal oxide layer 140 is formed on barrier layer 130.Electricity
Resistance structure 150 is formed at the outer wall 140s of metal oxide layer 140 bottom, and electrode material layer 160 is formed at metal oxide
On layer 140.
In embodiment, the material of conductive structure 220 may include a conductive material, e.g. tungsten metal (W).However, preceding
The material for the conductive structure 220 stated can do appropriate selection according to practical application, be not limited with previous example.
In embodiment, barrier layer 130 has high conductivity and is difficult to oxidized characteristic, can be used for stopping to be formed
The over oxidation of the oxidation technology of metal oxide layer 140, e.g. barrier oxidation technique aoxidize conductive structure 220, and can be with
The thickness of metal oxide layer 140 is preferably controlled in technique so that the thickness of metal oxide layer 140 has preferably equal
Even property, and then can make semiconductor structure 100 that there is preferably characteristic.Also, barrier layer 130 can also increase metal oxide
The adherence (adhesion) of layer 140 and conductive structure 220.
In one embodiment, the material on barrier layer 130 is titanium nitride, can increase conductive structure 220 and material that material is tungsten
Matter is the adherence between the metal oxide layer 140 of tungsten oxide.
Embodiments in accordance with the present invention, as shown in Fig. 2 electric resistance structure 150 is formed at the outer wall of metal oxide layer 140
140s bottom.For further, the electric resistance structure 150 with high resistance can be formed at the outer of metal oxide layer 140
Between wall 140s and through hole 110v side wall 110s, consequently, it is possible to can make between conductive structure 220 and electrode material layer 160
With better insulating properties, further prevent that short circuit occurs between conductive structure 220 and electrode material layer 160.
In embodiment, semiconductor structure 200 more may include a laying (not being illustrated in schema), and laying is formed at conduction
Between structure 220 and insulation system 110.In embodiment, the material of laying may include titanium nitride.
Fig. 3 illustrates the diagrammatic cross-section of the semiconductor structure 300 according to another embodiment of the present invention.In the present embodiment with
Previous embodiment identical element is to continue to use same element numbers, and similar elements related description refer to it is foregoing, herein
Repeat no more.
As shown in figure 3, semiconductor structure 300 includes an insulation system 210, conductive structure 220, barrier layer 130, metal oxygen
Compound layer 140, electric resistance structure 150 and electrode material layer 160.Insulation system 210 has a through hole (via) 210v, conduction knot
Structure 220 is formed in through hole 210v.Barrier layer 130 is formed on conductive structure 220, and metal oxide layer 140 is formed at stop
On layer 130.Electric resistance structure 150 is formed at the outer wall 140s of metal oxide layer 140 bottom, and electrode material layer 160 is formed at
On metal oxide layer 140.As shown in figure 3, electric resistance structure 150 may include metal oxide structures 150a or space 150b extremely
It is one of few.
In embodiment, as shown in figure 3, insulation system 210 may include clearance wall 211 and interlayer dielectric layer 213.Clearance wall
211 are formed on clearance wall 211 around conductive structure 220, interlayer dielectric layer 213, and clearance wall 211 and interlayer dielectric layer 213
It is collectively forming through hole 210v.
Through hole 210v, which corresponds to clearance wall 211, has the first width W1, and through hole 210v, which corresponds to interlayer dielectric layer 213, to be had
Second width W2, the first width W1 and the second width W2 can be with identical or different.In one embodiment, as shown in Fig. 2 the first width
W1 is more than the second width W2.In other embodiment, the first width W1 can also be equal to or less than the second width W2.
In embodiment, semiconductor structure 300 more may include laying (not being illustrated in schema), and laying is formed at conductive knot
Between structure 220 and insulation system 210, e.g. between conductive structure 220 and clearance wall 211.In embodiment, the material of laying
It may include titanium nitride.
Embodiments in accordance with the present invention, semiconductor structure 100/200/300 is, for example, that a kind of contact resistance-type storage is single
First (Contact-type resistive random access memory unit) structure, conductive structure 120/220 is for example
It is a contact structures (contact structure), metal oxide layer 140 is, for example, a memory element (memory
Element), electrode material layer 160 is, for example, a top electrode layer.For example, contact structures, memory element and top electrode layer can
The multilayered memory cellular construction of an insulator/metal layer/metal is constituted, its resistance value can change via applying bias, make to deposit
High resistance and low resistance two states can be had by storing up element, to express " 0 " and " 1 " of digital signal, and perform memory cell
The function of the write-in and erasing of structure.Specifically, when applying applying bias, in the multilayered memory of insulator/metal layer/metal
Thread conducting path is formed in the insulating barrier of cellular construction, and causes memory element to be changed into low resistance state.When electric current passes through
Afterwards, thread conducting path fracture, then cause memory element to be changed into high resistance state.
When the thickness of metal oxide layer 140 has good uniformity, in other words, the thickness of the insulating barrier of memory element
With high uniformity, then the resistance value of memory element can be controlled preferably, and then make contact resistive memory cell knot
Structure has preferably characteristic.
Fig. 4 A~Fig. 4 D are refer to, it illustrates the manufacture method of the semiconductor structure 100 according to one embodiment of the invention
Flow chart.
As shown in Figure 4 A, the insulation system 110 with through hole 110v is formed, barrier layer 130 is formed in through hole 110v, with
And a metal level 440 is formed on barrier layer 130.In embodiment, barrier layer 130 is formed on through hole 110V side wall 110s.
In embodiment, barrier layer 130 and metal level 440 are for example formed at and fill up through hole 110v.
In embodiment, a flatening process further can be carried out to barrier layer 130 and metal level 440, to planarize stop
The surface of layer 130 and metal level 440.In embodiment, flatening process is, for example, chemical mechanical milling tech (CMP
process).After planarization, as shown in Figure 4 A, the top surface 130a on barrier layer 130 and the top surface 440a of metal level 440 are neat
Put down and wait plane.After planarization, the top surface 130a on barrier layer 130 and the top surface 440a of metal level 440 can and insulate
The top surface 110a of structure 110 is to flush and wait plane or the plane such as non-.In embodiment, as shown in Figure 4 A, top surface 130a
And the top surface 110a of top surface 440a and insulation system 110 is the plane such as non-.
As shown in Figure 4 B, a part of barrier layer 130 on through hole 110v inwall 110s is removed.After this step,
The top surface 130a' on barrier layer 130 and the top surface 440a of metal level 440 are the planes such as non-.It is, for example, via one in embodiment
Etching technics removes this part barrier layer 130 on through hole 110v 110s inwalls, and using for the He of barrier layer 130
The etching liquid that metal level 440 has high selectivity is performed etching so that only partial barrier 130 is etched removal, and metal level
440 structure is not etched substantially destruction.
As shown in Figure 4 C, an oxidation technology is carried out with metal oxide layer 440 to form metal oxide layer 140 in barrier layer
On 130 and formed electric resistance structure 150 in the outer wall 140s of metal oxide layer 140 bottom.In embodiment, metal level 440
Some be oxidized and form metal oxide layer 140, not oxidized part then forms conductive structure 120.
As shown in Figure 4 D, electrode material layer 160 is formed on metal oxide layer 140.So far, Fig. 4 D (Fig. 1) are formed at
Shown semiconductor structure 100.
In oxidation technology, metal level 440 is oxidized and its volumetric expansion, therefore forms metal oxidation as shown in Figure 4 D
Nitride layer 140, wherein the metal oxide layer 140 expanded, its outer wall 140s towards through hole 110v side wall 110s extends.In addition,
Electric resistance structure 150, e.g. space 150b are formed at the outer wall 140s and through hole 110v of metal oxide layer 140 side wall
Between 110s.In embodiment, space 150b is for example formed at the outer wall 140s of metal oxide layer 140 bottom.This step
In, because the top surface 130a' on barrier layer 130 is less than the top surface 440a of metal level 440, therefore the space 150b that is formed
Top surface 150b-1 is also less than the top surface 140a of metal oxide layer 140.
In embodiment, oxidation technology for example can be plasma oxidation process (plasma oxidation
Process), rapid thermal oxidation process (rapid thermal oxidation process) or photochemical oxidation process
(photo-chemical oxidation process).However, the type of foregoing oxidation technology can be according to practical application
Appropriate selection is done, is not limited with previous example.
Furthermore, in oxidation technology, the barrier layer 130 of an exposed portion may can also be oxidized and form electric resistance structure
150, e.g. metal oxide structures 150a.For example, barrier layer 130 is exposed to one of the surface outside metal level 440
Part can be oxidized in oxidation technology and form metal oxide structures 150a.In embodiment, metal oxide structures
150a material for example includes the oxide on barrier layer 130.For example, when the material on barrier layer 130 is titanium nitride, then metal
Oxide structure 150a material may include titanium oxynitrides.In this step, because the top surface 130a' on barrier layer 130 is less than gold
Belong to the top surface 440a of layer 440, therefore the metal oxide structures 150a formed top surface 150a-1 is also less than metal oxygen
The top surface 140a of compound layer 140.
Fig. 5 A~Fig. 5 F are refer to, it illustrates the manufacturer of the semiconductor structure 200 according to another embodiment of the present invention
The flow chart of method.
As shown in Fig. 5 A~Fig. 5 B, the insulation system 110 with a through hole 110v is formed, and form conductive structure 220
In through hole 110v.Manufacture method of the conductive structure 220 in through hole 110v is formed for example to comprise the following steps.
As shown in Figure 5A, a conductive material layer 220a is inserted in through hole 110v.Then, as shown in Figure 5 B, one is removed
Point conductive material layer 220a into conductive structure 220 in through hole 110v, and to expose a through hole 110v upper part
(upper portion)110r.In other words, conductive structure 220 is not filled to through hole 110v upper part 110r.
In embodiment, it more can be selectively formed laying (not being illustrated in schema) and tied in conductive material layer 220a and insulation
Between structure 110.For example, be initially formed laying on the inwall of insulation system 110, be subsequently formed conductive material layer 220a in
On laying.In the present embodiment, when removing partially electronically conductive material layer 220a, the laying of part is removed in the lump so that leave
Laying is only positioned between conductive structure 220 and insulation system 110.
In embodiment, it is, for example, to remove partially electronically conductive material layer 220a via an etching technics, after removal, leaves conduction
Structure 220 and the upper part 110r for being not filled by conductive structure 220.As shown in Figure 5 B, this upper part 110r systems are recessed with one
Fall into and present.In embodiment, the depth D1 that the depression of this upper part 110r formation has is about the barrier layer being subsequently formed
The totalling of the thickness of thickness and metal oxide layer, be, for example,But this depth D1 can be according to practical application
Appropriate selection is done, e.g. the need for the characteristic of resistance of element etc., is not limited with aforementioned range.
As shown in Figure 5 C, a barrier layer 130 ' is formed on conductive structure 220 and on through hole 110v side wall 110s, and
A metal level 340 ' is formed on barrier layer 130 '.In embodiment, barrier layer 130 ' and metal level 340 ' are for example formed at simultaneously
In the depression of upper part 110r formation for filling up through hole 110v.
As shown in Figure 5 D, a flatening process is carried out to barrier layer 130 ' and metal level 340 ', to planarize barrier layer
130 ' and the surface of metal level 340 ', and form barrier layer 130 and metal level 340.In embodiment, being, for example, of flatening process
Learn mechanical milling tech (CMP process).After planarization, as shown in Figure 5 D, the top surface 130a and metal on barrier layer 130
The top surface 340a of layer 340 is flushed and is waited plane.After planarization, the top surface 130a on barrier layer 130 and the top of metal level 340
Surface 340a can be flushed with the top surface 110a systems of insulation system 110 and be waited plane or the plane such as non-.In embodiment, such as scheme
Shown in 5D, the top surface 110a of top surface 130a and top surface 340a and insulation system 110 is the plane such as non-.
As shown in fig. 5e, a part of barrier layer 130 on through hole 110v inwall 110s is removed.After this step,
The top surface 130a' on barrier layer 130 and the top surface 340a of metal level 340 are the planes such as non-.It is, for example, via one in embodiment
Etching technics removes this partial barrier 130, and using the quarter for barrier layer 130 and metal level 340 with high selectivity
Erosion liquid is performed etching so that only partial barrier 130 is etched removal, and the structure of metal level 340 is not etched substantially
Destruction.
As illustrated in figure 5f, an oxidation technology is carried out with metal oxide layer 340 to form metal oxide layer 140 in barrier layer
On 130 and electric resistance structure 150 is formed in the outer wall 140s of metal oxide layer 140 bottom, and form electrode material layer
160 on metal oxide layer 140.In embodiment, because barrier layer 130 can prevent going deep into for oxygen so that oxidation technology pair
It can be blocked on barrier layer 130 in the oxidation of metal level 340, therefore the depth of oxidation will not down diffuse to conductive structure
220, it thus can preferably control the thickness of metal oxide layer 140, the thickness of metal oxide layer 140 can also be compared with
Uniformly.
In embodiment, as illustrated in figure 5f, electrode material layer 160 is also formed on the top surface 110a of insulation system 110.
In oxidation technology, metal level 340 is oxidized and its volumetric expansion, therefore forms metal oxidation as illustrated in figure 5f
Nitride layer 140, wherein the metal oxide layer 140 expanded, its outer wall 140s towards through hole 110v side wall 110s extends.In addition,
Electric resistance structure 150, e.g. space 150b are formed at the outer wall 140s and through hole 110v of metal oxide layer 140 side wall
Between 110s.In embodiment, space 150b is for example formed at the outer wall 140s of metal oxide layer 140 bottom.This step
In, because the top surface 130a' on barrier layer 130 is less than the top surface 340a of metal level 340, therefore the space 150b that is formed
Top surface 150b-1 is also less than the top surface 140a of metal oxide layer 140.
Furthermore, in oxidation technology, the barrier layer 130 of an exposed portion may can also be oxidized and form electric resistance structure
150, e.g. metal oxide structures 150a.For example, barrier layer 130 is exposed to one of the surface outside metal level 340
Part can be oxidized in oxidation technology and form metal oxide structures 150a.In embodiment, metal oxide structures
150a material for example includes the oxide on barrier layer 130.For example, when the material on barrier layer 130 is titanium nitride, then metal
Oxide structure 150a material may include titanium oxynitrides.In this step, because the top surface 130a' on barrier layer 130 is less than gold
Belong to the top surface 340a of layer 340, therefore the metal oxide structures 150a formed top surface 150a-1 is also less than metal oxygen
The top surface 140a of compound layer 140.
So far, it is formed at the semiconductor structure 200 shown in Fig. 5 F (Fig. 2).In summary, in the present embodiment, metal oxidation
The thickness T2 of nitride layer 140 can be via the depth D1 of depression of regulation and control through hole 110v upper part 110r formation, barrier layer 130
The flatening process of thickness T1 and metal level 340 ' regulates and controls well.Also, above-mentioned technique have more with it is existing complementary
The advantage of metal-oxide semiconductor (MOS) (CMOS) process compatible.
Fig. 6 A~Fig. 6 G are refer to, it illustrates the manufacturer of the semiconductor structure 300 according to another embodiment of the present invention
The flow chart of method.
As figs. 6 a to 6 c, the insulation system 210 with a through hole 210v is formed, and forms conductive structure 220
In through hole 210v.The manufacture method for forming insulation system 210 for example comprises the following steps.
As shown in Figure 6A, clearance wall 211 is formed, wherein conductive structure 220 is filled in clearance wall 211, between causing
Gap wall 211 is around conductive structure 220.
In embodiment, laying (not being illustrated in schema) is more can be selectively formed in conductive structure 220 and insulation system
Between 210.For example, laying is initially formed on the inwall of insulation system 210, being subsequently formed conductive structure 220 in pad
On layer.
Then, as shown in Figure 6B, an interlayer dielectric material layers 413 are formed on clearance wall 211 and on conductive structure 220.
Then, as shown in Figure 6 C, a part of interlayer dielectric material layers 413 being located on conductive structure 220 are removed with formation
Interlayer dielectric layer 213 is on clearance wall 211, and wherein clearance wall 211 is collectively forming through hole 210v with interlayer dielectric layer 213.Implement
It is, for example, that the part interlayer dielectric material layers 413 being located on conductive structure 220 are removed with mask etch process in example, and is formed
Perforate 213r, and perforation 213r is connected to conductive structure 220 through interlayer dielectric layer 213.In embodiment, e.g. using for
The etching liquid that interlayer dielectric material layers 413 and conductive structure 220 have high selectivity is performed etching so that only part interlayer dielectric
Material layer 413 is etched removal, the destruction and structure of conductive structure 220 is not etched substantially.As shown in Figure 6 C, correspond to
The perforation 213r of interlayer dielectric layer 213 to house the space of conductive structure 220 corresponding to clearance wall 211 with being collectively forming insulation
The through hole 210v of structure 210.In embodiment, the height H1 that interlayer dielectric layer 213 (perforation 213r) has is about to be subsequently formed
Barrier layer thickness and metal oxide layer thickness totalling, be, for example,But this height H1 can be according to
Appropriate selection is done according to practical application, e.g. the need for the characteristic of resistance of element etc., is not limited with aforementioned range.
In the present embodiment, perforation 213r is further formed via the mode of interlevel dielectric deposition 213, due to thin film deposition
Technique has a high controling power for the uniformity of thickness, therefore perforation 213r height H1 has a high uniformity, and then after causing
Continuing the thickness of metal oxide layer 140 formed therein has high uniformity.Embodiments in accordance with the present invention, with semiconductor junction
Exemplified by structure 300 is contact resistive memory cell structure, the thickness of the insulating barrier of memory element has high uniformity, then stores
The resistance value of element can be controlled preferably, and then make resistive memory cell structure have preferably characteristic.
As shown in Figure 6 D, a barrier layer 130 ' is formed on conductive structure 220 and on through hole 110v side wall 110s, and
A metal level 340 ' is formed on barrier layer 130 '.In embodiment, barrier layer 130 ' and metal level 340 ' are for example formed at simultaneously
Fill up in perforation 213r.
As illustrated in fig. 6e, a flatening process is carried out to barrier layer 130 ' and metal level 340 ', to planarize barrier layer
130 ' and the surface of metal level 340 ', and form barrier layer 130 and metal level 340.In embodiment, being, for example, of flatening process
Learn mechanical milling tech.After planarization, as illustrated in fig. 6e, the top surface 130a on barrier layer 130 and the top surface of metal level 340
340a is flushed and is waited plane.After planarization, the top surface 130a on barrier layer 130 and the top surface 340a of metal level 340 can be with
Flushed with the top surface 210a systems of insulation system 210 and wait plane or the plane such as non-.In embodiment, as illustrated in fig. 6e, table is pushed up
The planes such as the top surface 210a systems of face 130a and top surface 340a and insulation system 210.
As fig 6 f illustrates, a part of barrier layer 130 on through hole 210v inwall 210s is removed.After this step,
The top surface 130a' on barrier layer 130 and the plane such as the top surface 340a systems of metal level 340 are non-.It is, for example, via one in embodiment
Etching technics removes this partial barrier 130, and using the quarter for barrier layer 130 and metal level 340 with high selectivity
Erosion liquid is performed etching so that only partial barrier 130 is etched removal, and the structure of metal level 340 is not etched substantially
Destruction.
As shown in Figure 6 G, an oxidation technology is carried out with metal oxide layer 340 to form metal oxide layer 140 in barrier layer
On 130 and electric resistance structure 150 is formed in the outer wall 140s of metal oxide layer 140 bottom, and form electrode material layer
160 on metal oxide layer 140.In embodiment, because barrier layer 130 can prevent going deep into for oxygen so that oxidation technology pair
It can be blocked on barrier layer 130 in the oxidation of metal level 340, therefore the depth of oxidation will not down diffuse to conductive structure
220, it thus can preferably control the thickness of metal oxide layer 140, the thickness of metal oxide layer 140 can also be compared with
Uniformly.
In embodiment, as shown in Figure 6 G, electrode material layer 160 is also formed on the top surface 210a of insulation system 210.
In oxidation technology, metal level 340 is oxidized and its volumetric expansion, therefore forms metal oxidation as shown in Figure 6 G
Nitride layer 140, wherein the metal oxide layer 140 expanded, its outer wall 140s towards through hole 210v side wall 210s extends.In addition,
Electric resistance structure 150, e.g. space 150b are formed at the outer wall 140s and through hole 210v of metal oxide layer 140 side wall
Between 210s.In embodiment, space 150b is for example formed at the outer wall 140s of metal oxide layer 140 bottom.
Furthermore, in oxidation technology, the barrier layer 130 of an exposed portion may can also be oxidized and form electric resistance structure
150, e.g. metal oxide structures 150a.For example, barrier layer 130 is exposed to one of the surface outside metal level 340
Part can be oxidized in oxidation technology and form metal oxide structures 150a.In embodiment, metal oxide structures
150a material for example includes the oxide on barrier layer 130.For example, when the material on barrier layer 130 is titanium nitride, then metal
Oxide structure 150a material may include titanium oxynitrides.
So far, it is formed at the semiconductor structure 300 shown in Fig. 6 G (Fig. 3).In summary, in the present embodiment, metal oxidation
The thickness T2 of nitride layer 140 can be via the regulation and control height H1 of interlayer dielectric layer 213, the thickness T1 and metal level 340 ' on barrier layer 130
Flatening process well regulate and control.Also, above-mentioned technique has more and existing CMOS work
The compatible advantage of skill.
Fig. 7 illustrates resistance-voltage curve of the semiconductor structure according to one embodiment of the invention and a comparative example.It is real
Apply in example, by taking semiconductor structure 100 as an example, remove behind a part of barrier layer 130 on through hole 110v inwall 110s, connect
Electric resistance structure 150 (such as metal oxide structures 150a and space 150b) can be formed in metal oxidation by the oxidation technology carried out
The outer wall 140s of nitride layer 140 bottom.Relatively, the semiconductor structure of comparative example does not carry out removing positioned at the interior of through hole 110v
The technique on a part of barrier layer 130 on wall 110s, thus oxidation technology only can oxidation barrier layer 130 top surface, and this oxygen
The top surface of change and the top surface of metal oxide layer 140 surface, therefore in the semiconductor structure of comparative example altogether, it is impossible to formed
Electric resistance structure 150 is in the outer wall 140s of metal oxide layer 140 bottom.Only have one compared to the semiconductor structure of comparative example
Electric resistance structure 150 of the layer thin oxide layer in the top surface on barrier layer 130, the semiconductor structure 100 of embodiment has larger
Depth, therefore can more effectively isolate electrode material layer 160 and conductive structure 120, reduction electrode material layer 160 and conductive knot
Electrical interference between structure 120, and then improve the breakdown voltage of the semiconductor structure 100 of embodiment.
As shown in fig. 7, curve I represents resistance-voltage curve of the semiconductor structure of comparative example, curve II represents embodiment
Semiconductor structure 100 resistance-voltage curve.As shown in fig. 7, the breakdown voltage of the semiconductor structure of comparative example is about
5.5~6V, and the semiconductor structure 100 of embodiment can have at least more than 8V breakdown voltage, far above partly leading for comparative example
The breakdown voltage of body structure.
In summary, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is when depending on being defined that appended claims scope is defined.
Claims (10)
1. a kind of semiconductor structure, including：
Insulation system, with a through hole (via)；
Barrier layer (stop layer), is formed in the through hole；
Metal oxide layer, is formed on the barrier layer；
Electric resistance structure (resistance structure), is formed at a bottom of an outer wall of the metal oxide layer；And
Electrode material layer, is formed on the metal oxide layer；
Wherein, the electric resistance structure includes at least one of metal oxide structures or space.
2. semiconductor structure according to claim 1, is further included：
Conductive structure, is formed in the through hole, and wherein the barrier layer is formed on the conductive structure.
3. the thickness of semiconductor structure according to claim 1, the wherein barrier layer isThe metal is aoxidized
The thickness of nitride layer is
4. semiconductor structure according to claim 1, the wherein barrier layer include metal nitride or inert metal
At least one of (inert metal).
5. a kind of resistive memory cell (Resistive random access memory unit) structure, including：
Insulation system, with a through hole (via)；
Barrier layer, is formed in the through hole；
Memory element (memory element), is formed on the barrier layer；
Electric resistance structure, is formed at a bottom of an outer wall of the memory element；And
Top electrode layer, is formed on the memory element；
Wherein, the electric resistance structure includes at least one of metal oxide structures or space.
6. resistive memory cell structure according to claim 5, is further included：
Contact structures (contact structure), are formed in the through hole, wherein the barrier layer is formed at the contact structures
On.
7. resistive memory cell structure according to claim 5, the wherein barrier layer include titanium nitride (TiN), nitridation
At least one of tantalum (TaN), tungsten nitride (WN), golden (Au) and platinum (Pt).
8. a kind of manufacture method of semiconductor structure, including：
An insulation system is formed, with a through hole (via)；
A barrier layer is formed in the through hole and on the side wall of the through hole；
A metal level is formed on the barrier layer；
Remove a part of barrier layer on an inwall of the through hole；
An oxidation technology is carried out to aoxidize the metal level to form a metal oxide layer on the barrier layer and forming an electricity
Structure is hindered in a bottom of an outer wall of the metal oxide layer；And
An electrode material layer is formed on the metal oxide layer；
Wherein, the oxidation technology is carried out more to aoxidize the barrier layer of an exposed portion to form the electric resistance structure.
9. the manufacture method of semiconductor structure according to claim 8, is further included：
A conductive structure is formed in the through hole, wherein the barrier layer is more formed on the conductive structure.
10. the manufacture method of semiconductor structure according to claim 8, wherein being to remove to be located at via an etching technics to be somebody's turn to do
The part barrier layer on the inwall of through hole.
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| CN102136547A (en) * | 2010-01-25 | 2011-07-27 | 旺宏电子股份有限公司 | Programmable metallization cell with iron buffer layers |
| CN102142442A (en) * | 2009-11-17 | 2011-08-03 | 三星电子株式会社 | Semiconductor device and forming method thereof |
| CN103035837A (en) * | 2012-05-11 | 2013-04-10 | 上海华虹Nec电子有限公司 | Structure and manufacturing method of semiconductor device |
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| CN102142442A (en) * | 2009-11-17 | 2011-08-03 | 三星电子株式会社 | Semiconductor device and forming method thereof |
| CN102136547A (en) * | 2010-01-25 | 2011-07-27 | 旺宏电子股份有限公司 | Programmable metallization cell with iron buffer layers |
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