TWI521576B - Resistive random-access memory and method for fabricating the same - Google Patents

Description

Resistive memory and manufacturing method thereof

The present invention relates to a resistive random-access memory (RRAM) and a method of fabricating the same.

Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electrical products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

However, there are still many challenges to overcome before mass production of RRAM. One of the challenges is the variation in the operating current-voltage (I-V) characteristics of the RRAM, which is the path from which a plurality of possible conductive filaments are formed between the top and bottom electrodes. Larger electrodes create more likely conductive filament formation paths that increase the variation of the I-V characteristics of the RRAM operation. In order to minimize these variations, the most straightforward approach is to shrink the electrodes.

On the other hand, when the bottom electrode material of the conventional RRAM is formed, a columnar crystal structure is often formed on the surface thereof, so that the uniformity of the subsequent inter-electrode dielectric layer deposition is poor, which affects the formation path of the conductive filament. generate, Increase the variation of the I-V characteristics of the RRAM operation.

An embodiment of the present invention provides a method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer An electric layer; forming a bottom electrode in the opening, wherein the bottom electrode is coplanar with the stop layer; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric layer; The top electrode material and the dielectric layer are patterned to define a top electrode and an inter-electrode dielectric layer thereunder, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the second surface The area is larger than the area of the first surface.

Another embodiment of the present invention provides a resistive memory comprising: a substrate; a dielectric layer over the substrate; a stop layer over the dielectric layer; and an opening through the stop layer and the dielectric layer a bottom electrode, in the opening, and coplanar with the stop layer; an inter-electrode dielectric layer over the bottom electrode and extending over a portion of the stop layer; and a top electrode dielectrically interposed between the electrodes Above the layer, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the area of the second surface is larger than the area of the first surface.

100, 200‧‧‧RRAM

102‧‧‧Base

112a, 250‧‧‧ bottom electrode

116a‧‧‧ top electrode

104, 104a‧‧‧ conductive layer

106‧‧‧Dielectric layer

108‧‧‧stop layer

110‧‧‧ openings

112, 230, 230a, 240, 240a‧‧‧ bottom electrode materials

114‧‧‧Dielectric layer

114a‧‧‧Interelectrode dielectric layer

116‧‧‧Top electrode material

106a, 118‧‧‧ filament structure

116S‧‧‧ lower surface

112S‧‧‧ upper surface

220‧‧‧ lining

1A-1H are schematic cross-sectional views showing an intermediate stage of fabricating the RRAM 100 in accordance with an embodiment of the present invention.

2A-2E are schematic cross-sectional views showing an intermediate stage of fabricating the RRAM 200 in accordance with another embodiment of the present invention.

Several different embodiments are set forth below in accordance with various features of the invention. The specific elements and arrangements of the present invention are intended to be simplified, but the invention is not limited to these embodiments. For example, a description of forming a first element on a second element can include an embodiment in which the first element is in direct contact with the second element, and also includes having additional elements formed between the first element and the second element such that An embodiment in which one element is not in direct contact with the second element. In addition, the present invention is represented by the repeated reference numerals and/or letters in the different examples for the sake of brevity, but does not represent a particular relationship between the various embodiments and/or structures.

1A to 1H are schematic cross-sectional views showing a method of manufacturing the RRAM 100 according to the first embodiment of the present invention. Referring to FIG. 1A, a conductive material 104 is formed on a substrate 102. The substrate 102 can be a germanium substrate, a germanium germanium substrate, a tantalum carbide substrate, a silicon-on insulator (SOI) substrate, a multi-layered substrate, a gradient substrate, or a hybrid orientation. Substrate, etc. In one embodiment, substrate 102 is a wafer. Conductive material 104 is, for example, tungsten, copper, aluminum, silver, gold, or other suitable electrically conductive material (eg, doped polysilicon). Next, referring to FIG. 1B, the conductive material 104 is patterned to form the conductive layer 104a. In the embodiment of the present invention, the conductive material 104 can be patterned by performing a lithography and dry etching process, such as reactive ion etching (RIE).

Next, referring to FIG. 1C, a dielectric layer 106 and a stop layer 108 over the dielectric layer 106 are formed over the substrate 102. Dielectric layer 106 can include hafnium oxide, tantalum nitride, hafnium oxynitride, low-k dielectrics, or other suitable dielectric materials. In some embodiments, the stop layer 108 is nitrogen-containing Materials such as tantalum nitride and niobium oxynitride. The method of forming the dielectric layer 106 and the stop layer 108 is, for example, chemical vapor deposition (CVD) or spin on coating.

Referring to FIG. 1D, after the dielectric layer 106 and the stop layer 108 are formed, an opening 110 is formed through the dielectric layer 106 and the stop layer 108. The opening 110 exposes a portion of the conductive layer 104a. The method of forming the opening 110 may include a dry etching process such as RIE. It is noted that a liner (not shown) may be selectively formed on the sidewalls and bottom of the opening 110 prior to proceeding to subsequent steps.

Next, referring to FIG. 1E, a bottom electrode material 112 is formed in the opening 110 and on the stop layer. The bottom electrode material 112 is, for example, titanium, titanium nitride, platinum, tungsten, aluminum, or other suitable electrode material. The method of forming the bottom electrode material is, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic CVD (MOCVD), or other suitable deposition process.

Next, referring to FIG. 1F, a portion of the bottom electrode material 112 is removed to form the bottom electrode 112a in the opening 110. The method of removing a portion of the bottom electrode material 112 is, for example, using the stop layer 108 as a polishing stop layer, and performing a planarization process (such as chemical mechanical polishing (CMP)) on the bottom electrode material to cause the upper surface 112S of the bottom electrode 112a to stop. The top surface of layer 108 is coplanar. Wherein, the planarization process can simultaneously remove the liner (if present). Different from the conventional RRAM, the present invention can effectively form a flat upper surface on the bottom electrode 112a by forming the ground electrode material 112 in the opening 108 and performing a planarization process using the stop layer 108 as a polishing stop layer. 112S, thereby improving the uniformity of the dielectric layer and the top electrode between the subsequent electrodes, avoiding the problem of the columnar crystal structure formed by the conventional RRAM on the surface of the bottom electrode, and greatly reducing the operation of the RRAM Variation of I-V characteristics.

Referring to FIG. 1G, after forming the bottom electrode 112a, a dielectric layer 114 and a top electrode material 116 are sequentially formed on the surfaces of the stop layer 108 and the bottom electrode 112a. Dielectric layer 114 can include hafnium oxide, tantalum nitride, hafnium oxynitride, high-k dielectrics, or other suitable dielectric materials. Wherein, the high dielectric constant material may include a metal oxide, for example, Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb An oxide of a metal such as Dy, Ho, Er, Tm, Yb, Lu, or the like. In an embodiment, the dielectric layer 114 is, for example, hafnium oxide (HfO ₂ ). The top electrode material 116 can comprise titanium, titanium nitride, platinum, tungsten, aluminum, or other suitable electrode material.

Next, referring to FIG. 1H, the dielectric layer 114 and the top electrode material 116 are patterned to define the inter-electrode dielectric layer 114a and the top electrode 116a, respectively, to complete the fabrication of the RRAM 100. The inter-electrode dielectric layer 114a and the top electrode 116a partially extend to the stop layer 108 on both sides of the opening 110. The method of patterning the dielectric layer 114 and the top electrode material 116 can be performed, for example, by performing a lithography and dry etching process (e.g., RIE). In the embodiment of the present invention, the top electrode 116a has a lower surface 116S, the lower surface 116S is opposite to the upper surface 112S of the bottom electrode 112a, and the area of the lower surface 116S of the top electrode 116a is larger than the area of the upper surface 112S of the bottom electrode 112a. By forming the above-mentioned asymmetric MIM structure, the present invention can effectively reduce the formation area of the filament structure 118 on the upper surface 112S of the bottom electrode 112a, thereby greatly reducing the variation of the I-V characteristics of the RRAM operation.

In addition to the above embodiments, the RRAM of the present invention can further utilize the bottom electrode of the composite structure depending on the material selection of the inter-electrode dielectric layer 114a. The RRAM 200 of another embodiment of the present invention will be described in detail below with reference to FIGS. 2A-2E. For the sake of brevity, components identical or similar to RRAM 100 are labeled with the same reference numerals. Marked, and the same process steps will not be described again.

Please refer to FIG. 2A, which is a schematic diagram following the step of FIG. 1D. In an embodiment, after the opening 110 is formed, a liner 220 may be selectively formed in the opening 110 and the stop layer 108, which acts to reduce stress. The liner 220 can be a conductive material such as titanium, titanium nitride, or a combination of the foregoing. The liner 220 is in electrical contact with the conductive layer 104a. Next, a first bottom electrode material 230 is formed in the opening 110 and above the stop layer 108. The first bottom electrode material 230 can comprise tungsten, copper, aluminum, or other suitable electrode material. In an embodiment, the first bottom electrode material 230 is, for example, tungsten. The method of forming the first bottom electrode material 230 may include PVD, ALD, MOCVD, or other suitable deposition process.

Next, referring to FIG. 2B, the first bottom electrode material 230 on the stop layer 108 and partially located in the opening 110 is removed to form the first bottom electrode 230a. The method of removing the first bottom electrode material 230 may include a dry etching process, such as an RIE process. In the step of FIG. 2B, the stop layer 108 acts as an etch stop layer, and this step simultaneously removes a portion of the liner 220 (if present) outside of the opening 110.

Next, as shown in FIG. 2C, a second bottom electrode material 240 is formed over the first bottom electrode 230a and the stop layer 108. The second bottom electrode material 240 can comprise titanium, platinum, titanium nitride, or other suitable electrode material. In an embodiment, the second bottom electrode material 240 is, for example, titanium nitride.

Next, referring to FIG. 2D, a portion of the second bottom electrode material 240 is removed to form a second bottom electrode 240a in the opening 110 to complete the bottom electrode 250 of the composite structure of the present embodiment. As shown in FIG. 2D, the bottom electrode 250 includes a first bottom electrode 230a and a second bottom electrode material 240a. The method of removing a portion of the second bottom electrode material 240 is performed by, for example, stopping the layer 108 as a polishing stop layer to planarize the second bottom electrode material 240. A process, such as chemical mechanical polishing (CMP), causes the upper surface 250S of the bottom electrode 250 to be coplanar with the top surface of the stop layer 108.

Finally, as shown in FIG. 2E, the inter-electrode dielectric layer 114a and the top electrode 116a are formed on the stop layer 108 and the bottom electrode 250 to complete the structure of the RRAM 200 of the present embodiment. The method of forming the inter-electrode dielectric layer 114a and the top electrode 116a is the same as that of the first to third figures and the related paragraphs, and therefore will not be described again. The top electrode 116a of the RRAM 200 has a lower surface 116S opposite the upper surface 250S of the bottom electrode 250, and the area of the lower surface 116S of the top electrode 116a is larger than the area of the upper surface 250S of the bottom electrode 250a. It should be noted that, in this embodiment, by forming the bottom electrode of the composite material, the resistance of the RRAM can be effectively reduced, and the operational efficiency of the RRAM can be improved.

The present invention forms a bottom electrode material in an opening in a process of fabricating an RRAM, and polishes the bottom electrode material using a stop layer to remove columnar crystals naturally formed by the bottom electrode material. In this way, a bottom electrode having a flat surface can be formed, thereby improving the uniformity of the subsequently deposited inter-electrode dielectric layer and greatly reducing variations in the I-V characteristics of the RRAM operation. In addition, the present invention can effectively reduce the formation area of the filament structure on the upper surface of the bottom electrode by forming an asymmetric MIM structure (ie, the lower surface of the top electrode is larger than the upper surface of the bottom electrode), thereby greatly reducing the RRAM. Variation in the IV characteristics of the operation.

Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Resistive memory

102‧‧‧Base

104a‧‧‧ Conductive layer

106‧‧‧Dielectric layer

108‧‧‧stop layer

112a‧‧‧ bottom electrode

114a‧‧‧Interelectrode dielectric layer

116a‧‧‧ top electrode

118‧‧‧filament structure

112S‧‧‧ upper surface

116S‧‧‧ lower surface

Claims (12)

A method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer Forming a bottom electrode in the opening, wherein the bottom electrode is coplanar with the stop layer; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric And patterning the top electrode material and the dielectric layer to define a top electrode and an inter-electrode dielectric layer therebelow, wherein the top electrode has a second surface and the bottom electrode is first The surface is opposite, and the area of the second surface is larger than the area of the first surface, wherein the step of forming the bottom electrode comprises: depositing a bottom electrode material to fill the opening and covering the stop layer; and stopping the layer The bottom electrode material is polished as a polishing stop layer to remove the bottom electrode material other than the opening. A method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer Forming a bottom electrode in the opening, wherein the bottom electrode is associated with the stop layer Coplanar; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric layer; and patterning the top electrode material and the dielectric layer to define a a top electrode and an inter-electrode dielectric layer thereunder, wherein the top electrode has a second surface opposite to a first surface of the bottom electrode, and an area of the second surface is larger than an area of the first surface, wherein the top surface is formed The step of the bottom electrode includes: depositing a first bottom electrode material to fill the opening and covering the stop layer; recessing the bottom electrode material to partially fill the first bottom electrode material in the opening; depositing a first A second bottom electrode material fills the remaining portion of the opening and covers the stop layer; and the second bottom electrode material is ground with the stop layer as a polishing stop layer to remove the second bottom electrode material other than the opening. The method of manufacturing a resistive memory according to claim 2, wherein the first bottom electrode material comprises tungsten, copper, aluminum, or a combination thereof, and the second bottom electrode material comprises titanium nitride and titanium. , platinum, or a combination of the foregoing. The method of manufacturing a resistive memory according to claim 1 or 2, wherein the stop layer comprises tantalum nitride, hafnium oxynitride, or a combination thereof. The method of manufacturing the resistive memory of claim 1 or 2, wherein before the step of forming the dielectric layer, further comprising: forming a conductive layer on the substrate; The conductive layer is patterned, wherein the conductive layer is exposed at the step of forming the opening. The method for manufacturing a resistive memory according to the first or second aspect of the invention, further comprising: forming a liner on the bottom and the side wall of the opening before the step of forming the bottom electrode. A resistive memory comprising: a substrate; a dielectric layer over the substrate; a stop layer over the dielectric layer; an opening through the stop layer and the dielectric layer; An electrode, in the opening, and coplanar with the stop layer; an inter-electrode dielectric layer over the bottom electrode and extending over a portion of the stop layer; and a top electrode interposed between the electrodes Above the electrical layer, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the second surface has an area greater than an area of the first surface. The resistive memory of claim 7, wherein the bottom electrode comprises: a first bottom electrode material partially filled in the opening; and a second bottom electrode material located at the first bottom electrode Above the material, wherein a top surface of the second bottom electrode material is coplanar with the stop layer. The resistive memory of claim 8, wherein the first bottom electrode material comprises tungsten, copper, aluminum, or a combination thereof, and the second bottom electricity The polar material includes titanium nitride, titanium, platinum, or a combination of the foregoing. The resistive memory of claim 7, wherein the stop layer comprises tantalum nitride, hafnium oxynitride, or a combination thereof. The resistive memory of claim 7, further comprising: a conductive layer under the dielectric layer, wherein the opening exposes a portion of the conductive layer. The resistive memory of claim 7, further comprising: a liner layer lining the sidewall and the bottom of the opening, wherein the bottom electrode is filled on the liner in the opening.