TWI495087B - Resistance memeory device - Google Patents

Description

Resistive memory element

This invention relates to a semiconductor component, and more particularly to a resistive memory component.

Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electrical products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

However, there are still many challenges to overcome before mass production of RRAM. One of the challenges is the variation in the operating current-voltage (I-V) characteristics of the RRAM, which is the path from which a plurality of possible conductive filaments are formed between the top and bottom electrodes. Larger electrodes create more likely conductive filament formation paths that increase the variation in the operational I-V characteristics of the RRAM. In order to minimize these variations, the most straightforward approach is to shrink the electrodes. However, it is difficult to further reduce the electrode due to the limitation of the lithography resolution.

On the other hand, the conventional RRAM manufacturing method requires at least two patterning steps. First, a first patterning step is performed to form in the dielectric layer. Conductor plug. Next, a second patterning step is performed to form a variable resistance memory cell composed of a bottom electrode, a variable resistance layer, and a top electrode on the conductor plug. Two different patterning steps have their own critical dimension (CD) variations. In addition, the alignment error between the two patterning steps needs to be considered. The above two reasons will increase the size of the resistive memory cell.

In view of the above, the present invention provides a resistive memory element that reduces variations in its I-V characteristics and reduces its memory cell size.

The invention provides a resistive memory element comprising a dielectric layer, a conductor layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on the substrate. The dielectric layer has a first opening formed by a lower opening and an upper opening. The conductor layer fills the lower opening. The bottom electrode is disposed on the bottom surface of the upper opening and at least a portion of the sidewall. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the bottom electrode and the top electrode.

In an embodiment of the invention, the lower opening is aligned with the side wall of the upper opening.

In an embodiment of the invention, the bottom electrode is exposed to the upper portion of the sidewall of the upper opening.

In an embodiment of the invention, the thickness of the bottom electrode on the sidewall of the upper opening is smaller than the thickness of the bottom electrode on the bottom surface of the upper opening.

In an embodiment of the invention, the dielectric layer further has a second opening, and the conductor layer fills the second opening.

In an embodiment of the invention, the first opening and the second opening penetrate through the dielectric layer.

In an embodiment of the invention, the resistive memory device further includes a metal layer disposed on the dielectric layer and electrically connected to the conductive layer in the top electrode and the second opening.

In an embodiment of the invention, the bottom electrode is disposed on a bottom surface and an entire sidewall of the upper opening.

In an embodiment of the invention, the thickness of the bottom electrode on the sidewall of the upper opening is substantially equal to the thickness of the bottom electrode on the bottom surface of the upper opening.

In an embodiment of the invention, the variable resistance layer is further disposed on the dielectric layer around the first opening.

In an embodiment of the invention, the dielectric layer further has a second opening, and the conductor layer fills the second opening.

In an embodiment of the invention, the first opening and the second opening penetrate through the dielectric layer.

In an embodiment of the invention, the variable resistance layer is exposed to the conductor layer in the second opening.

In an embodiment of the invention, the resistive memory device further includes a metal layer disposed on the dielectric layer and electrically connected to the conductive layer in the top electrode and the second opening.

In an embodiment of the invention, the conductor layer is electrically connected to another conductor layer under the dielectric layer.

In an embodiment of the invention, the other conductor layer comprises doping Zone, polysilicon layer or metal layer.

Based on the above, the resistive memory element of the present invention is formed by a self-aligned process, thereby avoiding the problem of conventional alignment errors and easily achieving the requirement of small component sizes. Also. Since the resistive memory element of the present invention has a smaller top electrode, it is possible to reduce the possible conductive filament formation path and reduce variations in the operational I-V characteristics of the RRAM.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

1A to 1E are schematic cross-sectional views showing a method of fabricating a resistive memory device according to a first embodiment of the present invention.

Referring to FIG. 1A, a dielectric layer 102 is formed on the substrate 100. Substrate 100 can be a semiconductor substrate, such as a germanium substrate. The material of the dielectric layer 102 includes hafnium oxide, tantalum nitride or hafnium oxynitride, and the method of forming the same includes performing chemical vapor deposition (CVD). In addition, the dielectric layer 102 has a first opening 104 and a second opening 106 that extend through the dielectric layer 102 . The first opening 104 is constituted by the lower opening 103 and the upper opening 105, and the lower opening 103 is aligned with the side wall of the upper opening 105. The method of forming the first opening 104 and the second opening 106 includes performing a patterning step of lithography etching.

Next, the conductor layer 108 is filled in the first opening 104 and the second opening 106. The material of the conductor layer 108 includes tungsten. It is particularly noted that the conductor layer 108 fills the second opening 106 and the lower opening 103 of the first opening 104. The method of forming the conductor layer 108 includes forming a conductive material layer (not shown) on the substrate 100, and the conductive material layer fills the first opening 104 and the second opening 106. Next, a patterning step is performed to remove the layer of conductor material in the upper opening 105 of the first opening 104.

In addition, the conductor layer 108 can be electrically connected to another conductor layer under the dielectric layer 102. In an embodiment, the other conductor layer may be a doped region 101 in the substrate 100, as shown in FIG. 1A. In another embodiment, the other conductor layer may also be a polysilicon gate or metal layer (not shown) on the substrate 100.

Referring to FIG. 1B, a bottom electrode material layer 110 is formed on the substrate 100. The material of the bottom electrode material layer 110 includes titanium nitride, and a method of forming the same includes performing physical vapor deposition (PVD). Due to the step coverage effect of the physical vapor deposition method, the thickness of the bottom electrode material layer 110 on the sidewalls of the upper opening 105 may be less than the thickness of the bottom electrode material layer 110 on the bottom surface of the upper opening 105. Next, a sacrificial layer 111 is formed on the dielectric layer 102, and the sacrificial layer 111 is filled in the upper opening 105. The material of the sacrificial layer 111 is, for example, a photoresist or yttrium oxide.

Referring to FIG. 1C, a portion of the sacrificial layer 111 is removed until the upper surface of the bottom electrode material layer 110 is exposed. A method of removing a portion of the sacrificial layer 111 includes performing a chemical mechanical polishing (CMP). Then, a portion of the bottom electrode material layer 110 is removed to form the bottom electrode 110a. The bottom electrode 110a exposes the upper surface of the dielectric layer 102 and the upper portion of the sidewall of the upper opening 105. A method of removing a portion of the bottom electrode material layer 110 includes performing a wet etching process. Thereafter, the remaining sacrificial layer 111 is removed.

Referring to FIG. 1D, a variable resistance material layer 112 and a top electrode material layer 114 are formed on the substrate 100, and the variable resistance material layer 112 and the top electrode material layer 114 are filled in the upper opening 105. The material of the variable resistance material layer 112 includes a transition metal oxide such as HfO ₂ or ZrO ₂ , and a method of forming the same includes performing an atomic layer deposition method (ALD). The material of the top electrode material layer 114 includes titanium nitride (for example, Ti/TiN), and the formation method thereof includes performing atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

Referring to FIG. 1E, the variable resistance material layer 112 and the top electrode material layer 114 outside the upper opening 105 are removed to form the variable resistance layer 112a and the top electrode 114a. The bottom electrode 110a, the variable resistance layer 112a, and the top electrode 114a constitute the variable resistance memory cell 116 of the present invention. The method of removing the variable resistance material layer 112 and the top electrode material layer 114 outside the upper opening 105 includes performing a chemical mechanical polishing method. In particular, since this removal step utilizes a chemical mechanical polishing method instead of the conventional etch back method, the antenna effect caused by the charge accumulation of the etch back method can be avoided. Next, a metal layer 118 is formed on the dielectric layer 102, and the metal layer 118 is electrically connected to the top electrode 114a and the conductor layer 108 of the second opening 106. The material of the metal layer 118 includes an aluminum-copper alloy, and the method of forming the same includes performing a chemical vapor deposition method. So far, the resistive memory element 10 of the first embodiment is completed.

In the first embodiment, the variable resistance memory cell 116 including the bottom electrode 110a, the variable resistance layer 112a, and the top electrode 114a is formed by a deposition, etching/polishing process, that is, the variable resistance memory cell 116 is It is formed by a self-aligned process without using a lithography process. In this way, the method of the present invention can eliminate the formation of a variable resistance memory cell as compared with the conventional method. The patterning step of 116. In addition, the formed top electrode 114a has a small area, thereby reducing the possible conductive filament formation path and reducing variations in the operational I-V characteristics of the RRAM.

Hereinafter, the resistive memory element 10 of the present invention will be described with reference to FIG. 1E. The resistive memory element 10 includes a dielectric layer 102, a conductor layer 108, a bottom electrode 110a, a variable resistance layer 112a, and a top electrode 114a. The dielectric layer 102 is disposed on the substrate 100. The dielectric layer 102 has a first opening 104 formed by a lower opening 103 and an upper opening 105, and the lower opening 103 is aligned with a sidewall of the upper opening 105. The conductor layer 108 fills the lower opening 103, and the conductor layer 108 is electrically connected to another conductor layer (for example, the doping region 101) under the dielectric layer 102. The bottom electrode 110a is disposed on a bottom surface and at least a portion of the sidewall of the upper opening 105. In this embodiment, the bottom electrode 110a exposes the upper portion of the sidewall of the upper opening 105. The top electrode 114a is disposed in the upper opening 105. The variable resistance layer 112a is disposed between the bottom electrode 110a and the top electrode 114a.

In particular, in this embodiment, the bottom electrode 110a exposes the upper portion of the sidewall of the upper opening 105. This configuration can avoid the short circuit problem caused by the bottom electrode 110a and the top electrode 114a being too close to the top end of the upper opening 105. In addition, since the thickness of the bottom electrode 110a on the sidewall of the upper opening 105 is smaller than the thickness of the bottom electrode 110a on the bottom surface of the upper opening 105, the operating region A of the variable resistance memory cell 116 is limited to the bottom electrode 110a and the top electrode 114a. The shortest path block, as shown in Figure 1E.

Moreover, in the first embodiment, the dielectric layer 102 further has a second opening 106, and the conductor layer 108 fills the second opening 106 more. In addition, resistance type The component 10 further includes a metal layer 118 disposed on the dielectric layer 102 and electrically connected to the conductor layer 108 of the top electrode 114a and the second opening 106.

Second embodiment

2A to 2E are schematic cross-sectional views showing a method of fabricating a resistive memory device according to a second embodiment of the present invention.

Referring to FIG. 2A, a dielectric layer 202 is formed on the substrate 200. The dielectric layer 202 has a first opening 204 and a second opening 206 that extend through the dielectric layer 202. The first opening 204 is constituted by the lower opening 203 and the upper opening 205, and the lower opening 203 is aligned with the side wall of the upper opening 205. Next, the conductor layer 208 is filled in the first opening 204 and the second opening 206. The conductor layer 208 fills the second opening 206 and the lower opening 203 of the first opening 204. In addition, the conductor layer 208 can be electrically connected to another conductor layer (eg, the doping region 201) under the dielectric layer 202.

Referring to FIG. 2B, a bottom electrode 210 is formed on the bottom surface of the upper opening 205 and the entire sidewall. A method of forming the bottom electrode 210 includes conformingly forming a bottom electrode material layer (not shown) on the substrate 200. The material of the bottom electrode material layer 210 includes titanium nitride, and the method of forming the same includes performing chemical vapor deposition (CVD). In this embodiment, the thickness of the bottom electrode material layer on the sidewalls of the upper opening 105 is substantially equal to the thickness of the bottom electrode material layer on the bottom surface of the upper opening 105. Thereafter, the bottom electrode material layer outside the upper opening 205 is removed.

Referring to FIG. 2C, a variable resistance material layer 212 and a top electrode material layer 214 are formed on the substrate 200, and the variable resistance material layer 212 and the top electrode material layer 214 are filled in the upper opening 205. The material of the variable resistance material layer 212 includes a transition metal oxide (for example, HfO ₂ or ZrO ₂ ), and a method of forming the same includes performing an atomic layer deposition method. The material of the top electrode material layer 214 includes titanium nitride (for example, Ti/TiN), and the formation method thereof includes performing atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

Referring to FIG. 2D, the top electrode material layer 214 outside the upper opening 205 is removed to form the top electrode 214a. The method of removing the top electrode material layer 214 outside the upper opening 205 includes performing a chemical mechanical polishing (CMP) with the variable resistance material layer 112 as a polishing stop layer. In particular, since this removal step utilizes a chemical mechanical polishing method instead of the conventional etch back method, the antenna effect caused by the charge accumulation of the etch back method can be avoided.

Thereafter, a portion of the variable resistance material layer 212 is removed to form a variable resistance layer 212a that exposes the second opening 206. Specifically, the variable resistance layer 212a extends along the inner wall of the upper opening 205 and is disposed on the dielectric layer 202 around the upper opening 205. The method of removing a portion of the variable resistance material layer 212 includes a patterning process for photolithography etching. The bottom electrode 210, the variable resistance layer 212a, and the top electrode 214a constitute the variable resistance memory cell 216 of the present invention.

Referring to FIG. 2E, a metal layer 218 is formed on the dielectric layer 202, and the metal layer 218 is electrically connected to the top electrode 214a and the conductor layer 208 of the second opening 206. The material of the metal layer 218 includes an aluminum-copper alloy, and the method of forming the same includes performing a chemical vapor deposition method or a physical vapor deposition method. So far, the resistive memory element 20 of the second embodiment has been completed.

In the second embodiment, the deposition, etching/polishing process is used to form The variable resistance memory cell 216 including the bottom electrode 210, the variable resistance layer 212a, and the top electrode 214a, that is, the variable resistance memory cell 216 is formed by a self-aligned process, without using a lithography process. In addition, the formed top electrode 214a has a small area, thereby reducing the possible conductive filament formation path and reducing variations in the operational I-V characteristics of the RRAM.

Hereinafter, the resistive memory element of the present invention will be described with reference to Fig. 2E. The resistive memory element 20 includes a dielectric layer 202, a conductor layer 208, a bottom electrode 210, a variable resistance layer 212a, and a top electrode 214a. The dielectric layer 202 is disposed on the substrate 200. The dielectric layer 202 has a first opening 204 formed by a lower opening 203 and an upper opening 205, and the lower opening 203 is aligned with a sidewall of the upper opening 205. The conductor layer 208 fills the lower opening 203, and the conductor layer 208 is electrically connected to another conductor layer (for example, the doping region 201) under the dielectric layer 202. The bottom electrode 210 is disposed on the bottom surface and the entire sidewall of the upper opening 205. The top electrode 214a is disposed in the upper opening 205. The variable resistance layer 212a is disposed between the bottom electrode 210 and the top electrode 214a.

Moreover, in the second embodiment, the dielectric layer 202 further has a second opening 206, and the conductor layer 208 fills the second opening 206 more. In addition, the resistive memory device 20 further includes a metal layer 218 disposed on the dielectric layer 202 and electrically connected to the top electrode 214a and the conductor layer 208 of the second opening 206.

In summary, the resistive memory device of the present invention is formed by a self-aligned process, thereby avoiding the problem of conventional alignment errors and easily achieving the requirements of small component sizes. Also. Since the resistive memory element of the present invention has a small top electrode, the possible conductive filament formation path can be reduced The path reduces the variation of the I-V characteristics of the RRAM operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧Resistive memory components

100, 200‧‧‧ base

101, 201‧‧‧Doped area

102, 202‧‧‧ dielectric layer

103, 203‧‧‧ lower opening

104, 204‧‧‧ first opening

105, 205‧‧‧ upper opening

106, 206‧‧‧ second opening

108, 208‧‧‧ conductor layer

110a, 210‧‧‧ bottom electrode

112a, 212a‧‧‧variable resistance layer

114a, 214a‧‧‧ top electrode

118, 218‧‧‧ metal layer

111‧‧‧ Sacrifice layer

110‧‧‧ bottom electrode material layer

112, 212‧‧‧Variable resistance material layer

114, 214‧‧‧ top electrode material layer

116, 216‧‧‧variable resistance memory cells

A‧‧‧ operating area

1A to 1E are schematic cross-sectional views showing a method of fabricating a resistive memory device according to a first embodiment of the present invention.

2A to 2E are schematic cross-sectional views showing a method of fabricating a resistive memory device according to a second embodiment of the present invention.

10‧‧‧Resistive memory components

100‧‧‧Base

101‧‧‧Doped area

102‧‧‧ dielectric layer

103‧‧‧lower opening

104‧‧‧First opening

105‧‧‧ upper opening

106‧‧‧second opening

108‧‧‧Conductor layer

110a‧‧‧ bottom electrode

112a‧‧‧Variable Resistance Layer

114a‧‧‧ top electrode

116‧‧‧Variable Resistor Memory Cell

118‧‧‧metal layer

A‧‧‧ operating area

Claims (16)

A resistive memory device comprising: a dielectric layer disposed on a substrate, the dielectric layer having a first opening formed by a lower opening and an upper opening; a conductor layer filling the lower opening; a bottom electrode, configured And a top electrode disposed in the upper opening and not in contact with the sidewall of the upper opening; and a variable resistance layer disposed on the bottom electrode and the bottom surface Between the top electrodes. The resistive memory element of claim 1, wherein the lower opening is aligned with a sidewall of the upper opening. The resistive memory element of claim 1, wherein the bottom electrode exposes an upper portion of a sidewall of the upper opening. The resistive memory device of claim 3, wherein a thickness of the bottom electrode on a sidewall of the upper opening is smaller than a thickness of the bottom electrode on a bottom surface of the upper opening. The resistive memory device of claim 1, wherein the dielectric layer further has a second opening, and the conductor layer further fills the second opening. The resistive memory device of claim 5, wherein the first opening and the second opening extend through the dielectric layer. The resistive memory device of claim 5, further comprising a metal layer disposed on the dielectric layer and facing the top The electrode and the conductor layer in the second opening are electrically connected. The resistive memory element of claim 1, wherein the bottom electrode is disposed on a bottom surface and an entire sidewall of the upper opening. The resistive memory device of claim 8, wherein the thickness of the bottom electrode on the sidewall of the upper opening is substantially equal to the thickness of the bottom electrode on the bottom surface of the upper opening. The resistive memory element of claim 9, wherein the variable resistance layer is further disposed on the dielectric layer around the first opening. The resistive memory device of claim 10, wherein the dielectric layer further has a second opening, the conductor layer filling the second opening. The resistive memory device of claim 10, wherein the first opening and the second opening extend through the dielectric layer. The resistive memory element of claim 11, wherein the variable resistance layer exposes the conductor layer in the second opening. The resistive memory device of claim 11, further comprising a metal layer disposed on the dielectric layer and the conductor layer in the top electrode and the second opening Electrical connection. The resistive memory device of claim 1, wherein the conductor layer is electrically connected to another conductor layer under the dielectric layer. The resistive memory element of claim 15, wherein the another conductor layer comprises a doped region, a polysilicon layer or a metal layer.