TWI499008B - Resistive random access memory device and fabrications thereof - Google Patents

Description

Resistive non-volatile memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a resistive non-volatile memory device and a method of fabricating the same.

In recent years, consumer electronics such as mobile phones, digital cameras and MP3 players have become popular, making the demand for non-volatile memory increasing. Currently, non-volatile memory on the market still uses flash memory as the mainstream, but it has disadvantages such as large operating voltage, slow operation speed, and poor data storage, which limits the future development of flash memory.

A number of new non-volatile memory materials and devices are currently being actively developed, including magnetic memory (MRAM), phase change memory (OUM), and resistive memory (RRAM). The resistive non-volatile memory has low power consumption, low operating voltage, short write erasing time, long durability, long memory time, non-destructive reading, multi-state memory, simple device process and scalability. advantage.

According to the above, the industry needs a resistive non-volatile memory device and related manufacturing methods to solve process-related problems for better reliability.

The invention provides a method for fabricating a resistive non-volatile memory device, comprising: providing a substrate, wherein the substrate comprises a lower electrode layer, a resistance conversion layer, an upper electrode layer and a first mask; The electric layer is above the substrate; a second mask is formed on the interlayer dielectric layer; and the interlayer dielectric layer is etched by using the second mask as an etching mask to form an opening exposing the first mask; forming a gap The wall layer is on the bottom and the side walls of the opening; a portion of the spacer layer on the bottom of the opening is removed; an isotropic etching is performed to remove the first mask in the opening.

The present invention provides a resistive non-volatile memory device comprising: a substrate; a lower electrode layer, a resistance conversion layer and an upper electrode layer on the substrate; a first mask on the upper electrode layer; a dielectric layer on the first mask and the substrate; an opening extending through the interlayer dielectric layer and the first mask to expose the upper electrode layer; a spacer wall located in the opening and partially opening above the first mask a sidewall; and a conductive plug located in the opening.

102‧‧‧Base

104‧‧‧ lower electrode layer

106‧‧‧resistive conversion layer

108‧‧‧Upper electrode layer

110‧‧‧First curtain

112‧‧‧Barrier layer

114‧‧‧Interlayer dielectric layer

116‧‧‧Second curtain

118‧‧‧ openings

120‧‧‧ lining

122‧‧‧conductive plug

302‧‧‧Base

304‧‧‧ lower electrode layer

306‧‧‧resistive conversion layer

308‧‧‧Upper electrode layer

310‧‧‧First curtain

312‧‧‧Barrier layer

314‧‧‧Interlayer dielectric layer

316‧‧‧second curtain

318‧‧‧ openings

318’‧‧‧ openings

319‧‧‧ clearance layer

319’‧‧‧

320‧‧‧ lining

322‧‧‧conductive plug

1A to 1D are cross-sectional views showing an intermediate stage of fabrication of a resistive non-volatile memory.

Fig. 2 is a graph showing current and voltage curves of the first A to 1D resistive non-volatile memory.

3A to 3D are cross-sectional views showing an intermediate stage of fabrication of a resistive non-volatile memory device.

Figure 4 shows the 1A~1D resistive non-volatile memory device and Fig. 3A~3D diagram showing the relationship between the cumulative distribution function and the leakage current of the resistive non-volatile memory device.

Figure 5 is a cross-sectional view showing the intermediate stage of fabrication of a resistive non-volatile memory device.

6A to 6G are cross-sectional views showing an intermediate stage of fabrication of a resistive non-volatile memory device in accordance with an embodiment of the present invention.

Embodiments embodying the invention are discussed in detail below. It will be appreciated that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of variations. The specific embodiments discussed are merely illustrative of specific ways to use the embodiments and are not intended to limit the scope of the invention. In order to make the features of the present invention more comprehensible, the following detailed description of the embodiments and the accompanying drawings

Hereinafter, a method of fabricating a resistive non-volatile memory device will be disclosed based on FIGS. 1A to 1D. First, referring to FIG. 1A, a substrate 102 is provided, and a lower electrode layer 104, a resistance conversion layer 106 and an upper electrode layer 108 are sequentially formed on the substrate 102. Next, a first mask 110 is formed on the upper electrode layer 108. The first mask 110 is used as an etching mask, and an etching process is performed to pattern the lower electrode layer 104, the resistance conversion layer 106 and the upper electrode layer 108. Referring to FIG. 1B, a barrier layer 112 is formed conformally on the substrate 102 and the first mask 110 to form an interlayer dielectric layer 114 on the barrier layer 112. Referring to FIG. 1C, a second mask 116 is formed on the interlayer dielectric layer 114. Subsequently, the second mask 116 is used as an etching mask to perform a dry etching (non-isotropic etching) process to sequentially etch the interlayer dielectric layer. 114, the barrier layer 112 and the first mask 110 expose the opening 118 to the upper electrode layer 108. Next, referring to FIG. 1D, a liner 120 and a conductive plug 122 are formed in the opening 118 to provide an electrical connection between the upper electrode layer 108 and an external circuit.

Fig. 2 is a graph showing current and voltage curves of the first A to 1D resistive non-volatile memory. As shown in Figure 2, the resistive non-volatile memory exhibits a non-uniform current-voltage distribution. The possible cause is that the dry etching process damages the upper electrode layer, causing charge accumulation in the lower electrode layer, the resistance conversion layer, and The structure of the upper electrode layer causes a problem of device reliability.

Hereinafter, a method of fabricating a resistive non-volatile memory device will be described based on FIGS. 3A to 3D. First, referring to FIG. 3A, a substrate 302 is provided, and a lower electrode layer 304, a resistance conversion layer 306 and an upper electrode layer 308 are sequentially formed on the substrate 302. Next, a first mask 310 of yttrium oxide is formed on the upper electrode layer 308. The first mask 310 is used as an etching mask, and an etching process is performed to pattern the lower electrode layer 304, the resistance conversion layer 306, and the upper electrode layer 308. Referring to FIG. 3B, a barrier layer 312 is formed conformally on the substrate 302 and the first mask 310 to form an interlayer dielectric layer 314 on the barrier layer 312. Referring to FIG. 3C, a second mask 316 is formed on the interlayer dielectric layer 314. Subsequently, the second mask 316 is used as an etching mask to perform a dry etching (non-isotropic etching) process, and the interlayer dielectric layer 314 and the barrier layer 312 are sequentially etched to form an opening 318, and the dry etching is performed. The process stops at the first mask 310. Subsequently, as shown in FIG. 3D, a wet etching process such as soaking hydrofluoric acid is performed to expose the opening 318. Electrode layer. Since the above process removes the first mask 310 by a wet etching process, damage to the upper electrode layer 308 is small.

Fig. 4 is a graph showing the relationship between the cumulative non-volatile memory device of the first 1A to 1D and the cumulative distribution function (CDF) and leakage current of the 3A to 3D resistive non-volatile memory device. As shown in Figure 4, the resistive non-volatile memory devices of Figures 3A to 3D show a more consistent leakage current distribution than the resistive non-volatile memory devices of Figures 1A to 1D, with better reliability. .

However, referring to FIG. 5, since the method of fabricating the resistive non-volatile memory device of FIGS. 3A-3D employs an isotropic wet etching process for etching the first mask 310, it is difficult to control the outline of the opening 318'. And the size, which causes the lateral dimension of the opening 318' to be larger than expected, which is a problem that a short circuit is likely to occur particularly when the device is downsized.

In order to solve the above problems, the present invention provides a method for fabricating a non-volatile memory in which a spacer of a material different from the interlayer dielectric layer is formed in the opening, thereby controlling the lateral dimension of the opening to reduce the problem of short circuit.

Hereinafter, a method of fabricating a resistive non-volatile memory device according to an embodiment of the present invention will be described based on FIGS. 6A to 6G. First, referring to FIG. 6A, a substrate 302 is provided, and a lower electrode layer 304, a resistance conversion layer 306 and an upper electrode layer 308 are sequentially formed on the substrate 302.

Any desired semiconductor device, such as a transistor, resistor, logic device, etc., can be formed over substrate 302, although only a flat substrate 302 is shown herein for simplicity of the drawing. In the description of the present invention, The term "bottom" includes both formed devices on a semiconductor wafer and various coatings overlying the wafer; the term "substrate surface" includes the exposed uppermost layer of the semiconductor wafer, such as the surface of the wafer, and insulation. Layer, metal wire, etc. The substrate may be a germanium substrate on the insulating layer, germanium, gallium arsenide, gallium nitride, strain enthalpy, germanium, tantalum carbide, diamond, and/or other suitable materials.

The lower electrode layer 304 can be titanium, platinum, aluminum, alloys thereof, stacked layers thereof, or other suitable materials such as titanium nitride, tantalum nitride or molybdenum nitride. The lower electrode layer 304 may be formed by E-beam evaporation or sputtering. The resistance conversion layer 306 may be strontium zirconate (SrZrO3), cerium oxide or zirconia. The resistance conversion layer 306 can be formed by electron beam vacuum evaporation or sputtering. The upper electrode layer 308 can be titanium, platinum, aluminum, alloys thereof, stacked layers thereof, or other suitable materials such as titanium nitride, tantalum nitride or molybdenum nitride. The upper electrode layer 308 can be formed by electron beam vacuum evaporation or sputtering.

Thereafter, a first mask 310 such as hafnium oxide, hafnium oxynitride or tantalum nitride is formed on the upper electrode layer 308. The forming process of the first mask 310 may include: forming a ruthenium oxide layer (not shown) on the upper electrode layer 308, and subsequently forming a photoresist layer (not shown) on the ruthenium oxide layer, and the photoresist layer A lithography patterning process is performed to form a patterned photoresist layer, and the photoresist layer is patterned as a mask, and an etch process is performed on the ruthenium oxide layer to form a first mask 310. Next, an etching process is performed using the first mask 310 as an etching mask to pattern the lower electrode layer 304, the resistance conversion layer 306, and the upper electrode layer 308.

Referring to FIG. 6B, a barrier layer 312 is formed conformally on the substrate 302 and the first mask 310 to form an interlayer dielectric layer. 314 is on the barrier layer 312. In some embodiments, the barrier layer 312 includes tantalum nitride, and the interlayer dielectric layer 314 includes Tetraethoxy silane (TEOS) as a precursor to form cerium oxide. In some examples, barrier layer 312 has a thickness of between about 200 angstroms and about 400 angstroms, and interlayer dielectric layer 314 has a thickness of between about 3,000 angstroms and about 4,000 angstroms.

Referring to FIG. 6C, a second mask 316 is formed on the interlayer dielectric layer 314. The forming process of the second mask 316 may include: forming a tantalum nitride layer (not shown) on the interlayer dielectric layer 314, and subsequently forming a photoresist layer (not shown) on the tantalum nitride layer, The photoresist layer performs a patterning process of lithography to form a patterned photoresist layer, and the photoresist layer is patterned as a mask, and an etching process is performed on the tantalum nitride layer to form a second mask 316.

Subsequently, the second mask 316 is used as an etching mask to perform an anisotropic etching process, and the interlayer dielectric layer 314 and the barrier layer 312 are sequentially etched to form the opening 318, and the anisotropic etching process is stopped. At the first mask 310, the first mask 310 is not etched to avoid damage to the upper electrode layer 308.

Referring to FIG. 6D, a spacer layer 319 is formed on the second mask 316 and formed on the bottom and sidewalls of the opening 318. It should be noted that the material of the spacer layer 319 is different from the material of the first mask 310, and has a certain etching selectivity ratio therebetween, so that the spacer layer 319 can have a protective interlayer dielectric layer in the subsequent etching step. The effect of 314 avoids or reduces the lateral dimension of the opening 318. In some embodiments, the isotropic etching process of the subsequently removed portion of the first mask 310 uses an etchant, and the etching selectivity of the etchant to the spacer layer 319 and the first mask 310 is about 30 to about 100. In some embodiments, the spacer layer 319 includes titanium nitride, tantalum nitride, or polysilicon, and the spacer layer 319 can have a thickness between about 100 angstroms and about 200 angstroms. In an example, the spacer layer 319 is titanium nitride.

Referring to FIG. 6E, an anisotropic etching process is performed to remove a portion of the spacer layer 319 at the bottom of the opening 318 to form a spacer 319' on the sidewall of the opening 318. Referring to FIG. 6F, an isotropic etching process is performed to remove the first mask 310 in the opening 318. In some embodiments, the isotropic etch process includes hot phosphoric acid etching or hydrofluoric acid etching. In embodiments where the first mask 310 includes yttrium oxide, the isotropic etch process can be soaking hydrofluoric acid. It should be noted that since the interlayer dielectric layer 314 is protected by the spacer 319', the anisotropic etching process of this step does not cause lateral etching of the interlayer dielectric layer 314, so the opening 318 is at the barrier layer 312. The above portion does not cause an increase in the lateral dimension, and the problem of short circuit due to the expansion of the opening 318 can be reduced or avoided.

Referring to FIG. 6G, a liner 320 is further formed on the bottom and sidewalls of the opening 318, and a conductive layer is filled in the opening 318 to form a conductive plug 322. In some embodiments, the liner 320 comprises titanium nitride, tungsten nitride or tantalum nitride, and the liner 320 may have a thickness of from about 150 angstroms to about 200 angstroms. Conductive plug 322 can comprise tungsten, copper, aluminum, or other suitable electrically conductive material. The liner 320 and the conductive plug 322 can be formed by chemical vapor deposition.

Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection of the invention is defined by the scope of the appended patent application. quasi.

302‧‧‧Base

304‧‧‧ lower electrode layer

306‧‧‧resistive conversion layer

308‧‧‧Upper electrode layer

310‧‧‧First curtain

312‧‧‧Barrier layer

314‧‧‧Interlayer dielectric layer

316‧‧‧second curtain

318‧‧‧ openings

319’‧‧‧

Claims (13)

A method of fabricating a resistive non-volatile memory device, comprising: providing a substrate, wherein the substrate comprises a lower electrode layer, a resistance conversion layer, an upper electrode layer and a first mask; forming an interlayer dielectric layer Above the substrate; forming a second mask on the interlayer dielectric layer; using the second mask as an etching mask, etching the interlayer dielectric layer to form an opening, exposing the first mask; Forming a spacer layer on the bottom and sidewalls of the opening; removing a portion of the spacer layer on the bottom of the opening; and performing an isotropic etching process to remove the first mask in the opening. The method of fabricating a resistive non-volatile memory device according to claim 1, wherein the isotropic etching process uses an etchant, and the etchant applies the spacer layer to the first mask The etch selectivity ratio is between about 30 and about 100. The method of fabricating a resistive non-volatile memory device according to claim 1, wherein the spacer layer comprises titanium nitride, tantalum nitride, polycrystalline germanium or germanium oxide. The method of fabricating the resistive non-volatile memory device of claim 1, further comprising forming a liner on the bottom and sidewalls of the opening and forming a conductive plug in the opening. The method of fabricating a resistive non-volatile memory device according to claim 1, wherein the first mask comprises ruthenium oxide, ruthenium oxynitride or tantalum nitride. The method of fabricating a resistive non-volatile memory device according to claim 1, wherein the isotropic etching process comprises soaking hydrofluoric acid or hot phosphoric acid. The method of fabricating a resistive non-volatile memory device according to claim 1, wherein before forming the interlayer dielectric layer, forming a barrier layer on the substrate is further included. The method for fabricating a resistive non-volatile memory device according to claim 1, wherein the etching process for etching the interlayer dielectric layer is an anisotropic etching using the second mask as an etching mask The process, and the anisotropic etching process is stopped at the first mask. A resistive non-volatile memory device comprising: a substrate; a lower electrode layer, a resistance conversion layer and an upper electrode layer on the substrate; a first mask on the upper electrode layer; An electrical layer on the first mask and the substrate; an opening extending through the interlayer dielectric layer and the first mask to expose the upper electrode layer; a spacer wall located in the opening, and at the first a portion of the upper side of the opening above the mask; and a conductive plug located in the opening. The resistive non-volatile memory device of claim 9, wherein the spacer comprises titanium nitride, tantalum nitride, polysilicon or tantalum oxide. The resistive non-volatile memory device of claim 9, wherein the first mask comprises ruthenium oxide, ruthenium oxynitride or tantalum nitride. The resistive non-volatile memory device of claim 9, further comprising a liner between the spacer and the conductive plug. The resistive non-volatile memory device of claim 12, wherein the underlayer comprises titanium nitride, tungsten nitride or tantalum nitride, and the conductive plug comprises tungsten, copper or aluminum.