CN108074866B - Preparation method and structure of semiconductor transistor - Google Patents
Preparation method and structure of semiconductor transistor Download PDFInfo
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- CN108074866B CN108074866B CN201711226548.8A CN201711226548A CN108074866B CN 108074866 B CN108074866 B CN 108074866B CN 201711226548 A CN201711226548 A CN 201711226548A CN 108074866 B CN108074866 B CN 108074866B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000002360 preparation method Methods 0.000 title description 4
- 238000000034 method Methods 0.000 claims abstract description 64
- 238000007789 sealing Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 239000002243 precursor Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 27
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 239000010703 silicon Substances 0.000 claims description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 238000000231 atomic layer deposition Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 20
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910021529 ammonia Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 10
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 9
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000010926 purge Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- YSIFWANZVUDOGH-UHFFFAOYSA-N C(CC)N.[Si] Chemical compound C(CC)N.[Si] YSIFWANZVUDOGH-UHFFFAOYSA-N 0.000 claims description 3
- 230000035484 reaction time Effects 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 22
- 238000010586 diagram Methods 0.000 description 14
- 239000003566 sealing material Substances 0.000 description 14
- 239000011810 insulating material Substances 0.000 description 11
- 239000004020 conductor Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention teaches a method and structure for fabricating a semiconductor transistor, comprising, a semiconductor substrate; the grid structure is positioned on the upper surface of the semiconductor substrate and comprises a grid conducting layer and a grid insulating layer positioned on the grid conducting layer; a gate insulating sidewall located on the sidewall of the gate structure; the bolt conducting structures are positioned on two sides of the grid structure, and are electrically isolated through an air insulating structure or an insulating layer; the air side wall is positioned between the bolt conducting layer and the gate insulating side wall and comprises an air gap and an insulating sealing layer, and the air gap is sealed through the insulating sealing layer. Compared with the prior art, the introduction of the air gap and the air compartment not only reduces the parasitic capacitance between the grid electrode and the bolt conducting structure, but also reduces the parasitic capacitance between the bolt conducting structure and the bolt conducting structure, improves the stability and the reliability of the transistor, and provides an effective way for further reducing the size of the transistor.
Description
Technical Field
The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a manufacturing method and structure of a semiconductor transistor.
Background
Metal-Oxide-semiconductor field effect transistors (MOSFETs) are the most commonly used cells in integrated circuits. Since the MOSFET is in normal operation, the voltages at the gate, source and drain are not equal, there is a coupling of the electric field between them which is manifested as a capacitance between them. Along with the development of integrated circuits, miniaturization of devices is a necessary trend, but parasitic capacitance in the process is not reduced in proportion to the reduction of the size of the devices, and the capacitance is reduced in proportion to the reduction of the size of the devices, so that the proportion of the parasitic capacitance in the total capacitance is greatly increased, the stability and the reliability of the devices are seriously affected, and therefore, the research on the parasitic capacitance of the small-size devices is more significant.
As the technology of dynamic random access memory (DRAM, dynamic Random Access Memory) is scaled down to nano-scale, under the condition that the device is greatly scaled down, it is a great challenge to improve the parasitic capacitance between the gate electrode and the source electrode and the drain electrode, the gate electrode and the source electrode are equivalent to two plates of a parallel plate capacitor, in the parallel plate capacitor, the following relationship exists between the capacitance C, the dielectric coefficient k of the dielectric layer of the parallel plate capacitor, the plate area a, the plate distance d, the plate charge quantity Q, the charge-discharge current I, the charge-discharge power P, the charge-discharge energy W, the charge-discharge time t, and the inter-plate voltage V: for a specific device, under the condition that the polar plate voltage, the charge-discharge current, the polar plate area and the polar plate distance are unchanged, the resistance-capacitance delay t & gtC & gtk and the switching energy W & gtC & gtk can be deduced, and a spacer layer with low dielectric coefficient can be selected from the resistance-capacitance delay t & gtC & gtk and the switching energy W & gtC & gtk, so that parasitic capacitance between a grid electrode and a drain source electrode can be effectively reduced, and further capacitance-resistance delay and switching energy consumption can be reduced. Fig. 1 is a schematic structural diagram of a MOSFET according to the prior art, which includes a semiconductor substrate 11', a gate conductive layer 121', a gate insulating layer 122', a gate insulating sidewall 13', and a plug structure, wherein the gate insulating sidewall 13' is sequentially formed by a silicon nitride layer 131', a silicon oxide layer 132', and a silicon nitride layer 131', the plug structure is formed by repeatedly arranging a plug conductive structure 15' and a plug insulating structure 16' along the length direction of the gate insulating sidewall 13', the plug insulating structure 16' is an insulating layer 162', and the dielectric constant (k: 7.8) of the silicon nitride layer 131' and the dielectric constant (k: 3.9) of the silicon oxide layer 132' are relatively high, which is disadvantageous for reducing parasitic capacitance in the semiconductor transistor and affecting reliability and stability of the device.
Therefore, how to reduce the parasitic capacitance between the gate and the plug conductive structure, and the parasitic capacitance between the plug conductive structure and the plug conductive structure, and to improve the reliability of the semiconductor device, has become an important problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method and structure for manufacturing a semiconductor transistor, which are used to solve the problem of large parasitic capacitance between a gate and a plug conductive structure and between the plug conductive structure and the plug conductive structure in the prior art, and improve the stability and reliability of the device.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor transistor structure, which is characterized in that the method for manufacturing a semiconductor transistor structure at least comprises the following steps:
step S1, providing a semiconductor substrate, sequentially forming a gate conducting layer and a gate insulating layer on the semiconductor substrate, and forming a gate structure by etching;
s2, forming a gate insulation side wall and a sacrificial side wall on the side wall of the gate structure in sequence, wherein two adjacent sacrificial side walls enclose a first groove;
S3, forming a plug conducting layer in the first groove surrounded by the sacrificial side wall, and forming a plurality of plug conducting structures isolated by a plurality of second grooves through etching;
s4, forming a bolt insulating structure in the second groove between the bolt conducting structures;
step S5, removing the sacrificial side wall to form an air gap between the gate insulating side wall and the bolt conducting structure;
and S6, forming an insulating sealing layer in the air gap so as to seal the air gap into an air side wall.
Preferably, the method of forming the plug insulating structure between the plug conductive structures comprises:
in step S4, a plug insulating sidewall is formed on the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate, and the plug insulating sidewall surrounds an air compartment; and closing the air compartment into an air insulating structure while forming the insulating sealing layer at step S6.
Preferably, the method of forming the plug insulating structure between the plug conductive structures comprises:
in step S4, an insulating layer is filled in the second recess surrounded by the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate.
Preferably, the method for forming the insulating sealing layer comprises atomic layer deposition, and the atomic layer deposition is realized through a plurality of deposition process cycles, wherein the deposition process of a single cycle comprises that a first precursor is chemically adsorbed on the surface of the side wall of the air gap to form a monoatomic layer, the excessive first precursor is removed through inert gas purging, a second precursor reacts with the monoatomic layer to form an insulating sealing film layer, and the excessive second precursor and byproducts are removed through inert gas purging.
Preferably, the first precursor enters the reaction cavity in a pulse mode and is chemically adsorbed on the side wall surface of the air gap, and the opening ratio of the main valve at the rear end of the machine is between 60% and 100%.
Preferably, the first precursor enters the reaction chamber in a pulsed manner, and the time for the chemisorption reaction on the sidewall surface of the air gap is between 1 second and 3 seconds.
Preferably, the insulating sealing layer is formed by depositing silicon nitride by an atomic layer deposition method, the first precursor comprises silane dichloride, the second precursor comprises ammonia, the deposition time of a single cycle is between 20 seconds and 60 seconds, and the process temperature is between 400 and 700 degrees. Preferably, the insulating sealing layer is formed by depositing silicon dioxide by an atomic layer deposition method, the first precursor comprises monopropylamine silicon, the second precursor comprises oxygen, the deposition time of a single cycle is between 20 seconds and 60 seconds, and the process temperature is room temperature.
The present invention also provides a semiconductor transistor structure, which at least comprises:
a semiconductor substrate;
the grid structure is positioned on the upper surface of the semiconductor substrate and comprises a grid conducting layer and a grid insulating layer positioned on the grid conducting layer;
a gate insulating sidewall located on a sidewall of the gate structure;
the bolt conducting structures are positioned on two sides of the grid electrode structure, and adjacent bolt conducting structures are electrically isolated through bolt insulating structures; wherein a gap between the plug conductive structure and the gate structure is greater than a deposited thickness of the gate insulating sidewall to form an air gap between the gate insulating sidewall and the plug conductive structure; the method comprises the steps of,
the first insulating sealing layer is formed on the air gap to seal the air gap into an air side wall, and the air side wall can effectively reduce parasitic capacitance between the grid electrode and the bolt conductive structure and reduce resistance-capacitance delay due to small air dielectric constant, so that switching speed is increased, and switching energy is reduced.
Preferably, the first insulating sealing layer is partially filled into the air gap opening between the gate insulating side wall and the plug conductive structure, and the inward filling depth of the first insulating sealing layer is not more than the plane height horizontal to the top surface of the gate conductive layer.
Preferably, the first top surface of the first insulating sealing layer, the second top surface of the gate insulating sidewall, the third top surface of the plug conductive structure, and the fourth top surface of the gate insulating layer of the gate structure are formed on the same polishing plane to ensure that the semiconductor transistor structure also keeps the air sidewall hermetically sealed at a relatively low height.
Preferably, the plug insulating structure has a fifth top surface, and is also formed on the same polishing plane.
Preferably, the fifth top surface of the plug insulating structure comprises a solid surface of an insulating layer filling a second recess formed surrounded by adjacent the plug conductive structure and adjacent the air sidewall.
Preferably, the fifth top surface of the plug insulating structure comprises an annular surface of a plug insulating side wall and a surface of a second insulating sealing layer in the annular surface enclosure, wherein the plug insulating side wall is connected with an end edge of an adjacent plug conducting structure and is formed on the side wall of the plug conducting structure and the upper surface of the semiconductor substrate so as to form an air compartment in an enclosed manner; the second insulating sealing layer seals the air compartment into an air insulating structure, and the air insulating structure can effectively reduce parasitic capacitance between the grid electrode and the bolt conducting structure, reduce resistance capacitance delay, further increase switching speed and reduce switching energy due to small air dielectric constant.
Preferably, the second insulating sealing layer is partially filled into the air compartment opening surrounded by the plug insulating sidewall, the depth of the second insulating sealing layer filled in is not more than the plane height horizontal to the top surface of the gate conductive layer, and the material of the second insulating sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.
Preferably, the material of the gate insulating sidewall is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride, and the thickness of the gate insulating sidewall is between 2 nm and 15 nm; the material of the bolt conductive structure comprises polysilicon; the material of the first insulating sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.
Preferably, the height of the air gap is greater than the height of the gate conductive layer and less than the height of the gate structure; the width of the air gap is between 2 nanometers and 20 nanometers; the air gap contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 millitorr and a standard atmospheric pressure.
Preferably, the material of the insulating layer is one selected from the group consisting of silicon nitride, silicon dioxide and silicon oxynitride
Preferably, the material of the plug insulating sidewall is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride, and the thickness of the plug insulating sidewall is between 2 nm and 15 nm.
Preferably, the height of the air compartment is greater than the height of the gate conductive layer and less than the height of the gate structure; the width of the air compartment is between 2 nanometers and 20 nanometers; one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen are contained in the air compartment; the gas pressure within the air compartment is between 200 millitorr and a standard atmospheric pressure.
Preferably, the air insulating structure has a closed air compartment with a pencil-point structure therein.
Preferably, the air sidewall has a closed air gap with a pencil point structure therein.
As described above, the method and structure for manufacturing a semiconductor transistor of the present invention have the following beneficial effects:
1. compared with the silicon nitride-silicon oxide-silicon nitride symmetrical grid insulating side wall structure in the prior art, the silicon nitride-silicon oxide-silicon nitride symmetrical grid insulating side wall structure has the advantages that the air dielectric constant is small, so that parasitic capacitance between a grid electrode and a bolt conducting structure can be effectively reduced, resistance-capacitance delay is reduced, switching speed is further increased, and switching energy is reduced; and a silicon nitride layer is reduced, so that the effective utilization area of the semiconductor substrate can be increased.
2. Compared with the insulating layer in the prior art, the air insulating structure with the air compartments has the advantages that the parasitic capacitance between the grid electrode and the bolt conducting structure and between the bolt conducting structure and the bolt conducting structure can be effectively reduced due to the fact that the air dielectric constant is small, the resistance-capacitance delay is reduced, the switching speed is further increased, and the switching energy is reduced.
3. In the process of preparing the plug conductive structure, the polysilicon is deposited firstly and the plug conductive structure is formed, and then the plug insulating structure is formed among the plug conductive structures, so that the conduction among the plug conductive structures caused by the fact that the polysilicon is deposited into the defects of the plug insulating structure when the plug insulating structure is formed firstly and then the polysilicon is deposited can be avoided, and the stability and the reliability of the device are improved.
4. The invention adopts the air side wall and the air insulation structure to effectively reduce parasitic capacitance between the grid electrode and the bolt conductive structures and between the bolt conductive structures, and provides an effective way for further reducing the size of the semiconductor transistor and improving the integrated circuit integration level under the condition of ensuring the normal operation of the semiconductor transistor.
Drawings
Fig. 1 is a schematic diagram of a prior art semiconductor transistor structure.
Fig. 2 is a flow chart of a method for manufacturing a semiconductor transistor according to the present invention.
Fig. 3 is a schematic structural view showing the formation of a gate conductive material layer, a gate insulating material layer and a gate pattern layer on a semiconductor substrate according to the present invention.
Fig. 4 is a schematic diagram showing a structure of forming a gate conductive layer and a gate insulating layer on a semiconductor substrate according to the present invention.
Fig. 5 is a schematic structural diagram of a gate insulating sidewall material layer formed on a sidewall of a gate structure according to the present invention.
Fig. 6 is a schematic structural view showing the formation of a gate insulating sidewall on a gate structure sidewall according to the present invention.
Fig. 7 is a schematic diagram showing a structure of a sacrificial sidewall material layer formed on a gate insulating sidewall according to the present invention.
Fig. 8 is a schematic diagram showing the structure of the present invention for forming the sacrificial sidewall on the gate insulating sidewall.
Fig. 9 is a schematic diagram showing a structure of forming a plug conductive material layer at a exposed position of a semiconductor substrate according to the present invention.
Fig. 10 is a schematic view showing a structure of forming a conductive plug layer at a exposed position of a semiconductor substrate according to the present invention.
Fig. 11 is a schematic diagram showing a structure of forming a plug pattern layer on a plug conductive layer according to the present invention.
Fig. 12 is a schematic structural view showing a structure of forming a conductive plug structure on a conductive plug layer according to the present invention.
Fig. 13 is a schematic structural diagram showing a process of forming a plug insulating sidewall material layer on a sidewall of a plug conductive structure and an upper surface of a semiconductor substrate according to an embodiment of the invention.
Fig. 14 is a schematic view showing a structure of forming a plug insulating sidewall on a sidewall of a plug conductive structure and an upper surface of a semiconductor substrate according to an embodiment of the invention.
FIG. 15 is a schematic diagram showing an air gap formed at the location of the sacrificial sidewall in accordance with the first embodiment of the present invention.
Fig. 16 is a schematic view showing a structure of forming an insulating sealing material layer in an air gap and an air compartment according to an embodiment of the invention.
Fig. 17 is a schematic structural diagram of a semiconductor transistor according to a first embodiment of the present invention.
Fig. 18 is a schematic structural diagram illustrating formation of an insulating material layer between conductive structures in accordance with a second embodiment of the present invention.
Fig. 19 is a schematic view showing a structure of forming an insulating layer between the conductive structures of the second embodiment of the present invention.
FIG. 20 is a schematic diagram showing a structure of forming an air gap at the sacrificial sidewall position in a second embodiment of the present invention.
Fig. 21 is a schematic structural diagram illustrating a structure of forming an insulating sealing material layer in an air gap according to a second embodiment of the invention.
Fig. 22 is a schematic view showing the structure of a semiconductor transistor according to the second embodiment of the invention
Fig. 23 shows a schematic structural view of the present invention taken along the section X of the dashed line in fig. 3 and 18.
Fig. 24 is a schematic view showing the structure of the section along the broken line Y in fig. 3 according to the present invention.
Fig. 25 is a schematic structural view showing an atomic deposition apparatus for preparing an insulating seal according to the present invention.
FIG. 26 is a schematic illustration of the process of the atomic layer deposition process of the present invention for preparing an insulating seal.
FIG. 27 is a schematic view showing the coverage of an insulating seal by an atomic layer deposition method according to the present invention.
FIG. 28 is a schematic view showing the structure of an insulating seal prepared by atomic layer deposition according to the present invention.
Description of element reference numerals
11 11' semiconductor substrate
121 121' gate conductive layer
1210. Grid conductive material layer
122 122' gate insulation layer
1220. Gate insulating material layer
13 13' gate insulating sidewall
130. Gate insulating sidewall material layer
131' silicon nitride layer
132' silicon dioxide layer
14. Air sidewall
140. Sacrificial sidewall
1400. Sacrificial sidewall material layer
141. Air gap
15 15' pin conductive structure
150. Conductive layer of bolt
1500. Conductive material layer of bolt
151. First groove
16 16' bolt insulation structure
161. Second groove
162 162' insulating layer
1620. Insulating material layer
17. Air insulation structure
171. Air compartment
172. Bolt insulating side wall
1720. Bolt insulating sidewall material layer
18. Insulating sealing layer
180. Insulating sealing material layer
181. First insulating sealing layer
182. Second insulating sealing layer
191. Grid pattern layer
192. Bolt pattern layer
21. Substrate and method for manufacturing the same
22. Storage box
23. A first precursor
24. Reaction chamber
25. Nozzle
S1 to S6 steps
a-d steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to 28. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 2 to 17, in order to effectively reduce parasitic capacitance between the gate and the conductive structure of the plug, reduce resistance-capacitance delay, further increase switching speed, and reduce switching energy, the embodiment provides a method for manufacturing a semiconductor transistor structure, which at least includes the following steps:
step S1 is performed to provide a semiconductor substrate 11, and a gate conductive layer 121 and a gate insulating layer 122 are sequentially formed on the semiconductor substrate 11, and a gate structure is formed by etching.
Specifically, as shown in fig. 3, in the present embodiment, the semiconductor substrate 11 is a silicon substrate; oxidizing an oxide layer (not shown) on the silicon substrate, wherein the oxide layer is used as a dielectric layer of a grid structure and has a thickness of 1-10 nanometers; forming a gate conductive material layer 1210 and a gate insulating material layer 1220 on the surface of the semiconductor substrate 11 by physical vapor deposition or chemical vapor deposition, wherein the gate conductive material layer 1210 may be made of tungsten metal and has a thickness of 15 nm to 90 nm, and the gate insulating material layer 1220 may be made of silicon nitride and has a thickness of 50 nm to 300 nm; a gate pattern layer 191 is formed on the gate insulating material layer 1220 using an exposure developing technique.
Specifically, as shown in fig. 4, in the present embodiment, a gate structure is formed on the upper surface of the semiconductor substrate 11 by using an etching process, where the gate structure includes a gate conductive layer 121 and a gate insulating layer 122 located on the gate conductive layer 121, and the etching process includes, but is not limited to, dry etching or wet etching, and a specific etching process may be selected according to practical requirements and experimental conditions, which is not limited to the present embodiment.
Step S2 is performed, where a gate insulating sidewall 13 and a sacrificial sidewall 140 are sequentially formed on the sidewalls of the gate structure, and two adjacent sacrificial sidewalls 140 enclose a first groove 151.
Specifically, in this embodiment, first, as shown in fig. 5, a layer of gate insulating sidewall material layer 130 is formed on the upper surface of the structure obtained in step S1 by using a chemical vapor deposition method, and then, as shown in fig. 6, preferably, dry etching is used to remove the gate insulating sidewall material layer 130 on the semiconductor substrate 11 and the gate insulating layer 122, so as to form the gate insulating sidewall 13, where the gate insulating sidewall 13 may be made of silicon nitride and has a thickness of 2 nm to 15 nm;
it should be noted that, the process gas for forming the silicon nitride gate insulating sidewall 13 by chemical vapor deposition includes, but is not limited to, a mixed gas of monosilane and ammonia, a mixed gas of dichlorosilane and ammonia, or a mixed gas of tetrachlorosilane and ammonia, and specific mixed gas may be selected according to experimental conditions, and the process pressure includes 0.25 torr to 500 torr and the process temperature is between 600 degrees to 800 degrees; wherein the volume ratio of monosilane, dichlorosilane or tetrachlorosilane to ammonia in the mixed gas is between 1:3 and 1:10.
Specifically, in this embodiment, first, as shown in fig. 7, a sacrificial sidewall material layer 1400 is formed on the gate insulating sidewall 13 by using a chemical vapor deposition method, then, as shown in fig. 8, the sacrificial sidewall material layer 1400 on the semiconductor substrate 11 and the gate insulating layer 122 is removed by using dry etching, so as to form the sacrificial sidewall 140, where the sacrificial sidewall 140 may be made of silicon dioxide and has a thickness ranging from 2 nm to 15 nm.
It should be noted that the process gas for forming the silicon dioxide sacrificial sidewall 140 by vapor deposition includes, but is not limited to, a mixture of ethyl orthosilicate and nitrous oxide, a mixture of monosilane and nitrous oxide, a mixture of ethyl orthosilicate and oxygen, and a mixture of monosilane and oxygen, and specific mixtures may be selected according to experimental conditions, and the process pressure includes 400 mtorr to 1 atm and the process temperature is 200 to 800 degrees.
In step S3, a plug conductive layer 150 is formed in the first recess 151 surrounded by the sacrificial sidewall 140 and the semiconductor substrate 11, and the plug conductive structures 15 isolated by the second recesses 161 may be formed by an etching process.
Specifically, in this embodiment, as shown in fig. 9, first, in this embodiment, a layer of plug conductive material layer 1500 is deposited on the upper surface of the structure obtained in step S2 by using a chemical vapor deposition method, where the material of the plug conductive material layer 1500 may be polysilicon, and the thickness is between 100 nm and 500 nm; next, as shown in fig. 10, the excess of the plug conductive material layer 1500 is preferably removed by chemical polishing to form the plug conductive layer 150, which stops on the upper surface of the gate insulating layer 122; then, as shown in fig. 11, a plug pattern layer 192 is formed on the plug conductive layer 150 by using an exposure and development technique; finally, as shown in fig. 12, the plug conductive layer 150 is preferably etched using a dry etching technique to form the plug conductive structures 15 and the second grooves 161 between the plug conductive structures 15.
Step S4 is performed to form a plug insulating structure 16 in the second recess 161 between the plug conductive structures 15.
Specifically, in this embodiment, first, as shown in fig. 13, a plug insulating sidewall material layer 1720 is formed on the sacrificial sidewall 140, the sidewall of the plug conductive structure 15 and the upper surface of the semiconductor substrate 11, where the material of the plug insulating sidewall material layer 1720 may be silicon nitride, and the thickness is between 2 nm and 15 nm; the preparation method of the plug insulating sidewall material layer 1720 includes, but is not limited to, chemical vapor deposition and physical vapor deposition. Then, as shown in fig. 14, the excess plug insulating sidewall material 1720 is preferably removed by chemical polishing to form the plug insulating sidewall 172, which stops on the upper surface of the gate insulating layer 122; the plug insulating side wall 172 encloses an air compartment 171.
Step S5 is performed to remove the sacrificial sidewall 140 and form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15.
Specifically, as shown in fig. 15, in this embodiment, the sacrificial sidewall 140 is removed by using a wet etching technique, so as to form the air gap 141.
Step S6 is performed to form an insulating sealing layer 18 on the air gap 141 and the air compartment 171 to seal the air gap 141 and the air compartment 171 into the air sidewall 14 and the air insulating structure 17, wherein the insulating sealing layer 18 includes a first insulating sealing layer 181 located in the air gap 141 and a second insulating sealing layer 182 located in the air compartment 171.
Specifically, in this embodiment, first, as shown in fig. 16, a layer of insulating sealing material layer 180 is formed on the structure obtained in step S5, where the insulating sealing material layer 180 may be made of silicon nitride or silicon dioxide, and the method for forming the insulating sealing material layer 180 includes atomic layer deposition; finally, as shown in fig. 17, the excess insulating sealing material layer 180 is removed, preferably by chemical polishing, to form the insulating sealing layer 18.
It should be noted that, as shown in fig. 25 to 27, in this embodiment, the insulating sealing layer 18 may be formed by atomic layer deposition, where the atomic layer deposition includes a plurality of reaction cycles, and a single reaction cycle process includes:
a. the first precursor 23 stored in the storage tank 22 enters the reaction chamber 24 through the nozzle 25 in a pulse manner, is chemically adsorbed on the side wall of the air gap 141 and the side wall surface of the air compartment 171, gradually covers the whole deposition area surface, and finally forms a monoatomic layer;
b. purging with an inert gas to remove excess of the first precursor 23 from the reaction chamber 24, the monoatomic layer remaining unchanged during the process;
c. the second precursor stored in the storage box 22 enters the reaction cavity 24 through the nozzle 25 in a pulse mode, reacts with the monoatomic layer, gradually consumes the whole nitrogen atom layer, finally forms an insulating sealing film layer, and can apply a radio frequency power supply to ionize, so that the reaction time is shortened, and the deposition temperature is reduced;
d. excess second precursor and byproducts in the reaction chamber 24 are removed by purging with an inert gas, during which the insulating sealing film remains unchanged.
As shown in fig. 28a to 28c, a plurality of insulating sealing film layers are sequentially formed through a plurality of reaction cycles, so as to form the air compartment 171 with a nib-shaped structure. In this embodiment, as shown in fig. 28a, the reaction cycle is adopted to deposit an insulating sealing material layer 180 on the side wall (the plug insulating side wall 172) of the air compartment 171, parameters of atomic layer deposition are controlled, so that the insulating sealing material layer 180 is mainly deposited on one end of the side wall (the plug insulating side wall 172) of the air compartment 171 far away from the semiconductor substrate 11, the reaction cycle times are increased, the thickness of the insulating sealing material layer 180 is continuously increased, the interval between one end of the side wall (the plug insulating side wall 172) of the air compartment 171 far away from the semiconductor substrate 11 is gradually reduced, a structure as shown in fig. 28b is formed, the reaction cycle times are continuously increased, the insulating sealing material layer 180 completely seals one end of the side wall (the plug insulating side wall 172) of the air compartment 171 far away from the semiconductor substrate 11, and finally the air compartment 171 with a nib-shaped structure as shown in fig. 28c is formed; in the process of forming the air compartment 171 with the nib-like structure, the air gap 141 with the nib-like structure is also formed, and the process of forming the air gap 141 is substantially the same as the process of forming the air compartment 171, so that the description thereof will not be repeated.
Specifically, as shown in condition 1 of fig. 25, the parameters for controlling the atomic layer deposition include that the first precursor 23 enters the reaction chamber 24 in a pulse manner and is chemically adsorbed on the surface of the substrate 21, at this time, the opening ratio of the back-end main valve of the machine is between 60% and 100%, the greater the opening ratio of the back-end main valve, the more preferentially the first precursor 23 is chemically adsorbed on the side wall of the air gap 141 and the side wall of the air compartment 171 at the end far from the semiconductor substrate 11, and the less amount of the first precursor 23 is chemically adsorbed on the side wall of the air gap 141 and the end of the side wall of the air compartment 171 near the semiconductor substrate 11.
Specifically, as shown in condition 2 of fig. 25, in one embodiment of the present invention, the parameters for controlling the atomic layer deposition include that the first precursor 23 enters the reaction chamber 24 in a pulse manner, the time for the chemisorption reaction on the surface of the substrate 21 includes 1 to 3s, the chemisorption reaction time is reduced, since the first precursor 23 contacts the sidewall of the air gap 141 and the sidewall of the air compartment 171 away from the end of the semiconductor substrate 11, the first precursor 23 is preferentially chemisorbed in the reaction chamber 24 at the sidewall of the air gap 141 and the sidewall of the air compartment 171 away from the end of the semiconductor substrate 11, and the sidewall of the air gap 141 and the sidewall of the air compartment 171 are only chemisorbed with a small amount of the first precursor 23 near the end of the semiconductor substrate 11.
In this embodiment, silicon nitride is deposited by an atomic layer deposition method to form the insulating sealing layer 18, the first precursor 23 includes silane dichloride, the second precursor includes ammonia, and the deposition time of a single cycle is between 20 seconds and 60 seconds, and the process temperature is between 400 degrees and 700 degrees.
It should be noted that, in one embodiment of the present invention, silicon dioxide is deposited by an atomic layer deposition method to form the insulating sealing layer 18, the first precursor 23 includes monopropylamine silicon, the second precursor includes oxygen, and the deposition time of a single cycle is between 20 seconds and 60 seconds, and the process temperature is room temperature.
As shown in fig. 17, the present embodiment further provides a semiconductor transistor structure, which at least includes: a semiconductor substrate 11; a gate structure including a gate conductive layer 121 and a gate insulating layer 122 on the gate conductive layer 121, and disposed on an upper surface of the semiconductor substrate 11; a gate insulating sidewall 13 located on a sidewall of the gate structure; the bolt conducting structures 15 are positioned on two sides of the grid structure, and adjacent bolt conducting structures 15 are electrically isolated through an air insulating structure 17; wherein a gap between the plug conductive structure 15 and the gate structure is greater than a deposition thickness of the gate insulating sidewall 13 to form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15; and a first insulating sealing layer 181 formed in the air gap 141 to seal the air gap 141 into an air sidewall 14, wherein the air sidewall 14 can effectively reduce parasitic capacitance between the gate and the plug conductive structure 15 due to small air dielectric constant, reduce resistance-capacitance delay, further increase switching speed, and reduce switching energy.
Specifically, the semiconductor substrate 11 is located at the bottom layer of the semiconductor transistor structure, and the material of the semiconductor substrate 11 includes, but is not limited to, silicon. In this embodiment, an oxide layer (not shown) is formed on the upper surface of the semiconductor substrate 11.
Specifically, the material of the gate conductive layer 121 includes, but is not limited to, tungsten, and the thickness of the gate conductive layer 121 is between 15 nm and 90 nm. The material of the gate insulating layer 122 includes, but is not limited to, one of silicon nitride, silicon dioxide and silicon oxynitride, and the thickness of the gate insulating layer 122 is between 50 nm and 300 nm. The material of the gate insulating sidewall 13 includes, but is not limited to, one of silicon nitride, silicon dioxide and silicon oxynitride, but is not limited to the embodiment, and the thickness of the gate insulating sidewall 13 is between 2 nm and 15 nm; the material of the plug conductive structure 15 includes, but is not limited to, polysilicon.
Specifically, as shown in fig. 17, the first top surface of the first insulating sealing layer 181, the second top surface of the gate insulating sidewall 13, the third top surface of the plug conductive structure 15, the fourth top surface of the gate insulating layer 122 of the gate structure, and the fifth top surface of the plug insulating structure 16 are formed on the same polishing plane.
Specifically, as shown in fig. 17, the fifth top surface of the plug insulating structure 16 includes an annular surface of a plug insulating sidewall 172 and a top surface of a second insulating seal layer 182 enclosed in the annular surface, the plug insulating sidewall 172 connects adjacent to the end edge of the plug conductive structure 15 and is formed on the sidewall of the plug conductive structure 15 and the upper surface of the semiconductor substrate 11 to enclose and form an air compartment 171; the second insulating sealing layer 182 seals the air compartment 171 into the air insulating structure 17, and the air insulating structure 17 can effectively reduce parasitic capacitance between the gate and the conductive structure 15, reduce resistance-capacitance delay, further increase switching speed, and reduce switching energy due to small air dielectric constant.
Specifically, the material of the plug insulating sidewall 172 includes, but is not limited to, one of silicon nitride, silicon dioxide and silicon oxynitride, and the thickness of the plug insulating sidewall 172 is between 2 nm and 15 nm.
The materials of the first insulating sealing layer 181 and the second insulating sealing layer 182 include one of silicon nitride, silicon dioxide and silicon oxynitride, but are not limited to this embodiment; the materials of the first insulating sealing layer 181 and the second insulating sealing layer 182 include, but are not limited to, silicon nitride, silicon dioxide or silicon oxynitride, and the filling depth of the first insulating sealing layer 181 and the second insulating sealing layer 182 is between 2 nm and 15 nm.
Specifically, the height of the air gap is greater than the height of the gate conductive layer 121 and less than the height of the gate structure; the width of the air gap is between 2 nanometers and 20 nanometers; the air gap contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 millitorr and a standard atmospheric pressure.
Specifically, as shown in fig. 23, the first insulating sealing layer 181 partially fills the air gap opening between the gate insulating sidewall 13 and the plug conductive structure 15, the depth of the first insulating sealing layer 181 is not more than the plane height horizontal to the top surface of the gate conductive layer 121, the first insulating sealing layer 181 penetrates the inner cavity wall of the air sidewall 14, and the air sidewall 14 has a closed air gap with a pen-point structure; the height of the air gap 141 is greater than the height of the gate conductive layer 121 and less than the height of the gate structure, and in this embodiment, the width of the air gap 141 is between 2 nm and 20 nm; the air gap 141 contains one or more of dichlorosilane, ammonia gas, silane, tetrachlorosilane and nitrogen gas; the gas pressure in the air gap 141 is between 200 mtorr to a standard atmospheric pressure.
Specifically, as shown in fig. 24, the second insulating sealing layer 182 is partially filled into the opening of the air compartment 171 surrounded by the bolt insulating sidewall 172, the depth of the second insulating sealing layer 182 filled into the opening does not exceed the plane height horizontal to the top surface of the gate conductive layer 121, the second insulating sealing layer 182 penetrates the inner cavity wall of the air insulating structure 17, and the air insulating structure 17 has a closed air compartment 171 with a pen-shaped structure therein; the height of the air compartment 171 is greater than the height of the gate conductive layer 121 and less than the height of the gate structure; the width of the air compartment 171 is between 2 nm and 20 nm; the air compartment 171 contains one or more of dichlorosilane, ammonia gas, silane, tetrachlorosilane and nitrogen gas; the gas pressure in the air compartment 171 is between 200 millitorr and a standard atmospheric pressure.
Example two
As shown in fig. 2 to 13 and fig. 18 to 22, the present embodiment provides a method for manufacturing a semiconductor transistor structure, which at least includes the following steps:
step S1 is performed to provide a semiconductor substrate 11, and a gate conductive layer 121 and a gate insulating layer 122 are sequentially formed on the semiconductor substrate 11, and a gate structure is formed by etching.
Step S2 is performed, where a gate insulating sidewall 13 and a sacrificial sidewall 140 are sequentially formed on the sidewalls of the gate structure, and two adjacent sacrificial sidewalls 140 enclose a first groove 151.
Step S3 is performed, in which a plug conductive layer 150 is formed in the first groove 151 surrounded by the sacrificial sidewall 140, and a plurality of plug conductive structures 15 isolated by a plurality of second grooves 161 are formed by etching.
The specific implementation manner of the steps S1 to S3 is basically the same as that of the steps S1 to S3 in the first embodiment, and thus a detailed description thereof will be omitted herein.
Step S4 is performed to form an insulating layer 162 in the second groove 161 between the stud conductive structures 15, and the insulating layer 162 is used as the stud insulating structure 16.
Specifically, first, as shown in fig. 18, the second recess 161 surrounded by the sacrificial sidewall 140, the sidewall of the conductive plug 15 and the upper surface of the semiconductor substrate 11 is filled with an insulating material layer 1620, and the insulating material layer 1620 may be made of silicon nitride and has a thickness between 50 nm and 200 nm. The preparation method of the insulating material layer 1620 includes, but is not limited to, chemical vapor deposition and physical vapor deposition; then, as shown in fig. 19, the excess insulating material layer 1620 may be removed by chemical polishing to form the insulating layer 162, which stops on the upper surface of the gate insulating layer 122.
Step S5 is performed to remove the sacrificial sidewall 140 to form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15.
Specifically, as shown in fig. 20, the sacrificial sidewall 140 is preferably removed by a wet etching technique to form the air gap 141.
Step S6 is performed to form an insulating sealing layer 18 on the air gap 141 to seal the air gap into the air sidewall 14.
Specifically, first, as shown in fig. 21, an insulating sealing material layer 180 is formed on the structure obtained in step S5, where the insulating sealing material layer 180 may be made of silicon nitride or silicon dioxide. Finally, as shown in fig. 22, the excess insulating sealing material layer 180 may be removed by chemical polishing to form the insulating sealing layer 18, and the method for forming the insulating sealing layer 18 includes atomic layer deposition, and the insulating sealing layer 18 includes a first insulating sealing layer 181.
It should be noted that, as shown in fig. 25 to 27, in the present embodiment, the insulating sealing layer 18 may be formed by atomic layer deposition, and the atomic layer deposition method is substantially the same as that of the first embodiment, so that no description is given here.
As shown in fig. 22, this embodiment also provides a semiconductor transistor structure, which is substantially the same as the semiconductor structure in the first embodiment, except that the plug conductive structures 15 in the semiconductor transistor structure in this embodiment are electrically isolated by an insulating layer 162, and the insulating layer 162 is filled in a groove surrounded by the adjacent plug conductive structures and the adjacent air sidewall, so that the description is omitted herein.
In summary, the asymmetric structure of the silicon nitride-air sidewall is adopted to replace the silicon nitride-silicon oxide-silicon nitride symmetric gate insulating sidewall structure in the prior art, and the air insulating structure containing air compartments is adopted to replace the insulating layer in the prior art, so that parasitic capacitance between the gate and the bolt conducting structure and parasitic capacitance between the bolt conducting structure and the bolt conducting structure can be effectively reduced, resistance-capacitance delay is reduced, switching speed is further increased, and switching energy is reduced; in the process of preparing the plug structure, polysilicon is deposited firstly and the conductive structures are formed, and then the plug insulating structures are formed among the plug conductive structures, so that the conduction among the plug conductive structures caused by the fact that polysilicon is deposited into defects of the plug insulating structures when the plug insulating structures are formed firstly and then the polysilicon is deposited can be avoided, and the stability and the reliability of the device are improved; the invention adopts the air side wall and the air insulation structure to effectively reduce parasitic capacitance between the grid electrode and the bolt conductive structure and between the bolt conductive structure and the bolt conductive structure, and provides an effective way for further reducing the size of the semiconductor transistor and improving the integrated circuit integration under the condition of ensuring the normal operation of the semiconductor transistor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (22)
1. A method for fabricating a semiconductor transistor structure, the method comprising:
step S1, providing a semiconductor substrate, sequentially forming a gate conducting layer and a gate insulating layer on the semiconductor substrate, and forming a gate structure by etching;
s2, forming a gate insulation side wall and a sacrificial side wall on the side wall of the gate structure in sequence, wherein two adjacent sacrificial side walls enclose a first groove;
s3, forming a plug conducting layer in the first groove surrounded by the sacrificial side wall, and forming a plurality of plug conducting structures isolated by a plurality of second grooves through etching;
s4, forming a bolt insulating structure in the second groove between the bolt conducting structures;
Step S5, removing the sacrificial side wall to form an air gap between the gate insulating side wall and the bolt conducting structure;
and S6, forming an insulating sealing layer on the air gap so as to seal the air gap into an air side wall.
2. The method of manufacturing a semiconductor transistor structure of claim 1, wherein forming said plug insulating structure between said plug conductive structures comprises:
in step S4, a plug insulating sidewall is formed on the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate, and the plug insulating sidewall surrounds an air compartment; and closing the air compartment into an air insulating structure while forming the insulating sealing layer at step S6.
3. The method of manufacturing a semiconductor transistor structure according to claim 1, wherein forming the plug insulating structure between the plug conductive structures comprises:
in step S4, an insulating layer is filled in the second recess surrounded by the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate.
4. The method of manufacturing a semiconductor transistor structure according to claim 1, 2 or 3, wherein the method of forming the insulating sealing layer comprises atomic layer deposition, the atomic layer deposition being performed by a plurality of cycles of deposition processes, wherein a single cycle of deposition processes includes chemisorption of a first precursor on a sidewall surface of the air gap to form a monoatomic layer, removing the excess first precursor by an inert gas purge, and reacting a second precursor with the monoatomic layer to form an insulating sealing film, and removing the excess second precursor by an inert gas purge.
5. The method of claim 4, wherein the first precursor is pulsed into the reaction chamber and chemisorbed on the sidewall surface of the air gap, wherein the back end main valve opening ratio is between 60% and 100%.
6. The method of claim 4, wherein the first precursor is pulsed into the reaction chamber for a chemisorption reaction time of between 1 second and 3 seconds on the sidewall surface of the air gap.
7. The method of claim 4, wherein the insulating cap layer is formed by depositing silicon nitride using atomic layer deposition, the first precursor comprises silane dichloride, the second precursor comprises ammonia, the deposition time for a single cycle is between 20 seconds and 60 seconds, and the process temperature is between 400 degrees and 700 degrees.
8. The method of claim 4, wherein the insulating cap layer is formed by depositing silicon dioxide using atomic layer deposition, wherein the first precursor comprises monopropylamine silicon, wherein the second precursor comprises oxygen, wherein the deposition time for a single cycle is between 20 seconds and 60 seconds, and wherein the process temperature comprises 25 degrees.
9. A semiconductor transistor structure, the semiconductor transistor structure comprising at least:
a semiconductor substrate;
the grid structure is positioned on the upper surface of the semiconductor substrate and comprises a grid conducting layer and a grid insulating layer positioned on the grid conducting layer;
a gate insulating sidewall located on the sidewall of the gate structure, wherein the gate insulating sidewall is made of one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride;
the bolt conducting structures are positioned on two sides of the grid electrode structure, and adjacent bolt conducting structures are electrically isolated through bolt insulating structures; wherein a gap between the plug conductive structure and the gate structure is greater than a deposited thickness of the gate insulating sidewall to form an air gap between the gate insulating sidewall and the plug conductive structure; the method comprises the steps of,
and the first insulating sealing layer is formed on the air gap to seal the air gap into an air side wall.
10. The semiconductor transistor structure of claim 9, wherein said first insulating cap layer partially fills an air gap opening between said gate insulating sidewall and said plug conductive structure, said first insulating cap layer having an inward fill depth not exceeding a planar height level with a top surface of said gate conductive layer.
11. The semiconductor transistor structure of claim 10, wherein a first top surface of said first insulating cap layer, a second top surface of said gate insulating sidewall, a third top surface of said plug conductive structure, and a fourth top surface of said gate insulating layer of said gate structure are formed on a same polishing plane.
12. The semiconductor transistor structure of claim 11, wherein said plug insulating structure has a fifth top surface also formed in the same polishing plane.
13. The semiconductor transistor structure of claim 12, wherein a fifth top surface of said plug insulating structure comprises a solid surface of an insulating layer filling a recess formed surrounded by adjacent said plug conductive structure and adjacent said air sidewall.
14. The semiconductor transistor structure of claim 13, wherein a material of said insulating layer is selected from the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.
15. The semiconductor transistor structure of claim 12, wherein a fifth top surface of said plug insulating structure comprises an annular surface of a plug insulating sidewall and a surface of a second insulating seal layer within the annular surface enclosure, said plug insulating sidewall connecting adjacent an end edge of said plug conductive structure and formed on a sidewall of said plug conductive structure and an upper surface of said semiconductor substrate to enclose a forming air compartment; the second insulating sealing layer seals the air compartment into an air insulating structure.
16. The semiconductor transistor structure of claim 15, wherein said second insulating cap layer partially fills said air compartment opening surrounded by said plug insulating sidewall, said second insulating cap layer having an inward fill depth not exceeding a planar height level with a top surface of said gate conductive layer, said second insulating cap layer being of a material selected from the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.
17. The semiconductor transistor structure of claim 15, wherein a material of said plug insulating sidewall is selected from the group consisting of silicon nitride, silicon dioxide and silicon oxynitride, and wherein a thickness of said plug insulating sidewall is between 2 nm and 15 nm.
18. The semiconductor transistor structure of claim 15, wherein a height of said air-spaced compartment is greater than a height of said gate conductive layer and less than a height of said gate structure; the width of the air compartment is between 2 nanometers and 20 nanometers; one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen are contained in the air compartment; the gas pressure within the air compartment is between 200 millitorr and a standard atmospheric pressure.
19. The semiconductor transistor structure of claim 15, wherein said air-insulating structure has enclosed air-compartments therein having a pencil-like structure.
20. The semiconductor transistor structure of claim 9, wherein a thickness of said gate insulating sidewall is between 2 nm and 15 nm; the material of the bolt conductive structure comprises polysilicon; the material of the first insulating sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.
21. The semiconductor transistor structure of claim 9, wherein a height of said air gap is greater than a height of said gate conductive layer and less than a height of said gate structure; the width of the air gap is between 2 nanometers and 20 nanometers; the air gap contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 millitorr and a standard atmospheric pressure.
22. The semiconductor transistor structure according to any one of claims 9 to 21, wherein said air sidewall has a closed air gap with a pencil-like structure therein.
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| CN207852645U (en) * | 2017-11-29 | 2018-09-11 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction |
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| US6090698A (en) * | 1999-07-23 | 2000-07-18 | United Microelectronics Corp | Fabrication method for an insulation structure having a low dielectric constant |
| CN102760687A (en) * | 2011-04-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device with air space and manufacture method thereof |
| CN104299911A (en) * | 2013-07-16 | 2015-01-21 | 格罗方德半导体公司 | Gate encapsulation achieved by single-step deposition |
| CN107195550A (en) * | 2017-06-30 | 2017-09-22 | 睿力集成电路有限公司 | A kind of semiconductor device structure and preparation method thereof |
| CN207852645U (en) * | 2017-11-29 | 2018-09-11 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction |
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