CN108074866B - Preparation method and structure of semiconductor transistor - Google Patents

Abstract

The invention teaches a preparation method and structure of a semiconductor transistor, which includes a semiconductor substrate; a gate structure located on the upper surface of the semiconductor substrate, including a gate conductive layer and a gate insulating layer located on the gate conductive layer; The insulating side wall is located on the side wall of the gate structure; the plug conductive structure is located on both sides of the gate structure, and each plug conductive structure is electrically isolated by an air insulation structure or insulation layer; the air side wall is located on the plug conductive layer and Between the gate insulating sidewalls, the air sidewalls include an air gap and an insulating sealing layer, and the air gap is sealed by the insulating sealing layer. Compared with the existing technology, the introduction of air gaps and air compartments not only reduces the parasitic capacitance between the gate and the plug conductive structure, but also reduces the parasitic capacitance between the plug conductive structure and the plug conductive structure, improving the performance of the transistor. Stability and reliability provide an effective way to further reduce the size of transistors.

Description

Preparation method and structure of semiconductor transistor

Technical field

The present invention relates to a manufacturing process of a semiconductor device, and in particular to a manufacturing method and structure of a semiconductor transistor.

Background technique

Metal-Oxide-SemiconductorField-Effect Transistor (MOSFET, Metal-Oxide-SemiconductorField-Effect Transistor) is the most commonly used unit in integrated circuits. Since the voltages of the gate, source and drain of the MOSFET are not equal under normal operating conditions, there is a coupling effect in the electric field between them, and this coupling effect is manifested as the existence of capacitance between them. With the development of integrated circuits, device miniaturization is an inevitable trend. However, the parasitic capacitance in the process does not decrease proportionally with the decrease in device size, while the capacitance of this certificate decreases proportionally with the decrease in device size. , so that the proportion of parasitic capacitance in the total capacitance is greatly increased, which seriously affects the stability and reliability of the device. Therefore, the study of parasitic capacitance of small-sized devices is more meaningful.

As the process of Dynamic Random Access Memory (DRAM) shrinks to the nanometer scale, it is a major challenge to improve the parasitic capacitance between the gate and source and drain electrodes under the condition of significant shrinkage of components. The poles are equivalent to the two plates of a parallel plate capacitor. In the parallel plate capacitor, the capacitance C, the dielectric coefficient k of the dielectric layer of the parallel plate capacitor, the plate area A, the plate spacing d, and the plate charge There is the following relationship between Q, charge and discharge current I, charge and discharge power P, charge and discharge energy W, charge and discharge time t, and inter-plate voltage V: C=kA/d, Q=It, C=Q/V, P =W/t=IV. For a specific device, we assume that the plate voltage, charge and discharge current, plate area and distance between plates remain unchanged. From this, we can derive the resistance-capacitance delay t∝C∝k , switching energy W∝C∝k, it can be seen that choosing a spacer layer with a low dielectric coefficient can effectively reduce the parasitic capacitance between the gate and the drain source, thereby reducing the capacitance-resistance delay and reducing switching energy consumption. Figure 1 is a schematic structural diagram of a prior art MOSFET, including a semiconductor substrate 11', a gate conductive layer 121', a gate insulating layer 122', a gate insulating sidewall 13', a plug structure, and the gate insulating sidewall 13' is composed of a silicon nitride layer 131', a silicon oxide layer 132' and a silicon nitride layer 131' in sequence. The plug structure consists of a plug conductive structure 15' and a plug insulating structure 16' along the gate insulating sidewall 13'. The plug insulation structure 16' is an insulating layer 162', the silicon nitride layer 131' has a dielectric constant (k: 7.8) and the silicon oxide layer 132' has a dielectric constant (k: 3.9) is higher, which will not be conducive to reducing the parasitic capacitance in the semiconductor transistor and affect the reliability and stability of the device.

Therefore, how to reduce the parasitic capacitance between the gate and the plug conductive structure, as well as the parasitic capacitance between the plug conductive structure and the plug conductive structure, and improve the reliability of the semiconductor device has become an important issue that needs to be solved by those skilled in the art.

Contents of the invention

In view of the above shortcomings of the prior art, the object of the present invention is to provide a preparation method and structure of a semiconductor transistor to solve the problem between the gate and the plug conductive structure in the prior art, as well as the plug conductive structure and the plug conductive structure. The problem of large parasitic capacitance between them improves device stability and reliability.

In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a semiconductor transistor structure, which is characterized in that the method for manufacturing a semiconductor transistor structure at least includes the following steps:

Step S1: Provide a semiconductor substrate, sequentially form a gate conductive layer and a gate insulating layer on the semiconductor substrate, and form a gate structure through etching;

Step S2: Form gate insulating sidewalls and sacrificial sidewalls in sequence on the sidewalls of the gate structure, and the two adjacent sacrificial sidewalls surround a first groove;

Step S3: Form a plug conductive layer in the first groove surrounded by the sacrificial sidewall, and form a plurality of plug conductive structures separated by a plurality of second grooves through etching;

Step S4: Form a plug insulating structure in the second groove between the plug conductive structures;

Step S5: Remove the sacrificial sidewall to form an air gap between the gate insulating sidewall and the plug conductive structure;

Step S6: Form an insulating sealing layer in the air gap to seal the air gap into an air side wall.

Preferably, the method of forming the plug insulating structure between the plug conductive structures includes:

In step S4, a plug insulating side wall is formed on the sacrificial side wall, the side wall of the plug conductive structure and the upper surface of the semiconductor substrate, and the plug insulating side wall surrounds an air compartment; and in step S6 forms the insulating sealing layer while sealing the air compartment into an air insulating structure.

Preferably, the method of forming the plug insulating structure between the plug conductive structures includes:

In step S4, an insulating layer is filled and formed in the second groove surrounded by the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate.

Preferably, the method of forming the insulating sealing layer includes atomic layer deposition, which is achieved through a cycle of multiple deposition processes, wherein a single cycle of deposition process includes chemical adsorption of the first precursor on the sidewall surface of the air gap. A single atomic layer is formed, and the excess of the first precursor is removed by inert gas purging. The second precursor reacts with the single atomic layer to form an insulating sealing film layer, and the excess of the second precursor is removed by inert gas purging. Precursors and by-products.

Preferably, the first precursor enters the reaction chamber in a pulse manner and is chemically adsorbed on the side wall surface of the air gap. At this time, the opening ratio of the main valve at the rear end of the machine is between 60% and 100%.

Preferably, the first precursor enters the reaction chamber in a pulse manner, and the chemical adsorption reaction time on the side wall surface of the air gap is between 1 second and 3 seconds.

Preferably, silicon nitride is deposited using atomic layer deposition to form the insulating sealing layer. The first precursor includes silane dichloride, the second precursor includes ammonia gas, and the deposition time of a single cycle is between 20 seconds and 60 seconds. time, the process temperature is between 400 degrees and 700 degrees. Preferably, silicon dioxide is deposited by atomic layer deposition to form the insulating sealing layer. The first precursor includes monopropylamine silicon, the second precursor includes oxygen, and the deposition time of a single cycle is between 20 seconds and 60 seconds. time, the process temperature is room temperature.

The present invention also provides a semiconductor transistor structure, which at least includes:

semiconductor substrate;

A gate structure, located on the upper surface of the semiconductor substrate, includes a gate conductive layer and a gate insulating layer located on the gate conductive layer;

Gate insulating sidewalls, located on the sidewalls of the gate structure;

Plug conductive structures are located on both sides of the gate structure, and adjacent plug conductive structures are electrically isolated by plug insulating structures; wherein the gap between the plug conductive structure and the gate structure is greater than The gate insulating sidewall is deposited to a thickness to form an air gap between the gate insulating sidewall and the plug conductive structure; and,

A first insulating sealing layer is formed on the air gap to seal the air gap into an air side wall. Since the dielectric constant of air is small, the air side wall can effectively reduce the interference between the gate and the plug conductive structure. Parasitic capacitance reduces resistance-capacitance delay, thereby increasing switching speed and reducing switching energy.

Preferably, the first insulating sealing layer is partially filled in the air gap opening between the gate insulating sidewall and the plug conductive structure, and the inward filling depth of the first insulating sealing layer does not exceed a level of The plane height of the top surface of the gate conductive layer.

Preferably, the first top surface of the first insulating sealing layer, the second top surface of the gate insulating sidewall, the third top surface of the plug conductive structure and the gate insulation of the gate structure The fourth top surface of the layer is formed on the same grinding plane to ensure that the semiconductor transistor structure remains airtightly sealed at a relatively low height.

Preferably, the plug insulation structure has a fifth top surface, also formed on the same grinding plane.

Preferably, the fifth top surface of said plug insulating structure includes a solid surface of an insulating layer filled in a second groove surrounded by adjacent said plug conductive structure and adjacent said air sidewall .

Preferably, the fifth top surface of the plug insulating structure includes an annular surface of the plug insulating sidewall and a surface of the second insulating sealing layer surrounded by the annular surface, and the plug insulating side wall connects the adjacent plugs. The end edge of the conductive structure is formed on the side wall of the plug conductive structure and the upper surface of the semiconductor substrate to surround and form an air compartment; the second insulating sealing layer seals the air compartment into air insulation. structure, due to the small dielectric constant of air, the air insulation structure can effectively reduce the parasitic capacitance between the gate and the plug conductive structure, reduce the resistance-capacitance delay, thereby increasing the switching speed and reducing the switching energy.

Preferably, the second insulating sealing layer is partially filled into the air compartment opening formed by the insulating side wall of the plug, and the inward filling depth of the second insulating sealing layer is no more than horizontal to the gate conductive layer. The plane height of the top surface, the material of the second insulating sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

Preferably, the material of the gate insulating sidewall is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride, and the thickness of the gate insulating sidewall is between 2 nanometers and 15 nanometers. The material of the plug conductive structure includes polysilicon; the material of the first insulating sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.

Preferably, the height of the air gap is greater than the height of the gate conductive layer and less than the height of the gate structure; the width of the air gap is between 2 nanometers and 20 nanometers; It contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 mTorr and one standard atmospheric pressure.

Preferably, the material of the insulating layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride.

Preferably, the material of the plug insulating sidewall is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride, and the thickness of the plug insulating sidewall is between 2 nanometers and 15 nanometers. between.

Preferably, the height of the air compartment is greater than the height of the gate conductive layer and less than the height of the gate structure; the width of the air compartment is between 2 nanometers and 20 nanometers; the air The compartment contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air compartment is between 200 mTorr and one standard atmospheric pressure.

Preferably, the air insulating structure has an enclosed air compartment with a pen tip-like structure.

Preferably, the air side wall has a closed air gap with a pen tip-like structure.

As mentioned above, the preparation method and structure of a semiconductor transistor of the present invention have the following beneficial effects:

1. The present invention adopts an asymmetric structure of silicon nitride-air sidewall. Compared with the silicon nitride-silicon oxide-silicon nitride symmetric gate insulating sidewall structure in the prior art, due to the small dielectric constant of air, it can effectively Reduce the parasitic capacitance between the gate and the plug conductive structure, reduce the resistance and capacitance delay, thereby increasing the switching speed and reducing the switching energy; and reducing a layer of silicon nitride layer, which can increase the effective utilization area of the semiconductor substrate.

2. The present invention adopts an air insulation structure containing air compartments. Compared with the insulating layer in the prior art, due to the small dielectric constant of air, it can effectively reduce the distance between the gate and the plug conductive structure, as well as the plug conductive structure and the plug conductive structure. The parasitic capacitance between structures reduces the resistance-capacitance delay, thereby increasing the switching speed and reducing the switching energy.

3. In the process of preparing the plug conductive structure in the present invention, polysilicon is first deposited to form the plug conductive structure, and then the plug insulating structure is formed between the plug conductive structures. This can avoid the polysilicon being deposited to Defects in the bolt insulation structure cause conduction between the bolt conductive structures, thereby improving the stability and reliability of the device.

4. The present invention uses air side walls and air insulation structures to effectively reduce the parasitic capacitance between the gate and the plug conductive structures and between the plug conductive structures, and provides a further method while ensuring the normal operation of the semiconductor transistor. An effective way to reduce the size of semiconductor transistors and improve the integration level of integrated circuits.

Description of the drawings

FIG. 1 shows a schematic diagram of a semiconductor transistor structure in the related art.

FIG. 2 shows a schematic flow chart of a method for manufacturing a semiconductor transistor of the present invention.

FIG. 3 shows a schematic structural diagram of forming a gate conductive material layer, a gate insulating material layer and a gate pattern layer on a semiconductor substrate according to the present invention.

FIG. 4 shows a schematic structural diagram of forming a gate conductive layer and a gate insulating layer on a semiconductor substrate according to the present invention.

FIG. 5 shows a schematic structural diagram of forming a gate insulating sidewall material layer on the sidewall of the gate structure according to the present invention.

FIG. 6 shows a schematic structural diagram of forming gate insulating sidewalls on the sidewalls of the gate structure according to the present invention.

FIG. 7 shows a schematic structural diagram of forming a sacrificial sidewall material layer on the gate insulating sidewall according to the present invention.

FIG. 8 shows a schematic structural diagram of forming sacrificial sidewalls on gate insulating sidewalls according to the present invention.

FIG. 9 shows a schematic structural diagram of forming a plug conductive material layer at an exposed position of a semiconductor substrate according to the present invention.

FIG. 10 shows a schematic structural diagram of forming a plug conductive layer at an exposed position of a semiconductor substrate according to the present invention.

FIG. 11 shows a schematic structural diagram of forming a plug pattern layer on a plug conductive layer according to the present invention.

FIG. 12 shows a schematic structural diagram of forming a plug conductive structure on a plug conductive layer according to the present invention.

FIG. 13 is a schematic structural diagram of forming a plug insulating sidewall material layer on the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate in Embodiment 1 of the present invention.

FIG. 14 is a schematic structural diagram of forming plug insulating sidewalls on the sidewalls of the plug conductive structure and the upper surface of the semiconductor substrate in Embodiment 1 of the present invention.

FIG. 15 shows a schematic structural diagram of forming an air gap at the position of the sacrificial side wall in Embodiment 1 of the present invention.

Figure 16 shows a schematic structural diagram of forming an insulating sealing material layer in an air gap and an air compartment in Embodiment 1 of the present invention.

FIG. 17 is a schematic structural diagram of a semiconductor transistor in Embodiment 1 of the present invention.

FIG. 18 is a schematic structural diagram of forming an insulating material layer between plug conductive structures in Embodiment 2 of the present invention.

FIG. 19 shows a schematic structural diagram of forming an insulating layer between plug conductive structures in Embodiment 2 of the present invention.

FIG. 20 shows a schematic structural diagram of forming an air gap at the position of the sacrificial side wall in Embodiment 2 of the present invention.

FIG. 21 is a schematic structural diagram of forming an insulating sealing material layer in the air gap in Embodiment 2 of the present invention.

Figure 22 shows a schematic diagram of the structure of a semiconductor transistor in Embodiment 2 of the present invention.

Figure 23 is a schematic structural view of the section along the dotted line X in Figures 3 and 18 of the present invention.

Figure 24 is a schematic structural diagram of the section along the dotted line Y in Figure 3 of the present invention.

Figure 25 shows a schematic structural diagram of an atomic deposition device for preparing insulating seals according to the present invention.

Figure 26 shows a schematic diagram of the reaction procedure for preparing insulating sealing by the atomic layer deposition method of the present invention.

Figure 27 shows a schematic diagram of the coverage of insulating seal prepared by the atomic layer deposition method of the present invention.

Figure 28 shows a schematic structural diagram of an insulating seal prepared by the atomic layer deposition method of the present invention.

Component label description

11,11’ Semiconductor substrate

121, 121’ Gate conductive layer

1210 gate conductive material layer

122, 122’ gate insulation layer

1220 gate insulating material layer

13,13’ Gate Insulation Sidewall

130 Gate insulation sidewall material layer

131’ silicon nitride layer

132’ silicon dioxide layer

14 air sidewall

140 sacrificial sidewall

1400 sacrificial sidewall material layer

141 air gap

15, 15’ Tie conductive structure

150 bolt conductive layer

1500 bolt conductive material layer

151 first groove

16, 16’ bolt insulated construction

161 Second Groove

162, 162’ insulation

1620 layer of insulating material

17 Air Insulated Structure

171 Air Compartment

172 bolt insulated side walls

1720 bolt insulating sidewall material layer

18 Insulating sealing layer

180 layer of insulating sealing material

181 First insulating sealing layer

182 Second insulation sealing layer

191 gate pattern layer

192 bolt pattern layer

21 substrate

22 storage boxes

23 First Precursor

24 reaction chamber

25 nozzles

S1～S6 steps

a～d steps

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

See Figure 2 through Figure 28. It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. The drawings only show the components related to the present invention and do not follow the actual implementation of the component numbers, shapes and components. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

Embodiment 1

As shown in Figures 2 to 17, in order to effectively reduce the parasitic capacitance between the gate and the plug conductive structure, reduce the resistance and capacitance delay, thereby increase the switching speed and reduce the switching energy, this embodiment provides a method for preparing a semiconductor transistor structure , the preparation method of the semiconductor transistor structure at least includes the following steps:

Step S1 is performed to provide a semiconductor substrate 11. A gate conductive layer 121 and a gate insulating layer 122 are sequentially formed on the semiconductor substrate 11, and a gate structure is formed by etching.

Specifically, as shown in Figure 3, in this embodiment, the semiconductor substrate 11 is a silicon substrate; an oxide layer (not shown in the figure) is oxidized on the silicon substrate as a gate structure. The dielectric layer has a thickness between 1 nanometer and 10 nanometers; a layer of gate conductive material layer 1210 and a layer of gate insulating material are formed on the surface of the semiconductor substrate 11 using physical vapor deposition or chemical vapor deposition. Layer 1220, the gate conductive material layer 1210 can be made of metal tungsten, with a thickness between 15 nanometers and 90 nanometers, and the gate insulating material layer 1220 can be made of silicon nitride, with a thickness between 50 nanometers. to 300 nanometers; use exposure and development technology to form a gate pattern layer 191 on the gate insulating material layer 1220.

Specifically, as shown in FIG. 4 , in this embodiment, an etching process is used to form a gate structure on the upper surface of the semiconductor substrate 11 . The gate structure includes a gate conductive layer 121 and a gate electrode located on the gate. The gate insulating layer 122 on the extremely conductive layer 121. The etching process includes but is not limited to dry etching or wet etching. A specific etching process can be selected according to actual needs and experimental conditions. This embodiment is not used as a limit.

Step S2 is performed to sequentially form gate insulating sidewalls 13 and sacrificial sidewalls 140 on the sidewalls of the gate structure. The two adjacent sacrificial sidewalls 140 surround a first groove 151 .

Specifically, in this embodiment, first, as shown in FIG. 5 , a layer of gate insulating sidewall material layer 130 is formed on the upper surface of the structure obtained in step S1 by chemical vapor deposition, and then, as shown in FIG. 6 , Preferably, dry etching is used to remove the gate insulating sidewall material layer 130 on the semiconductor substrate 11 and the gate insulating layer 122 to form the gate insulating sidewall 13. The material of the side wall 13 can be silicon nitride, with a thickness ranging from 2 nanometers to 15 nanometers;

It should be noted that the process gas used to form the silicon nitride gate insulating sidewall 13 by the chemical vapor deposition method includes but is not limited to a mixed gas of monosilane and ammonia, a mixed gas of dichlorosilane and ammonia, or a mixed gas of tetrachlorosilane and tetrachlorosilane. The mixed gas of ammonia can be selected according to the experimental conditions. The specific mixed gas is not limited to this embodiment. The process pressure ranges from 0.25 Torr to 500 Torr, and the process temperature ranges from 600 degrees to 800 degrees; wherein, in the mixed gas The volume ratio of monosilane, dichlorosilane or tetrachlorosilane to ammonia gas is between 1:3 and 1:10.

Specifically, in this embodiment, first, as shown in FIG. 7 , a sacrificial sidewall material layer 1400 is formed on the gate insulating sidewall 13 by chemical vapor deposition, and then, as shown in FIG. 8 , Dry etching is used to remove the sacrificial sidewall material layer 1400 on the semiconductor substrate 11 and the gate insulating layer 122 to form the sacrificial sidewall 140. The material of the sacrificial sidewall 140 can be Silicon dioxide, with a thickness ranging from 2 nm to 15 nm.

It should be noted that the process gas used to form the silicon dioxide sacrificial sidewall 140 by the vapor deposition method includes but is not limited to a mixed gas of ethyl orthosilicate and nitrous oxide, a mixed gas of monosilane and nitrous oxide, The mixed gas of ethyl orthosilicate and oxygen, the mixed gas of monosilane and oxygen, the specific mixed gas can be selected according to the experimental conditions, and is not limited to this embodiment. The process pressure includes 400 mTorr to 1 standard atmosphere, and the process temperature Between 200 degrees and 800 degrees.

Step S3 is performed to form a plug conductive layer 150 in the first groove 151 surrounded by the sacrificial sidewall 140 and the semiconductor substrate 11 . An etching process may be used to form a plurality of plugs separated by a plurality of second grooves 161 . Conductive structure15.

Specifically, in this embodiment, as shown in Figure 9, first, in this embodiment, a chemical vapor deposition method is used to deposit a plug conductive material layer 1500 on the upper surface of the structure obtained in step S2. The plug conductive material The material of the layer 1500 can be polysilicon, with a thickness ranging from 100 nanometers to 500 nanometers; secondly, as shown in Figure 10, preferably, chemical grinding technology is used to remove the excess plug conductive material layer 1500 to form the entire conductive material layer 1500. For the plug conductive layer 150, this process stops on the upper surface of the gate insulating layer 122; then, as shown in FIG. 11, exposure and development technology is used to form the plug pattern layer 192 on the plug conductive layer 150; finally, As shown in FIG. 12 , preferably, dry etching technology is used to etch the plug conductive layer 150 to form the plug conductive structure 15 and the second recess located between the plug conductive structure 15 . slot 161.

Step S4 is performed to form a plug insulating structure 16 in the second groove 161 between the plug conductive structures 15 .

Specifically, in this embodiment, first, as shown in FIG. 13 , plug insulating sidewall material is formed on the sacrificial sidewall 140 , the sidewall of the plug conductive structure 15 and the upper surface of the semiconductor substrate 11 Layer 1720, the material of the plug insulating sidewall material layer 1720 can be silicon nitride, with a thickness ranging from 2 nanometers to 15 nanometers; the preparation method of the plug insulating sidewall material layer 1720 includes but is not limited to chemical vapor deposition and physical Vapor deposition is not limited to this embodiment. Then, as shown in FIG. 14 , chemical polishing technology is preferably used to remove the excess plug insulating sidewall material layer 1720 to form the plug insulating sidewall 172 . This process stops at the upper surface of the gate insulating layer 122 ; The plug insulating side wall 172 surrounds the air compartment 171.

Step S5 is performed to remove the sacrificial sidewall 140 and form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15 .

Specifically, as shown in FIG. 15 , in this embodiment, wet etching technology is used to remove the sacrificial sidewall 140 to form the air gap 141 .

Step S6 is performed to form an insulating sealing layer 18 on the air gap 141 and the air compartment 171 to seal the air gap 141 and the air compartment 171 into an air side wall 14 and an air insulation structure 17. The insulating sealing layer 18 includes a first insulating sealing layer 181 located in the air gap 141 and a second insulating sealing layer 182 located in the air compartment 171 .

Specifically, in this embodiment, first, as shown in Figure 16, an insulating sealing material layer 180 is formed on the structure obtained in step S5. The material of the insulating sealing material layer 180 can be silicon nitride or silicon dioxide. The method of forming the insulating sealing material layer 180 includes atomic layer deposition; finally, as shown in FIG. 17 , chemical grinding technology is preferably used to remove the excess insulating sealing material layer 180 to form the insulating sealing layer. 18.

It should be noted that, as shown in Figures 25 to 27, in this embodiment, atomic layer deposition can be used to form the insulating sealing layer 18. Atomic layer deposition includes multiple reaction cycles, where a single reaction cycle process includes:

a. The first precursor 23 stored in the storage box 22 enters the reaction chamber 24 through the nozzle 25 in a pulse manner, and is chemically adsorbed on the side walls of the air gap 141 and the side wall surface of the air compartment 171, and gradually Cover the entire surface of the deposition area, and finally form a single atomic layer;

b. Use inert gas to purge to remove excess first precursor 23 in the reaction chamber 24, during which the single atomic layer remains unchanged;

c. The second precursor stored in the storage box 22 enters the reaction chamber 24 through the nozzle 25 in a pulse manner, reacts with the single atomic layer, and gradually consumes the entire nitrogen atomic layer. , and finally form an insulating sealing film layer, the second precursor can be ionized by applying radio frequency power, shortening the reaction time and lowering the deposition temperature;

d. Use inert gas to purge to remove excess second precursor and by-products in the reaction chamber 24. During this process, the insulating sealing film layer remains unchanged.

As shown in Figures 28a to 28c, multiple layers of insulating sealing films are sequentially formed through multiple reaction cycles, thereby forming the air compartment 171 with a pen tip-like structure. In practical applications, the number of reaction cycles can be determined according to the materials and gaps. Parameters such as width can be set in detail, which is not limited to this embodiment. This embodiment is divided into three steps. As shown in Figure 28a, the reaction cycle is used to deposit an insulating sealing material layer 180 on the side wall (bolt insulating side wall 172) of the air compartment 171 to control the atomic layer. The deposition parameters are such that the insulating sealing material layer 180 is mainly deposited on the side wall of the air compartment 171 (the insulating side wall 172 ) away from the semiconductor substrate 11 , increasing the number of reaction cycles, and the insulating sealing The thickness of the material layer 180 continues to increase, and the distance between the side walls (bolt insulating side walls 172) of the air compartment 171 away from the semiconductor substrate 11 gradually becomes smaller, forming a structure as shown in Figure 28b, continuing By increasing the number of reaction cycles, the insulating sealing material layer 180 completely seals the end of the side wall (the plug insulating side wall 172 ) of the air compartment 171 away from the semiconductor substrate 11 , and finally forms the shape as shown in FIG. 28 c The air compartment 171 with a pen tip-like structure; in the process of forming the air compartment 171 with a pen tip-like structure, the air gap 141 with a pen tip-like structure is also formed at the same time. The formation of the air gap 141 The process is basically the same as the formation process of the air compartment 171, so it will not be described again here.

Specifically, as shown in Condition 1 in Figure 25, the parameters for controlling atomic layer deposition include the first precursor 23 entering the reaction chamber 24 in a pulse manner and chemically adsorbing on the surface of the substrate 21. At this time, The opening ratio of the main valve at the rear end of the stage is between 60% and 100%. The greater the opening ratio of the main valve at the rear end, the first precursor 23 in the reaction chamber 24 is preferentially chemically adsorbed on the side walls and sides of the air gap 141 The side wall of the air compartment 171 is away from the end of the semiconductor substrate 11 , while the side wall of the air gap 141 and the end of the side wall of the air compartment 171 close to the semiconductor substrate 11 are only chemically adsorbed. A small amount of said first precursor 23.

Specifically, as shown in Condition 2 in Figure 25, in one embodiment of the present invention, the parameters for controlling atomic layer deposition include the first precursor 23 entering the reaction chamber 24 in a pulsed manner, and the substrate 21 The surface chemical adsorption reaction time includes 1 to 3 s, which reduces the chemical adsorption reaction time because the first precursor 23 first contacts the side wall of the air gap 141 and the side wall of the air compartment 171 is away from the semiconductor liner. One end of the bottom 11, the first precursor 23 in the reaction chamber 24 is preferentially chemically adsorbed on the side wall of the air gap 141 and the end of the side wall of the air compartment 171 away from the semiconductor substrate 11, However, only a small amount of the first precursor 23 is chemically adsorbed on the side wall of the air gap 141 and the side wall of the air compartment 171 close to the semiconductor substrate 11 .

It should be noted that in this embodiment, silicon nitride is deposited using atomic layer deposition to form the insulating sealing layer 18. The first precursor 23 includes silane dichloride, and the second precursor includes ammonia gas, in a single cycle. The deposition time ranges from 20 seconds to 60 seconds, and the process temperature ranges from 400 degrees to 700 degrees.

It should be noted that in one embodiment of the present invention, silicon dioxide is deposited using atomic layer deposition to form the insulating sealing layer 18 , the first precursor 23 includes monopropylamine silicon, and the second precursor includes oxygen. , the deposition time of a single cycle ranges from 20 seconds to 60 seconds, and the process temperature is room temperature.

As shown in Figure 17, this embodiment also provides a semiconductor transistor structure. The semiconductor transistor structure at least includes: a semiconductor substrate 11; a gate structure located on the upper surface of the semiconductor substrate 11 and including a gate conductive layer. 121, and the gate insulating layer 122 located on the gate conductive layer 121; the gate insulating sidewalls 13, located on the sidewalls of the gate structure; the plug conductive structures 15, located on both sides of the gate structure, The adjacent plug conductive structures 15 are electrically isolated by air insulation structures 17; wherein the gap between the plug conductive structures 15 and the gate structure is greater than the deposition thickness of the gate insulating sidewall 13, To form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15; and, a first insulating sealing layer 181 is formed in the air gap 141 to seal the air gap 141. Due to the small dielectric constant of air, the air sidewall 14 can effectively reduce the parasitic capacitance between the gate and the plug conductive structure 15, reduce the resistance and capacitance delay, thereby increasing the switching speed and reducing the switching energy.

Specifically, the semiconductor substrate 11 is located at the bottom layer of the semiconductor transistor structure, and the material of the semiconductor substrate 11 includes but is not limited to silicon. In this embodiment, an oxide layer (not shown in the figure) is formed on the upper surface of the semiconductor substrate 11 .

Specifically, the material of the gate conductive layer 121 includes but is not limited to tungsten, and is not limited to this embodiment. The thickness of the gate conductive layer 121 is between 15 nanometers and 90 nanometers. The material of the gate insulating layer 122 includes but is not limited to one of silicon nitride, silicon dioxide, and silicon oxynitride. It is not limited to this embodiment. The thickness of the gate insulating layer 122 is between 50 nanometers. to 300nm. The material of the gate insulating sidewall 13 includes but is not limited to one of silicon nitride, silicon dioxide, and silicon oxynitride. It is not limited to this embodiment. The thickness of the gate insulating sidewall 13 is between 2 nanometers. to 15 nanometers; the material of the plug conductive structure 15 includes but is not limited to polysilicon, and is not limited to this embodiment.

Specifically, as shown in FIG. 17 , the first top surface of the first insulating sealing layer 181 , the second top surface of the gate insulating sidewall 13 , the third top surface of the plug conductive structure 15 , the The fourth top surface of the gate insulation layer 122 of the gate structure and the fifth top surface of the plug insulation structure 16 are formed on the same grinding plane.

Specifically, as shown in FIG. 17 , the fifth top surface of the plug insulating structure 16 includes the annular surface of the plug insulating sidewall 172 and the top surface of the second insulating sealing layer 182 surrounded by the annular surface. The plug insulating sidewall 172 connects the end edge of the adjacent plug conductive structure 15 and is formed on the side wall of the plug conductive structure 15 and the upper surface of the semiconductor substrate 11 to surround the air compartment 171; The second insulating sealing layer 182 seals the air compartment 171 into an air insulating structure 17. Due to the small dielectric constant of air, the air insulating structure 17 can effectively reduce the parasitic capacitance between the gate and the plug conductive structure 15, reducing The resistor and capacitor delay, thereby increasing the switching speed and reducing the switching energy.

Specifically, the material of the plug insulating sidewall 172 includes but is not limited to one of silicon nitride, silicon dioxide, and silicon oxynitride. It is not limited to this embodiment. The thickness of the plug insulating sidewall 172 is between Between 2nm and 15nm.

The materials of the first insulating sealing layer 181 and the second insulating sealing layer 182 include one of silicon nitride, silicon dioxide, and silicon oxynitride, and are not limited to this embodiment; the first insulating sealing layer The materials of 181 and the second insulating sealing layer 182 include but are not limited to silicon nitride, silicon dioxide or silicon oxynitride, and are not limited to this embodiment. The materials of the first insulating sealing layer 181 and the second insulating sealing layer 181 The filling depth of the sealing layer 182 is between 2 nanometers and 15 nanometers.

Specifically, the height of the air gap is greater than the height of the gate conductive layer 121 and less than the height of the gate structure; the width of the air gap is between 2 nanometers and 20 nanometers; the air gap It contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 millitorr and one standard atmospheric pressure.

Specifically, as shown in FIG. 23 , the first insulating sealing layer 181 is partially filled in the air gap opening between the gate insulating sidewall 13 and the plug conductive structure 15 . The first insulating sealing layer 181 The inward filling depth does not exceed the height of the plane horizontal to the top surface of the gate conductive layer 121. The first insulating sealing layer 181 penetrates the inner cavity wall of the air side wall 14. The inside of the air side wall 14 A closed air gap with a pen tip-like structure; the height of the air gap 141 is greater than the height of the gate conductive layer 121 and less than the height of the gate structure. In this embodiment, the width of the air gap 141 Between 2 nanometers and 20 nanometers; the air gap 141 contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap 141 is between Between 200 mTorr and one standard atmosphere.

Specifically, as shown in FIG. 24 , the second insulating sealing layer 182 is partially filled into the opening of the air compartment 171 formed by the plug insulating side wall 172 , and the inward filling depth of the second insulating sealing layer 182 is Not exceeding the height of the plane horizontal to the top surface of the gate conductive layer 121 , the second insulating sealing layer 182 penetrates the inner cavity wall of the air insulating structure 17 , and the air insulating structure 17 has a pen tip-like closed structure. Air compartment 171; the height of the air compartment 171 is greater than the height of the gate conductive layer 121 and less than the height of the gate structure; the width of the air compartment 171 is between 2 nanometers and 20 nanometers. space; the air compartment 171 contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air compartment 171 is between 200 mTorr and a standard between atmospheric pressures.

Embodiment 2

As shown in Figures 2 to 13 and Figures 18 to 22, this embodiment provides a method for preparing a semiconductor transistor structure. The method for preparing a semiconductor transistor structure at least includes the following steps:

Step S1 is performed to provide a semiconductor substrate 11. A gate conductive layer 121 and a gate insulating layer 122 are sequentially formed on the semiconductor substrate 11, and a gate structure is formed by etching.

Step S2 is performed to sequentially form gate insulating sidewalls 13 and sacrificial sidewalls 140 on the sidewalls of the gate structure. The two adjacent sacrificial sidewalls 140 surround a first groove 151 .

Step S3 is performed to form a plug conductive layer 150 in the first groove 151 surrounded by the sacrificial sidewall 140, and form a plurality of plug conductive structures 15 isolated by a plurality of second grooves 161 through etching.

The specific implementation methods of the above steps S1 to S3 are basically the same as those of the first embodiment, and therefore will not be described again here.

Step S4 is performed to form an insulating layer 162 in the second groove 161 between each of the plug conductive structures 15 . The insulating layer 162 serves as the plug insulating structure 16 .

Specifically, first, as shown in FIG. 18 , the second groove 161 surrounded by the sacrificial sidewall 140 , the sidewall of the plug conductive structure 15 and the upper surface of the semiconductor substrate 11 is filled with Insulating material layer 1620. The material of the insulating material layer 1620 can be silicon nitride, with a thickness ranging from 50 nanometers to 200 nanometers. The preparation method of the insulating material layer 1620 includes but is not limited to chemical vapor deposition and physical vapor deposition, and is not limited to this embodiment; then, as shown in FIG. 19 , the excess insulating material layer 1620 can be removed using chemical grinding technology. , forming the insulating layer 162, and this process stops at the upper surface of the gate insulating layer 122.

Step S5 is performed to remove the sacrificial sidewall 140 to form an air gap 141 between the gate insulating sidewall 13 and the plug conductive structure 15 .

Specifically, as shown in FIG. 20 , wet etching technology is preferably used to remove the sacrificial sidewall 140 to form the air gap 141 .

Step S6 is performed to form an insulating sealing layer 18 on the air gap 141 to seal the air gap into an air side wall 14 .

Specifically, first, as shown in FIG. 21 , an insulating sealing material layer 180 is formed on the structure obtained in step S5. The material of the insulating sealing material layer 180 can be silicon nitride or silicon dioxide. Finally, as shown in FIG. 22 , chemical grinding technology can be used to remove the excess insulating sealing material layer 180 to form the insulating sealing layer 18 . The method of forming the insulating sealing layer 18 includes atomic layer deposition. The insulating sealing layer 18 includes a first insulating sealing layer 181 .

It should be noted that, as shown in FIGS. 25 to 27 , in this embodiment, atomic layer deposition can be used to form the insulating sealing layer 18 . The atomic layer deposition method is basically the same as that in Embodiment 1, so it will not be described again here.

As shown in Figure 22, this embodiment also provides a semiconductor transistor structure. The semiconductor transistor structure of this embodiment is basically the same as the semiconductor structure in Embodiment 1. The difference is that each plug in the semiconductor transistor structure in this embodiment is conductive. The structures 15 are electrically isolated by an insulating layer 162 . The insulating layer 162 is filled and formed in a groove surrounded by the adjacent plug conductive structures and the adjacent air side walls, so no details are given here.

To sum up, the present invention uses an asymmetric structure of silicon nitride-air sidewalls to replace the silicon nitride-silicon oxide-silicon nitride symmetric gate insulating sidewall structure in the prior art, and adopts an air insulating structure containing air compartments. Instead of the insulating layer in the existing technology, due to the small dielectric constant of air, the parasitic capacitance between the gate and the plug conductive structure, as well as between the plug conductive structure and the plug conductive structure can be effectively reduced, reducing the resistance and capacitance delay, thereby increasing the switching speed. , reduce switching energy; in the process of preparing the plug structure, the present invention first deposits polysilicon and forms a conductive structure, and then forms a plug insulating structure between each plug conductive structure, which can avoid the polysilicon deposition caused by forming the plug insulating structure first and then depositing polysilicon. Defects in the plug insulation structure cause conduction between the plug conductive structures, improving the stability and reliability of the device; the invention uses air side walls and air insulation structures to effectively reduce the gap between the gate and the plug conductive structure, and The parasitic capacitance between the plug conductive structure and the plug conductive structure provides an effective way to further reduce the size of the semiconductor transistor and improve the integration level of the integrated circuit while ensuring the normal operation of the semiconductor transistor. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (22)

1. A method for preparing a semiconductor transistor structure, characterized in that the method for preparing a semiconductor transistor structure at least includes the following steps: Step S1: Provide a semiconductor substrate, sequentially form a gate conductive layer and a gate insulating layer on the semiconductor substrate, and form a gate structure through etching; Step S2: Form gate insulating sidewalls and sacrificial sidewalls in sequence on the sidewalls of the gate structure, and the two adjacent sacrificial sidewalls surround a first groove; Step S3: Form a plug conductive layer in the first groove surrounded by the sacrificial sidewall, and form a plurality of plug conductive structures separated by a plurality of second grooves through etching; Step S4: Form a plug insulating structure in the second groove between the plug conductive structures; Step S5: Remove the sacrificial sidewall to form an air gap between the gate insulating sidewall and the plug conductive structure; Step S6: Form an insulating sealing layer on the air gap to seal the air gap into an air side wall. 2. The method of manufacturing a semiconductor transistor structure according to claim 1, wherein the method of forming the plug insulating structure between the plug conductive structures includes: In step S4, a plug insulating side wall is formed on the sacrificial side wall, the side wall of the plug conductive structure and the upper surface of the semiconductor substrate, and the plug insulating side wall surrounds an air compartment; and in step S6 forms the insulating sealing layer while sealing the air compartment into an air insulating structure. 3. The method of manufacturing a semiconductor transistor structure according to claim 1, wherein the method of forming the plug insulating structure between the plug conductive structures includes: In step S4, an insulating layer is filled and formed in the second groove surrounded by the sacrificial sidewall, the sidewall of the plug conductive structure and the upper surface of the semiconductor substrate. 4. The method for preparing a semiconductor transistor structure according to claim 1, 2 or 3, wherein the method for forming the insulating sealing layer includes atomic layer deposition, which is achieved through a cycle of multiple deposition processes, wherein The deposition process of a single cycle includes the chemical adsorption of the first precursor on the side wall surface of the air gap to form a single atomic layer, purging with inert gas to remove excess of the first precursor, and the second precursor and the single atom layer. The layer reacts to form an insulating sealing film layer, and excess of the second precursor is removed by inert gas purging. 5. The method for preparing a semiconductor transistor structure according to claim 4, wherein the first precursor enters the reaction chamber in a pulsed manner and is chemically adsorbed on the side wall surface of the air gap. At this time, the machine The rear main valve opening ratio is between 60% and 100%. 6. The method for preparing a semiconductor transistor structure according to claim 4, wherein the first precursor enters the reaction chamber in a pulsed manner, and the chemical adsorption reaction time on the side wall surface of the air gap is between Between 1 second and 3 seconds. 7. The method for preparing a semiconductor transistor structure according to claim 4, wherein silicon nitride is deposited using atomic layer deposition to form the insulating sealing layer, the first precursor includes silane dichloride, and the second precursor Including ammonia, deposition times for a single cycle range from 20 to 60 seconds, and process temperatures range from 400 to 700 degrees. 8. The method for preparing a semiconductor transistor structure according to claim 4, wherein silicon dioxide is deposited by atomic layer deposition to form the insulating sealing layer, the first precursor includes monopropylamine silicon, and the second precursor The precursor includes oxygen, the deposition time for a single cycle ranges from 20 seconds to 60 seconds, and the process temperature includes 25 degrees. 9. A semiconductor transistor structure, characterized in that the semiconductor transistor structure at least includes: semiconductor substrate; A gate structure, located on the upper surface of the semiconductor substrate, includes a gate conductive layer and a gate insulating layer located on the gate conductive layer; Gate insulating sidewalls are located on the sidewalls of the gate structure, and the material of the gate insulating sidewalls is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride; Plug conductive structures are located on both sides of the gate structure, and adjacent plug conductive structures are electrically isolated by plug insulating structures; wherein the gap between the plug conductive structure and the gate structure is greater than The gate insulating sidewall is deposited to a thickness to form an air gap between the gate insulating sidewall and the plug conductive structure; and, A first insulating sealing layer is formed on the air gap to seal the air gap into an air side wall. 10. The semiconductor transistor structure of claim 9, wherein the first insulating sealing layer is partially filled in the air gap opening between the gate insulating sidewall and the plug conductive structure, and the first insulating sealing layer is The infill depth of an insulating sealing layer does not exceed the height of a plane horizontal to the top surface of the gate conductive layer. 11. The semiconductor transistor structure of claim 10, wherein the first top surface of the first insulating sealing layer, the second top surface of the gate insulating sidewall, and the third top surface of the plug conductive structure The top surface and the fourth top surface of the gate insulating layer of the gate structure are formed on the same grinding plane. 12. The semiconductor transistor structure of claim 11, wherein the plug insulation structure has a fifth top surface, which is also formed on the same grinding plane. 13. The semiconductor transistor structure of claim 12, wherein the fifth top surface of the plug insulating structure includes a solid surface of an insulating layer formed between adjacent plug conductive structures and adjacent the air side wall surrounded by a groove. 14. The semiconductor transistor structure of claim 13, wherein the material of the insulating layer is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride. 15. The semiconductor transistor structure of claim 12, wherein the fifth top surface of the plug insulation structure includes an annular surface of the plug insulation sidewall and a second insulating sealing layer surrounded by the annular surface. surface, the plug insulating sidewall connects the end edge of the adjacent plug conductive structure and is formed on the side wall of the plug conductive structure and the upper surface of the semiconductor substrate to surround and form an air compartment; the third Two insulating sealing layers seal the air compartment into an air insulating structure. 16. The semiconductor transistor structure of claim 15, wherein the second insulating sealing layer partially fills the air compartment opening formed by the plug insulating sidewalls, and the second insulating sealing layer is The filling depth does not exceed a plane height horizontal to the top surface of the gate conductive layer, and the material of the second insulating sealing layer is selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride. one. 17. The semiconductor transistor structure of claim 15, wherein the material of the insulating sidewall is selected from one of the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride. The thickness of the insulating sidewall of the plug is between 2 nanometers and 15 nanometers. 18. The semiconductor transistor structure of claim 15, wherein the height of the air compartment is greater than the height of the gate conductive layer and less than the height of the gate structure; The width is between 2 nanometers and 20 nanometers; the air compartment contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air compartment is between 200 Between millitorr and one standard atmosphere. 19. The semiconductor transistor structure of claim 15, wherein the air insulating structure has an enclosed air compartment with a pen tip-like structure. 20. The semiconductor transistor structure of claim 9, wherein a thickness of the gate insulating sidewall is between 2 nanometers and 15 nanometers; the material of the plug conductive structure includes polysilicon; and the first insulating The material of the sealing layer is selected from one of the group consisting of silicon nitride, silicon dioxide and silicon oxynitride. 21. The semiconductor transistor structure of claim 9, wherein the height of the air gap is greater than the height of the gate conductive layer and less than the height of the gate structure; the width of the air gap is between Between 2 nanometers and 20 nanometers; the air gap contains one or more of dichlorosilane, ammonia, silane, tetrachlorosilane and nitrogen; the gas pressure in the air gap is between 200 mTorr to one standard atmospheric pressure. 22. The semiconductor transistor structure according to any one of claims 9 to 21, wherein the air side wall has a closed air gap with a pen tip-like structure.