CN106847754B - Semiconductor storage unit and preparation method thereof - Google Patents
Semiconductor storage unit and preparation method thereof Download PDFInfo
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- CN106847754B CN106847754B CN201710134566.7A CN201710134566A CN106847754B CN 106847754 B CN106847754 B CN 106847754B CN 201710134566 A CN201710134566 A CN 201710134566A CN 106847754 B CN106847754 B CN 106847754B
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- bit line
- air bin
- hole
- insulating barrier
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Abstract
The present invention provides a kind of semiconductor storage unit and preparation method thereof, and the preparation method includes：Semi-conductive substrate is provided, it is formed with active area, groove isolation construction, the transistor wordline of channel form and the bit line of fin-shaped；Insulating barrier is formed in each bit line surface, contact hole is formed between each bit line and fills conductive material；Produce the first air bin in conductive material above each groove isolation construction, using depositing operation in first air bin fill insulant, control the depositing operation to form hole in the insulating materials；The second air bin is produced between each bit line and conductive material, fill insulant, the control long-pending technique form hole in the insulating materials in second air bin using depositing operation.The present invention can substantially improve signal delay Problem of Failure in dynamic RAM read-write program, and can extend the bit line design length limit, to be laid out more electric capacity in unit area.
Description
Technical field
The present invention can effectively reduce memory parasitic capacitance in ic manufacturing technology field more particularly to one kind
Semiconductor storage unit and preparation method thereof.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made up of the memory cell of many repetitions.Each memory cell generally includes capacitor 10 and crystal
Pipe 11；The grid of transistor 11 is connected with wordline 13, drain be connected with bit line 12, source electrode is connected with capacitor 10；In wordline 13
Voltage signal be capable of opening or closing for controlling transistor 11, and then the number being stored in capacitor 10 is read by bit line 12
It is believed that breath, or data message is written in capacitor 10 by bit line 12 and stored, as shown in Figure 1.
At present in dynamic RAM manufacturing process area, as size of electronic devices reduces, dynamic random storage
Signal delay failure (RC delay) suppresses also to become difficult in device read-write program.
Based on described above, there is provided one kind can effectively suppress signal delay in dynamic RAM read-write program and fail
Semiconductor storage unit and preparation method thereof be necessary.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of semiconductor storage unit and its
Preparation method, for solving in the prior art as size of electronic devices reduces, signal in dynamic RAM read-write program
Delay failure suppresses the problem of more difficult.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of semiconductor storage unit,
Including step：Semi-conductive substrate is provided, the trench isolations formed with active area, each active area of isolation in the Semiconductor substrate
The bit line of structure, wordline and fin-shaped；Insulating barrier is formed in each bit line surface, contact hole is formed between each bit line and is filled and is led
Electric material；The first air bin is produced in conductive material above each groove isolation construction, using depositing operation in described
The first insulating materials is filled in one air bin, while by controlling the depositing operation to form in first insulating materials
One hole；And the second air bin is produced between each bit line and conductive material, using depositing operation in second air
The second insulating materials is filled in storehouse, while the second hole is formed in second insulating materials by controlling the long-pending technique.
Preferably, the active area is had the shape of a strip into the Semiconductor substrate, and the wordline is the crystal of channel form
Pipe wordline, the transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two word transistors
Line, the bit line indention extension intersects with a plurality of transistor wordline, and every bit line passes through two transistors
Active area between wordline.
In another preferred scheme, the active area is had the shape of a strip into the Semiconductor substrate, and the wordline is ditch
The transistor wordline of channel-shaped, the transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two
Bar transistor wordline, the bit line is linearly with a plurality of transistor wordline square crossing, and every bit line passes through described two
Active area between bar transistor wordline.
Preferably, form insulating barrier in each bit line surface and contact hole is formed between each bit line and fill conductive material bag
Include：The first insulating barrier is formed in the bit line surface；The second insulating barrier is formed in Semiconductor substrate table；In second insulating barrier
Surface forms the 3rd insulating barrier, and the 3rd insulating barrier is not less than the top of bit line；Planarization is after the 3rd insulating barrier table
Face sequentially forms hard mask and graphic mask, the graphic mask is parallel with wordline and its quantity be wordline half；And base
It is etched down in graphic mask and exposes active area, forms contact hole；Form the conductive material for being filled in the contact hole.
Preferably, making the first air bin includes：Etch the insulating barrier that the conductive material makes it below each bit line surface；
Autoregistration air bin screen layer is covered on the conductive material and the 4th insulating barrier using chemical vapor deposition method, is located at
The thickness of autoregistration air bin screen layer in the middle part of contact hole is less than the thickness positioned at contact hole both sides；Using plasma etching institute
Autoregistration air bin screen layer is stated, the autoregistration air bin screen layer in the middle part of contact hole is entirely removed to form air bin window
Mouthful, and the autoregistration air bin screen layer positioned at contact hole both sides is partly retained；And based on the autoregistration air bin screen
Cover layer and etch the conductive material to groove isolation construction, form the first air bin.
Preferably, making the second air bin includes：The first insulating barrier is formed in the bit line surface；In Semiconductor substrate table
Form the second insulating barrier；The 3rd insulating barrier is formed in second surface of insulating layer；Contact hole is formed between each bit line and is filled out
Fill conductive material；And second insulating barrier and the 3rd insulating barrier are removed by wet corrosion technique and is formed positioned at bit line and led
The second air bin between electric material.
Preferably, the depth-to-width ratio of first air bin and the second air bin is 5~20.
Preferably, the width ratio of first hole and the first air bin is 1:2~3；Second hole and the second sky
The width ratio of gas storehouse is 1:2~3..
Preferably, fill insulant and hole is formed in the insulating materials in the first air bin and the second air bin
The technique in hole includes enhancing high-aspect-ratio technique (eHARP), high-density plasma deposition process (HDP), tetraethyl orthosilicate
Learn one kind in gas-phase deposition (TEOS CVD) and plasma reinforced chemical vapour deposition technique (PECVD).
The present invention also provides a kind of semiconductor storage unit, including：Semiconductor substrate, in the Semiconductor substrate formed with
Active area, the groove isolation construction of each active area of isolation, the bit line of wordline and fin-shaped；Insulating barrier, it is formed at each bit line surface；
Contact hole, it is formed between each bit line, conductive material is filled with the contact hole；First air bin, be formed at each groove every
From in the conductive material of superstructure, being filled with the first insulating materials, and first insulating materials in first air bin
In formed with the first hole；And second air bin, it is formed between each bit line and conductive material, is filled out in second air bin
Filled with the second insulating materials, and formed with the second hole in second insulating materials.
Preferably, the active area is had the shape of a strip into the Semiconductor substrate, and the wordline is the crystal of channel form
Pipe wordline, the transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two word transistors
Line, the bit line indention extension intersects with a plurality of transistor wordline, and every bit line passes through two transistors
Active area between wordline.
In another preferred scheme, the active area is had the shape of a strip into the Semiconductor substrate, and the wordline is ditch
The transistor wordline of channel-shaped, the transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two
Bar transistor wordline, the bit line is linearly with a plurality of transistor wordline square crossing, and every bit line passes through described two
Active area between bar transistor wordline.
Preferably, the transistor wordline of the channel form includes layer of dielectric material and electrode material layer, the dielectric material
The dielectric constant of layer is one kind in 1~8, including silica and silicon nitride, and thickness is 1~10 nanometer；The electrode material bag
One kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon is included, its resistivity is 2 × 10-8Ω m~1 ×
102Ωm。
Preferably, there is dielectric barrier layer between the transistor wordline and bit line, its dielectric material constant is 1.0~
10, thickness is 5~80 nanometers.
Preferably, the depth-to-width ratio of first air bin and the second air bin is 5~20.
Preferably, the width ratio of first hole and the first air bin is 1:2~3；Second hole and the second sky
The width ratio of gas storehouse is 1:2~3.
Preferably, first insulating materials and second insulating materials include the one of which of silica and silicon nitride
Or the mixed film of two kinds of compositions.
Preferably, first hole is less than 10 supports (Torr) with the gas pressure intensity in second hole.
Preferably, first hole is by the completely airtight cladding of first insulating materials.
Preferably, second hole is by the completely airtight cladding of second insulating materials.
As described above, semiconductor storage unit of the present invention and preparation method thereof, has the advantages that：
The present invention makes memory lines group contact hole using lithographic process, while utilizes automatic alignment and flatening process,
Gap between bit line makes air chamber structure, substantially improves signal delay in dynamic RAM read-write program and fails
Problem, and the bit line design length limit can be extended, to be laid out more electric capacity in unit area.In the present invention, bit line it
Between clearance air chamber structure can effectively reduce by more than 15% bit line parasitic capacitance.
Brief description of the drawings
Fig. 1 is shown as the cellular construction schematic diagram of dynamic RAM.
What each step of preparation method that Fig. 2~Figure 21 is shown as the semiconductor storage unit of the embodiment of the present invention 1 was presented
Structural representation.
What each step of preparation method that Figure 22~Figure 41 is shown as the semiconductor storage unit of the embodiment of the present invention 2 was presented
Structural representation.
Component label instructions
201st, 301 active area
202nd, 302 wordline
203rd, 303 bit line
204th, 304 groove isolation construction
205th, 305 Semiconductor substrate
306 enclosing regions
207th, 307 first separation layer
208th, 308 second separation layer
209th, 309 first insulating barrier
210th, 310 second insulating barrier
211st, 311 the 3rd insulating barrier
212nd, 312 hard mask
213rd, 313 graphic mask
214th, 314 the 4th insulating barrier
215th, 315 conductive material
216th, 316 autoregistration air bin screen layer
217th, 317 first air bin
218th, 318 first insulating materials
219th, 319 first hole
220th, 320 second air bin
221st, 321 second insulating materials
222nd, 322 second hole
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 2~Figure 41.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in illustrating then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment 1
As shown in Fig. 2~Figure 21, the present embodiment provides a kind of preparation method of semiconductor storage unit, including step：
As shown in Figures 2 and 3, step 1) is carried out first, there is provided semi-conductive substrate 205, in the Semiconductor substrate 205
Formed with memory array structure, including active area 201, the groove isolation construction 204 of each active area 201 of isolation, channel form
The bit line 203 of transistor wordline 202 and fin-shaped, specific first separation layer between the transistor wordline 202 and bit line 203
207, there is the second separation layer 208 on the bit line 203, wherein, second separation layer 208 act as isolating the bit line
203 and the conductive material 215 of subsequent touch window.
In the present embodiment, the active area 201 is had the shape of a strip into the Semiconductor substrate 205；The transistor
Wordline 202 is spaced intersects with the active area 201, and each active area 201 is correspondingly arranged two transistor wordline 202, right
Isolated between every two transistor wordline 202 of Ying Yuyi active areas 201 by groove isolation construction 204；The bit line 203 is in
Zigzag extension intersects with a plurality of transistor wordline 202, and every bit line 203 passes through two transistor wordline 202
Between active area 201, as shown in Figure 2 to 3, wherein, Fig. 3 is shown as sectional views of the Fig. 2 along A-A '.
Further, the Semiconductor substrate 205 is single crystal silicon material, and the active area 201 is with element doping
Single crystal silicon material, its resistivity are 5 × 10 Ω m~5 × 103Ω m, wherein, described Ω m represent ohm meter.
The groove isolation construction 204 includes shallow trench and the dielectric material being filled in the shallow trench, the dielectric
The K values of material are typically less than 3, and it act as isolating shallow trench electric leakage and mitigating being electrically coupled (coupling), the dielectric
Material can be silica material etc., the shallow groove depths be 800~1600 nanometers between with controlling transistor degree of isolation.
The transistor wordline 202 of the channel form includes layer of dielectric material and electrode material layer, the layer of dielectric material
Dielectric constant is one kind in 1~8, including silica and silicon nitride, and thickness is 1~10 nanometer；The electrode material include tungsten,
One kind in titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon, its resistivity are 2 × 10-8Ω m~1 × 102Ω
m。
First separation layer 207 act as isolating the transistor wordline 202 and bit line 203, and it can pass through low pressure
Be vapor-deposited (Low Presure Chemical Vapor Deposition) or plasma gas-phase deposit (Plasma
Enhancement Chemical Vapor Deposition) etc. technique formed, its dielectric material constant is preferably 1.0~10,
Such as silicon nitride (Silicon Nitride), between its thickness is 5~80 nanometers.
As shown in Fig. 4~Fig. 5, step 2) is then carried out, in the surface of 203 and second separation layer of bit line 208 and side wall
Form the first insulating barrier 209.
Specifically, the surface deposition of insulative material of Semiconductor substrate 205 is first equal to using such as chemical vapor deposition method, then
The insulating materials on the surface of the first separation layer 207 is removed using ion etch process, retains the bit line 203 and second and isolates
208 surface of layer and the insulating materials of side wall, form first insulating barrier 209.The resistivity of first insulating barrier 209 is 2
×1011Ω m~1 × 1025Ω m, the mixed film of one or two kinds of compositions of silica and silicon nitride can be included.
As shown in Fig. 6~Figure 11, step 3) is then carried out, formation is coated on the surface of the first insulating barrier 209 successively
Second insulating barrier 210 and the 3rd insulating barrier 211, while remove and be exposed to first separation layer 207 on the surface of Semiconductor substrate 205 and reveal
Go out active area 201, form contact hole.
Specifically, step 3) includes：
Step 3-1), form the second insulating barrier 210 in the table of Semiconductor substrate 205.Second insulating barrier 210 can pass through
Technique for atomic layer deposition (ALD) or the process such as low pressure gas phase deposition (LPCVD) or Spin on Dielectrics (SOD)
Complete, its dielectric material constant be 1.0~10, such as nitrogen oxide (Silicon Nitride), thickness be 5~200 nanometers it
Between, as shown in Figure 6.
Step 3-2), the 3rd insulating barrier 211 is formed in the surface of the second insulating barrier 210, the 3rd insulating barrier 211 is not
Less than the second separation layer 208 on bit line 203.3rd insulating barrier 211 can pass through technique for atomic layer deposition (ALD) or low
The process such as chemical vapor deposition (LPCVD) or Spin on Dielectrics (SOD) is completed, and its dielectric material constant is 1.0
~10, such as nitrogen oxide (Silicon Nitride), and second insulating barrier 210 and the 3rd is insulated by annealing process
Layer 211 is densified, as shown in Figure 7.
Step 3-3), planarized with cmp or ion(ic) etching, as shown in figure 8, planarization is after the described 3rd
Insulating barrier 211 sequentially forms hard mask 212 and graphic mask 213, and the graphic mask 213 includes multiple parallel with wordline 202
Screen layer, each screen layer is across two wordline 202 of corresponding same active area, and its width is slightly larger than two institutes of wordline 202
The width of leap, its total quantity of the screen layer are the half of wordline 202, as shown in FIG. 9 and 10, wherein, Figure 10 is shown
For Fig. 9 overlooking structure figure.
Step 3-4), hard mask 212, the 3rd insulating barrier 211, the second insulating barrier 210 and are etched based on graphic mask 213
One separation layer 207, expose active area 201, form contact hole, as shown in figure 11.
The etching can be divided into two steps, and first step goes to hard mask 212 to be etched to figure, and second step is still further below
The 3rd insulating barrier 211, the second insulating barrier 210 and the first separation layer 207 are etched to exposing active area 201, and figure is divested with ion
Processing procedure, which is cleaned, after the residuals of shape mask 213 and hard mask 212 and progress removes remained on surface (Residue) and particulate
(Micro particle)。
As shown in figure 12, step 4) is then carried out, forms the 4th insulating barrier 214 for being coated on the 3rd insulating barrier 211.
As shown in Figure 13~Figure 14, step 5) is then carried out, formation is filled in the contact hole and covered to the described 4th
Conductive material 215 on insulating barrier 214, return the quarter conductive material 215 and make it below the 4th insulating barrier 214.
The conductive material 215 includes one kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon
Or two or more combinations, its resistivity are 2 × 10-8Ω m~1 × 102Ωm。
As shown in Figure 14~Figure 15, step 6) is then carried out, formation is covered in the insulating barrier of conductive material 215 and the 4th
Autoregistration air bin screen layer 216 on 214, sky is formed using autoregistration air bin screen layer 216 described in plasma etching
Gas storehouse window, and further etch the conductive material 215 and form the first air bin 217.
In the present embodiment, step 6) includes：
Step 6-1), covered using chemical vapor deposition method on the insulating barrier 214 of conductive material 215 and the 4th
Autoregistration air bin screen layer 216, the thickness of the autoregistration air bin screen layer 216 in the middle part of contact hole are less than positioned at contact
The thickness of window both sides, as shown in figure 14.
Step 6-2), using autoregistration air bin screen layer 216 described in plasma etching, in the middle part of contact hole from right
Quasi- air bin screen layer 216 is entirely removed to form air bin window, and the autoregistration air bin positioned at contact hole both sides shields
Layer 216 is partly retained, as shown in figure 15.
Step 6-3), the conductive material 215 is etched to trench isolations knot based on the autoregistration air bin screen layer 216
Structure 204, the first air bin 217 is formed, it is 5~20, preferably 8~20 that first air bin 217, which has a depth-to-width ratio, is such as schemed
Shown in 16, after the completion of etching, with ion divest residual ion(ic) etching side product species and carry out after clean processing procedure remove surface
Residual particulates.
As shown in figure 17, step 7) is then carried out, is filled out using chemical vapor deposition method in first air bin 217
The first insulating materials 218 is filled, because first air bin 217 has a larger depth-to-width ratio, such as 8~20 so that Ke Yitong
When by controlling the chemical vapor deposition method to form the first hole 219 in first insulating materials 218.
For example, under conditions of gas pressure intensity is less than 10 supports (Torr), preferable gas pressure intensity is 2~6 supports (Torr), is adopted
With enhancing high-aspect-ratio technique eHARP (enhanced high aspect ratio process), high-density plasma sinks
Product technique HDP (High density plasma deposition), tetraethyl orthosilicate chemical vapor deposition method TEOS CVD
(Tetra-ethoxysilane Chemical Vapor Deposition) or plasma reinforced chemical vapour deposition technique
PECVD (Plasma Enhancement Chemical Vapor Deposition) is filled in first air bin 217
First insulating materials 218, while by controlling the chemical vapor deposition method to form in first insulating materials 218
One hole 219, the pressure in the first hole 219 prepared under above-mentioned preferable gas pressure intensity is 2~6 supports (Torr), can be with
Reduce due in first hole 219 pressure it is excessive and cause explosion probability of happening.Further, first hole
219 be by the completely airtight cladding of first insulating materials 218, is influenceed with preventing the pollution hole such as element in successive process
The dielectric constant of hole, while improve the mechanical stability of hole.In addition, the air bin 217 of the first hole 219 and first
Width ratio is 1:2~3, parasitic capacitance great reduction of this width than bit line 203 can be caused, substantially improve dynamic with
Signal delay Problem of Failure in machine memory read/write program, and the design length limit of bit line 203 can be extended.As an example, institute
Stating the first insulating materials 218 includes the mixed film of one or two kinds of compositions of silica and silicon nitride, in the present embodiment, institute
It is silicon nitride to state the first insulating materials 218.
As shown in Figure 18~Figure 19, step 8) is then carried out, is planarized to and exposes the 3rd insulating barrier 211 and conduction material
Material 215, the 3rd insulating barrier 211 and the second insulating barrier 210 are then removed using wet corrosion technique and form the second air bin
220.It is 5~20, preferably 8~20 that second air bin 220, which has a depth-to-width ratio,.
As shown in Figure 20~Figure 21, step 9) is finally carried out, using chemical vapor deposition method in second air bin
The second insulating materials 221 is filled in 220, because second air bin 220 has a larger depth-to-width ratio, such as 8~20 so that
Can be simultaneously by controlling the chemical vapor deposition method to form the second hole 222 in second insulating materials 221.
For example, under conditions of gas pressure intensity is less than 10 supports (Torr), preferable gas pressure intensity is 2~6 supports (Torr), is adopted
With enhancing high-aspect-ratio technique eHARP (enhanced high aspect ratio process), high-density plasma sinks
Product technique HDP (High density plasma deposition), tetraethyl orthosilicate chemical vapor deposition method TEOS CVD
(Tetra-ethoxysilane Chemical Vapor Deposition) or plasma reinforced chemical vapour deposition technique
PECVD (Plasma Enhancement Chemical Vapor Deposition) is filled in second air bin 220
Second insulating materials 221, while by controlling the chemical vapor deposition method to form in second insulating materials 221
Two holes 222, the pressure in the second hole 222 prepared under above-mentioned preferable gas pressure intensity is 2~6 supports (Torr), can be with
Reduce due in second hole 222 pressure it is excessive and cause explosion probability of happening.Further, second hole
222 be by the completely airtight cladding of second insulating materials 221, is influenceed with preventing the pollution hole such as element in successive process
The dielectric constant of hole, while improve the mechanical stability of hole.In addition, the air bin 220 of the second hole 222 and second
Width ratio is 1:2~3, parasitic capacitance great reduction of this width than bit line 203 can be caused, substantially improve dynamic with
Signal delay Problem of Failure in machine memory read/write program, and the design length limit of bit line 203 can be extended.As an example, institute
Stating the second insulating materials 221 includes the mixed film of one or two kinds of compositions of silica and silicon nitride, in the present embodiment, institute
It is silicon nitride to state the second insulating materials 221.
As shown in figure 21, the present embodiment also provides a kind of semiconductor storage unit, and it is mainly used as described in Fig. 2~Figure 21
Preparation method prepare, the semiconductor storage unit mainly includes Semiconductor substrate 205, formed in the Semiconductor substrate 205
There are active area 201, the groove isolation construction 204 of each active area 201 of isolation, the transistor wordline 202 of channel form and fin-shaped
Bit line 203；Insulating barrier, it is formed at each surface of bit line 203；Contact hole, it is formed between each bit line 203, is filled out in the contact hole
Filled with conductive material 215；First air bin 217, it is formed in the conductive material 215 of each top of groove isolation construction 204, it is described
The first insulating materials 218 is filled with first air bin 217, and hole 219 is formed in the insulating materials；Second air bin
220, it is formed between each bit line 203 and conductive material 215, the second insulating materials is filled with second air bin 220
221, and hole 222 is formed in the insulating materials.
As an example, the active area 201 is had the shape of a strip into the Semiconductor substrate 205, the transistor wordline
202 are spaced and intersect with the active area 201, and each active area 201 is correspondingly arranged two transistor wordline 202, institute's rheme
The extension of the indention of line 203 intersects with a plurality of transistor wordline 202, and every bit line 203 passes through two transistors
Active area 201 between wordline 202.
As an example, the transistor wordline 202 of the channel form includes layer of dielectric material and electrode material layer, the medium
The dielectric constant of material layer is one kind in 1~8, including silica and silicon nitride, and thickness is 1~10 nanometer；The electrode material
Material includes one kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon, and its resistivity is 2 × 10-8Ωm
~1 × 102Ωm。
As an example, there is dielectric barrier layer, its dielectric material constant between the transistor wordline 202 and bit line 203
For 1.0~10, thickness is 5~80 nanometers.
As an example, the depth-to-width ratio of the air bin 220 of the first air bin 217 and second is 5~20.
As an example, the width ratio of the air bin 217 of the first hole 219 and first is 1:2~3, second hole
222 and second air bin 220 width ratio be 1:2~3.
As an example, the insulating materials 221 of the first insulating materials 218 and second includes one kind of silica and silicon nitride
Or the mixed film of two kinds of compositions.
As an example, first hole 219 is less than 10 supports (Torr) with the gas pressure intensity in second hole 222.
Preferably, first hole 219 and the gas pressure intensity in second hole 222 are 2~6 supports (Torr).The gas pressure intensity
Scope can reduce due in the hole 222 of the first hole 219 and second pressure it is excessive and cause explosion probability of happening.It is excellent
Selection of land, the gas pressure intensity of first hole 219 can be not less than the gas pressure intensity in second hole 222.Described first
Hole 219 can not include oxidizing gas with the gas in second hole 222.
As an example, first hole 219 is by the completely airtight cladding of first insulating materials 218 described second
Hole 222 is by the completely airtight cladding of second insulating materials 221, to ensure the hole 222 of the first hole 219 and second
It is not easy to influence the dielectric constant of hole by other element pollutions, while improves the mechanical stability of hole.
Embodiment 2
As shown in Figure 22~Figure 41, the present embodiment provides a kind of preparation method of semiconductor storage unit, including step：
As shown in FIG. 22 and 23, step 1) is carried out first, there is provided semi-conductive substrate 305, the Semiconductor substrate 305
On formed with memory array structure, including active area 301, the groove isolation construction 304 of each active area 301 of isolation, channel form
Transistor wordline 302 and fin-shaped bit line 303, specific first separation layer between the transistor wordline 302 and bit line 303
307, there is the second separation layer 308 on the bit line 303, wherein, second separation layer 308 act as isolating the bit line
303 and the conductive material 315 of subsequent touch window.
In the present embodiment, the active area 301 is had the shape of a strip into the Semiconductor substrate 305, the transistor
Wordline 302 is spaced intersects with the active area 301, and each active area 301 is correspondingly arranged two transistor wordline 302, right
Isolated between every two transistor wordline 302 of Ying Yuyi active areas 301 by groove isolation construction 304, in addition, the present embodiment
Part bit line 303 can pass through some groove isolation constructions 304 position, forming portion lane place line 303 is by groove isolation construction 304
The enclosing region 306 surrounded, as shown in the dotted-line ellipse frame in Figure 22 and Figure 23；The bit line 303 linearly with it is described more
The square crossing of bar transistor wordline 302, and every bit line 303 is by the active area between two transistor wordline 302
301, as shown in Figure 22~Figure 23, wherein, Figure 23 is shown as sectional views of the Figure 22 along B-B '.
Further, the Semiconductor substrate 305 is single crystal silicon material, and the active area 301 is with element doping
Single crystal silicon material, its resistivity are 5 × 10 Ω m~5 × 103Ω m, wherein, described Ω m represent ohm meter.
The groove isolation construction 304 includes shallow trench and the dielectric material being filled in the shallow trench, the dielectric
The K values of material are typically less than 3, and it act as isolating shallow trench electric leakage and mitigating being electrically coupled (coupling), the dielectric
Material can be silica material etc., the shallow groove depths be 800~1600 nanometers between with controlling transistor degree of isolation.
The transistor wordline 302 of the channel form includes layer of dielectric material and electrode material layer, the layer of dielectric material
Dielectric constant is one kind in 1~8, including silica and silicon nitride, and thickness is 1~10 nanometer；The electrode material include tungsten,
One kind in titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon, its resistivity are 2 × 10-8Ω m~1 × 102Ω
m。
First separation layer 307 act as isolating the transistor wordline 302 and bit line 303, and it can pass through low pressure
Be vapor-deposited (Low Presure Chemical Vapor Deposition) or plasma gas-phase deposit (Plasma
Enhancement Chemical Vapor Deposition) etc. technique formed, its dielectric material constant is preferably 1.0~10,
Such as silicon nitride (Silicon Nitride), between its thickness is 5~80 nanometers.
As shown in Figure 24~Figure 25, step 2) is then carried out, in the surface of 303 and second separation layer of bit line 308 and side
Wall forms the first insulating barrier 309.
Specifically, the surface deposition of insulative material of Semiconductor substrate 305 is first equal to using such as chemical vapor deposition method, then
The insulating materials on the surface of the first separation layer 307 is removed using ion etch process, retains the bit line 303 and second and isolates
308 surface of layer and the insulating materials of side wall, form first insulating barrier 309.The resistivity of first insulating barrier 309 is 2
×1011Ω m~1 × 1025Ω m, the mixed film of one or two kinds of compositions of silica and silicon nitride can be included.
As shown in Figure 26~Figure 31, step 3) is then carried out, formation is coated on the surface of the first insulating barrier 309 successively
Second insulating barrier 310 and the 3rd insulating barrier 311, while remove and be exposed to first separation layer 307 on the surface of Semiconductor substrate 305 and reveal
Go out active area 301, form contact hole.
Specifically, step 3) includes：
Step 3-1), form the second insulating barrier 310 in the table of Semiconductor substrate 305.Second insulating barrier 310 can pass through
Technique for atomic layer deposition (ALD) or the process such as low pressure gas phase deposition (LPCVD) or Spin on Dielectrics (SOD)
Complete, its dielectric material constant be 1.0~10, such as nitrogen oxide (Silicon Nitride), thickness be 5~200 nanometers it
Between, as shown in figure 26.
Step 3-2), the 3rd insulating barrier 311 is formed in the surface of the second insulating barrier 310, the 3rd insulating barrier 311 is not
Less than the second separation layer 308 on bit line 303.3rd insulating barrier 311 can pass through technique for atomic layer deposition (ALD) or low
The process such as chemical vapor deposition (LPCVD) or Spin on Dielectrics (SOD) is completed, and its dielectric material constant is 1.0
~10, such as nitrogen oxide (Silicon Nitride), and second insulating barrier 310 and the 3rd is insulated by annealing process
Layer 311 is densified, as shown in figure 27.
Step 3-3), planarized with cmp or ion(ic) etching, as shown in figure 28, planarized after the described 3rd
Insulating barrier 311 sequentially forms hard mask 312 and graphic mask 313, and the graphic mask 313 is parallel with wordline 302 and its quantity
For the half of wordline 302, as shown in Figure 29 and Figure 30, wherein, Figure 30 is shown as Figure 29 overlooking structure figure.
Step 3-4), hard mask 312, the 3rd insulating barrier 311, the second insulating barrier 310 and are etched based on graphic mask 313
One separation layer 307, expose active area 301, form contact hole, as shown in figure 31.
The etching can be divided into two steps, and first step goes to hard mask 312 to be etched to figure, and second step is still further below
The 3rd insulating barrier 311, the second insulating barrier 310 and the first separation layer 307 are etched to exposing active area 301, and figure is divested with ion
Processing procedure, which is cleaned, after the residuals of shape mask 313 and hard mask 312 and progress removes remained on surface (Residue) and particulate
(Micro particle)。
As shown in figure 32, step 4) is then carried out, forms the 4th insulating barrier 314 for being coated on the 3rd insulating barrier 311.
As shown in Figure 33~Figure 34, step 5) is then carried out, formation is filled in the contact hole and covered to the described 4th
Conductive material 315 on insulating barrier 314, return the quarter conductive material 315 and make it below the 4th insulating barrier 314.
The conductive material 315 includes one kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon
Or two or more combinations, its resistivity are 2 × 10-8Ω m~1 × 102Ωm。
As shown in Figure 34~Figure 35, step 6) is then carried out, formation is covered in the insulating barrier of conductive material 315 and the 4th
Autoregistration air bin screen layer 316 on 314, sky is formed using autoregistration air bin screen layer 316 described in plasma etching
Gas storehouse window, and further etch the conductive material 315 and form the first air bin 317.
In the present embodiment, step 6) includes：
Step 6-1), covered using chemical vapor deposition method on the insulating barrier 314 of conductive material 315 and the 4th
Autoregistration air bin screen layer 316, the thickness of the autoregistration air bin screen layer 316 in the middle part of contact hole are less than positioned at contact
The thickness of window both sides, as shown in figure 34.
Step 6-2), using autoregistration air bin screen layer 316 described in plasma etching, in the middle part of contact hole from right
Quasi- air bin screen layer 316 is entirely removed to form air bin window, and the autoregistration air bin positioned at contact hole both sides shields
Layer 316 is partly retained, as shown in figure 35.
Step 6-3), the conductive material 315 is etched to trench isolations knot based on the autoregistration air bin screen layer 316
Structure 304, the first air bin 317 is formed, it is 5~20, preferably 8~20 that first air bin 317, which has a depth-to-width ratio, is such as schemed
Shown in 36, after the completion of etching, with ion divest residual ion(ic) etching side product species and carry out after clean processing procedure remove surface
Residual particulates.
As shown in figure 37, step 7) is then carried out, is filled out using chemical vapor deposition method in first air bin 317
The first insulating materials 318 is filled, because first air bin 317 has a larger depth-to-width ratio, such as 8~20 so that Ke Yitong
When by controlling the chemical vapor deposition method to form the first hole 319 in first insulating materials 318.
For example, under conditions of gas pressure intensity is less than 10 supports (Torr), preferable gas pressure intensity is 2~6 supports (Torr), is adopted
With enhancing high-aspect-ratio technique eHARP (enhanced high aspect ratio process), high-density plasma sinks
Product technique HDP (High density plasma deposition), tetraethyl orthosilicate chemical vapor deposition method TEOS CVD
(Tetra-ethoxysilane Chemical Vapor Deposition) or plasma reinforced chemical vapour deposition technique
PECVD (Plasma Enhancement Chemical Vapor Deposition) is filled in first air bin 317
First insulating materials 318, while by controlling the chemical vapor deposition method to form in first insulating materials 318
One hole 319, the pressure in the first hole 319 prepared under above-mentioned preferable gas pressure intensity is 2~6 supports (Torr), can be with
Reduce due in first hole 319 pressure it is excessive and cause explosion probability of happening.Further, first hole
319 be by the completely airtight cladding of first insulating materials 318, is influenceed with preventing the pollution hole such as element in successive process
The dielectric constant of hole, while improve the mechanical stability of hole.In addition, the air bin 317 of the first hole 319 and first
Width ratio is 1:2~3, parasitic capacitance great reduction of this width than bit line 303 can be caused, substantially improve dynamic with
Signal delay Problem of Failure in machine memory read/write program, and the design length limit of bit line 303 can be extended.As an example, institute
Stating the first insulating materials 318 includes the mixed film of one or two kinds of compositions of silica and silicon nitride, in the present embodiment, institute
It is silicon nitride to state the first insulating materials 218.
As shown in Figure 38~Figure 39, step 8) is then carried out, is planarized to and exposes the 3rd insulating barrier 311 and conduction material
Material 315, the 3rd insulating barrier 311 and the second insulating barrier 310 are then removed using wet corrosion technique and form the second air bin
320.It is 5~20, preferably 8~20 that second air bin 320, which has a depth-to-width ratio,.
As shown in Figure 40~Figure 41, step 9) is finally carried out, using chemical vapor deposition method in second air bin
The second insulating materials 321 is filled in 320, because second air bin 320 has a larger depth-to-width ratio, such as 8~20 so that
Can be simultaneously by controlling the chemical vapor deposition method to form the second hole 322 in second insulating materials 321.
For example, under conditions of gas pressure intensity is less than 10 supports (Torr), preferable gas pressure intensity is 2~6 supports (Torr), is adopted
With enhancing high-aspect-ratio technique eHARP (enhanced high aspect ratio process), high-density plasma sinks
Product technique HDP (High density plasma deposition), tetraethyl orthosilicate chemical vapor deposition method TEOS CVD
(Tetra-ethoxysilane Chemical Vapor Deposition) or plasma reinforced chemical vapour deposition technique
PECVD (Plasma Enhancement Chemical Vapor Deposition) is filled in second air bin 320
Second insulating materials 321, while by controlling the chemical vapor deposition method to form in second insulating materials 321
Two holes 322, the pressure in the second hole 322 prepared under above-mentioned preferable gas pressure intensity is 2~6 supports (Torr), can be with
Reduce due in second hole 322 pressure it is excessive and cause explosion probability of happening.Further, second hole
322 be by the completely airtight cladding of second insulating materials 321, is influenceed with preventing the pollution hole such as element in successive process
The dielectric constant of hole, while improve the mechanical stability of hole.In addition, the air bin 320 of the second hole 322 and second
Width ratio is 1:2~3, parasitic capacitance great reduction of this width than bit line 303 can be caused, substantially improve dynamic with
Signal delay Problem of Failure in machine memory read/write program, and the design length limit of bit line 303 can be extended.As an example, institute
Stating the second insulating materials 321 includes the mixed film of one or two kinds of compositions of silica and silicon nitride, in the present embodiment, institute
It is silicon nitride to state the second insulating materials 321.
As shown in figure 41, the present embodiment also provides a kind of semiconductor storage unit, and it is mainly used such as Figure 22~Figure 41 institutes
Prepared by the preparation method stated, the semiconductor storage unit mainly includes Semiconductor substrate 305, shape in the Semiconductor substrate 305
Into have active area 301, the groove isolation construction 304 of each active area 301 of isolation, channel form transistor wordline 302 and fin-shaped
Bit line 303；Insulating barrier, it is formed at each surface of bit line 303；Contact hole, it is formed between each bit line 303, in the contact hole
Filled with conductive material 315；First air bin 317, it is formed in the conductive material 315 of each top of groove isolation construction 304, institute
State and the first insulating materials 318 is filled with the first air bin 317, and hole 319 is formed in the insulating materials；Second air
Storehouse 230, it is formed between each bit line 303 and conductive material 315, the second insulating materials is filled with second air bin 320
321, and hole 322 is formed in the insulating materials.
As an example, the active area 301 is had the shape of a strip into the Semiconductor substrate 305；The transistor wordline
302 are spaced and intersect with the active area 301, and each active area 301 is correspondingly arranged two transistor wordline 302；Institute's rheme
Line 303 is linearly with a plurality of square crossing of transistor wordline 302, and every bit line 303 passes through two word transistors
Active area 301 between line 302.
As an example, the transistor wordline 302 of the channel form includes layer of dielectric material and electrode material layer, the medium
The dielectric constant of material layer is one kind in 1~8, including silica and silicon nitride, and thickness is 1~10 nanometer；The electrode material
Material includes one kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type polysilicon, and its resistivity is 2 × 10-8Ωm
~1 × 102Ωm。
As an example, there is dielectric barrier layer, its dielectric material constant between the transistor wordline 302 and bit line 303
For 1.0~10, thickness is 5~80 nanometers.
As an example, the depth-to-width ratio of the air bin 320 of the first air bin 317 and second is 5~20.
As an example, the width ratio of the air bin 317 of the first hole 319 and first is 1:2~3, second hole
322 and second air bin 320 width ratio be 1:2~3.
As an example, the insulating materials 321 of the first insulating materials 318 and second includes one kind of silica and silicon nitride
Or the mixed film of two kinds of compositions.
As an example, first hole 319 is less than 10 supports (Torr) with the gas pressure intensity in second hole 322.
Preferably, first hole 319 and the gas pressure intensity in second hole 322 are 2~6 supports (Torr).The gas pressure intensity
Scope can reduce due in the hole 322 of the first hole 319 and second pressure it is excessive and cause explosion probability of happening.
As an example, first hole 319 is by the completely airtight cladding of first insulating materials 318 described second
Hole 322 is by the completely airtight cladding of second insulating materials 321, to ensure the hole 322 of the first hole 319 and second
It is not easy to influence the dielectric constant of hole by other element pollutions, while improves the mechanical stability of hole.
As described above, semiconductor storage unit of the present invention and preparation method thereof, has the advantages that：
The present invention makes memory lines group contact hole using lithographic process, while utilizes automatic alignment and flatening process,
Gap between bit line makes air chamber structure, substantially improves signal delay in dynamic RAM read-write program and fails
Problem, and the bit line design length limit can be extended, to be laid out more electric capacity in unit area.In the present invention, bit line it
Between clearance air chamber structure can effectively reduce by more than 15% bit line parasitic capacitance.So the present invention effectively overcomes now
There is the various shortcoming in technology and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (18)
1. a kind of preparation method of semiconductor storage unit, it is characterised in that including step：
Semi-conductive substrate is provided, in the Semiconductor substrate formed with active area, each active area of isolation groove isolation construction,
The bit line of wordline and fin-shaped；
Insulating barrier is formed in each bit line surface, contact hole is formed between each bit line and fills conductive material；
The first air bin is produced in conductive material above each groove isolation construction, it is empty in described first using depositing operation
The first insulating materials is filled in gas storehouse, while the first hole is formed in first insulating materials by controlling the depositing operation
Hole；And
The second air bin is produced between each bit line and conductive material, is filled using depositing operation in second air bin
Second insulating materials, while form the second hole in second insulating materials by controlling the long-pending technique.
2. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that：
The active area is had the shape of a strip into the Semiconductor substrate, and the wordline is the transistor wordline of channel form, described
Transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two transistor wordline, the bit line
With the transistor wordline square crossing, and the active area that every bit line passes through between two transistor wordline.
3. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that formed in each bit line surface
Insulating barrier and contact hole is formed between each bit line and fills conductive material and includes：
The first insulating barrier is formed in the bit line surface；
The second insulating barrier is formed in semiconductor substrate surface；
The 3rd insulating barrier is formed in second surface of insulating layer, the 3rd insulating barrier is not less than the top of bit line；
Planarization sequentially forms hard mask and graphic mask after the 3rd surface of insulating layer, and the graphic mask is put down with wordline
Row and its quantity are the half of wordline；
It is etched down to based on graphic mask and exposes active area, forms contact hole；
Form the 4th insulating barrier for being coated on the 3rd insulating barrier；And
Form the conductive material for being filled in the contact hole.
4. the preparation method of semiconductor storage unit according to claim 3, it is characterised in that：Make the first air bin bag
Include：
Etch the insulating barrier that the conductive material makes it below each bit line surface；
Autoregistration air bin screen is covered on the conductive material and the 4th insulating barrier using chemical vapor deposition method
Layer is covered, the thickness of the autoregistration air bin screen layer in the middle part of contact hole is less than the thickness positioned at contact hole both sides；
Using autoregistration air bin screen layer described in plasma etching, the autoregistration air bin screen layer quilt in the middle part of contact hole
All remove and form air bin window, and the autoregistration air bin screen layer positioned at contact hole both sides is partly retained；And
The conductive material is etched to groove isolation construction based on the autoregistration air bin screen layer, forms the first air bin.
5. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that：Make the second air bin bag
Include：
The first insulating barrier is formed in the bit line surface；
The second insulating barrier is formed in semiconductor substrate surface；
The 3rd insulating barrier is formed in second surface of insulating layer；
Contact hole is formed between each bit line and fills conductive material；And
Second insulating barrier and the 3rd insulating barrier are removed by wet corrosion technique to be formed between bit line and conductive material
The second air bin.
6. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that：First air bin and
The depth-to-width ratio of second air bin is 5~20.
7. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that：In the first air bin and
Fill insulant and the technique of hole is formed in the insulating materials include enhancing high-aspect-ratio technique, height in two air bins
In density plasma depositing operation, tetraethyl orthosilicate chemical vapor deposition method and plasma reinforced chemical vapour deposition technique
One kind.
8. the preparation method of semiconductor storage unit according to claim 1, it is characterised in that：First hole and
The width ratio of one air bin is 1:2~3；The width ratio of second hole and the second air bin is 1:2~3.
A kind of 9. semiconductor storage unit, it is characterised in that including
Semiconductor substrate, in the Semiconductor substrate formed with active area, the groove isolation construction of each active area of isolation, wordline with
And the bit line of fin-shaped；
Insulating barrier, it is formed at each bit line surface；
Contact hole, it is formed between each bit line, conductive material is filled with the contact hole；
First air bin, it is formed in the conductive material above each groove isolation construction, filled with the in first air bin
One insulating materials, and formed with the first hole in first insulating materials；And
Second air bin, it is formed between each bit line and conductive material, the second insulating materials is filled with second air bin,
And formed with the second hole in second insulating materials.
10. semiconductor storage unit according to claim 9, it is characterised in that：
The active area is had the shape of a strip into the Semiconductor substrate, and the wordline is the transistor wordline of channel form, described
Transistor wordline is spaced intersects with the active area, and each active area is correspondingly arranged two transistor wordline, the bit line
With the transistor wordline square crossing, and the active area that every bit line passes through between two transistor wordline.
11. semiconductor storage unit according to claim 9, it is characterised in that：The transistor wordline bag of the channel form
Layer of dielectric material and electrode material layer are included, the dielectric constant of the layer of dielectric material is in 1~8, including silica and silicon nitride
One kind, thickness be 1~10 nanometer；It is more that the electrode material includes tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon and p-type
One kind in crystal silicon, its resistivity are 2 × 10-8Ω m~1 × 102Ωm。
12. semiconductor storage unit according to claim 9, it is characterised in that：Have between the wordline and bit line and be situated between
Electricity isolated layer, its dielectric material constant are 1.0~10, and thickness is 5~80 nanometers.
13. semiconductor storage unit according to claim 9, it is characterised in that：First air bin and the second air
The depth-to-width ratio in storehouse is 5~20.
14. semiconductor storage unit according to claim 9, it is characterised in that：First hole and the first air bin
Width ratio be 1:2~3；The width ratio of second hole and the second air bin is 1:2~3.
15. semiconductor storage unit according to claim 9, it is characterised in that：First insulating materials and described
Two insulating materials include the mixed film of silica and the one of which of silicon nitride or two kinds of compositions.
16. semiconductor storage unit according to claim 9, it is characterised in that：First hole and second hole
Gas pressure intensity in hole is less than 10 supports.
17. semiconductor storage unit according to claim 9, it is characterised in that：First hole is by described first
The completely airtight cladding of insulating materials.
18. semiconductor storage unit according to claim 17, it is characterised in that：Second hole is by described second
The completely airtight cladding of insulating materials.
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| CN107546226A (en) * | 2017-09-29 | 2018-01-05 | 睿力集成电路有限公司 | Memory and its manufacture method |
| CN109979940B (en) * | 2017-12-27 | 2021-03-26 | 长鑫存储技术有限公司 | Semiconductor memory device and method of manufacturing the same |
| CN110299324B (en) * | 2018-03-22 | 2024-03-26 | 长鑫存储技术有限公司 | Transistor structure of semiconductor memory and method for manufacturing the same |
| CN110797340A (en) * | 2018-08-03 | 2020-02-14 | 长鑫存储技术有限公司 | Semiconductor memory device with a memory cell having a plurality of memory cells |
| CN110875314A (en) * | 2018-08-30 | 2020-03-10 | 长鑫存储技术有限公司 | Bit line structure, preparation method thereof and memory |
| CN112992774B (en) * | 2019-12-02 | 2022-06-10 | 长鑫存储技术有限公司 | Method for forming gap |
| US11227865B2 (en) * | 2020-02-05 | 2022-01-18 | Nanya Technology Corporation | Semiconductor device having buried word line and method of manufacturing the same |
| CN111463204A (en) * | 2020-04-08 | 2020-07-28 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN113517289B (en) * | 2020-04-10 | 2024-02-09 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN111463208B (en) | 2020-04-29 | 2021-10-26 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN113035775B (en) * | 2021-02-25 | 2023-04-28 | 长鑫存储技术有限公司 | Memory device and method of manufacturing the same |
| US11854880B2 (en) | 2021-02-25 | 2023-12-26 | Changxin Memory Technologies, Inc. | Memory device and method for manufacturing the same |
| CN116133366A (en) * | 2021-08-11 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116096068A (en) * | 2021-10-29 | 2023-05-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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