CN110299324B - Transistor structure of semiconductor memory and method for manufacturing the same - Google Patents
Transistor structure of semiconductor memory and method for manufacturing the same Download PDFInfo
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- CN110299324B CN110299324B CN201810241906.0A CN201810241906A CN110299324B CN 110299324 B CN110299324 B CN 110299324B CN 201810241906 A CN201810241906 A CN 201810241906A CN 110299324 B CN110299324 B CN 110299324B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 118
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 238000002513 implantation Methods 0.000 claims abstract description 85
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 14
- 230000005684 electric field Effects 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 41
- 238000002955 isolation Methods 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 19
- 239000007943 implant Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 12
- 239000002019 doping agent Substances 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000007787 solid Substances 0.000 description 3
- 208000032750 Device leakage Diseases 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- 229910052787 antimony Inorganic materials 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a transistor structure of a semiconductor memory and a manufacturing method thereof, wherein the method comprises the following steps: forming an active region and a word line intersecting the active region on a substrate; forming a contact window between two word lines and depositing a conductive material; forming bit lines on the substrate and crossing the active regions in an staggered manner; etching the conductive material uncovered by the bit line to form a bit line contact pad; and implanting ions into the active region through the uncovered region in the contact window to form an ion re-implantation region, and forming an ion re-implantation diffusion region on the side of the active region, which is close to the word line, by utilizing the scattering of the ions. The invention implants ions through the narrow uncovered area in the contact window to form the ion re-implantation area and the ion re-implantation diffusion area, and reduces the original doping concentration of the active area, slows down the electric field intensity and improves the electric leakage on the premise of not influencing the current path and the resistance of the bit line contact.
Description
Technical Field
The present invention relates to the field of semiconductor storage technology, and more particularly, to a transistor structure of a semiconductor memory for improving leakage using ion implantation scattering and a method of manufacturing the same.
Background
Conventional semiconductor memory cells are typically formed of a MOS (Metal-Oxide Semiconductor, metal oxide semiconductor) transistor and a capacitor, with information stored as charge on the plates of the capacitor. However, since the contact electrode plate of the capacitor is connected with the source-drain region of the transistor, the leakage current of the PN junction of the source-drain region easily causes the leakage phenomenon of the capacitor, which results in unstable information stored in the memory cell. The method for inhibiting leakage current in the background technology is to inject ions in the bit line contact window area, which are opposite to the original doping in the source drain electrode area, so as to reduce the concentration of the original doping impurities in the source drain electrode area, further slow down the electric field intensity of PN junction of the source drain electrode area and improve or inhibit the generation of leakage current. But the current path and resistance under the bit line contact in the bit line contact region are severely affected by the ion implantation in the bit line contact region. How to control the ion implantation area of the bit line contact window area and eliminate the influence of the ion implantation on the current path and the resistance under the bit line contact becomes a subject in the technical field.
Disclosure of Invention
Embodiments of the present invention provide a transistor structure of a semiconductor memory device for improving leakage using ion implantation scattering and a method for fabricating the same, which solve or alleviate one or more technical problems in the prior art, and at least provide a beneficial choice.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a transistor structure of a semiconductor memory, including:
providing a substrate and forming a plurality of active regions in the substrate;
forming a plurality of embedded word lines in the substrate, wherein each active area is intersected with two word lines;
etching a central region between the two intersecting word lines in the active region of the substrate to form a contact window;
depositing a conductive material on the contact window and the area of the substrate between the active areas;
forming a bit line on the substrate;
etching the conductive material by taking the bit line as a mask to form a bit line contact pad in the contact window, wherein the overlapped area of the bit line and the active area is not completely matched with the contact window in shape and size, so that the bit line contact pad is formed below the area of the bit line covering the active area and is not completely filled in the contact window, and the contact window comprises an area which is not covered by the bit line contact pad and the bit line; and
and implanting ions into the active region through the uncovered region of the contact window to form an ion re-implantation region so as to slow down the electric field intensity of the contact window outside the overlapped region of the bit line.
In some embodiments, the shape of the ion re-implantation region on the active region comprises a triangle.
In some embodiments, the source and drain regions on both sides of the active region are further formed as ion re-implantation diffusion regions adjacent to the word line on sides near the word line.
In some embodiments, the ion re-implantation is of a type opposite to the ion type originally doped in the active region such that the ion concentration of the original doping in the ion re-implantation region is lower than the ion concentration of the original doping in the active region.
In some embodiments, in the step of providing the substrate, an isolation structure is disposed in the substrate, the isolation structure being formed between adjacent ones of the active regions.
In some embodiments, the word line is buried in the substrate in a linear extension manner and penetrates through the active region and the isolation structure between the active regions, and the implantation depth of the ion re-implantation region is equal to or greater than a first implantation depth of the top surface of the word line from the upper surface of the substrate, but less than the ion implantation depth of the active region.
In some embodiments, in the step of forming the bit lines, the bit lines are arranged on the substrate in a wave-like extending manner, and a section length of the bit lines overlapped on the isolation structure is greater than twice a section length of the bit lines overlapped on the active region.
In some embodiments, the method of manufacturing further comprises: after the word lines are formed, a protective layer is deposited on the surface of the active region and the word lines, and an opening groove of the protective layer is formed between the word lines so as to form the contact window of the active region subsequently.
In a second aspect, an embodiment of the present invention provides a transistor structure of a semiconductor memory, including:
a substrate in which an active region is formed;
a word line buried in the substrate and intersecting the active region; the active region is provided with a contact window and is positioned between two adjacent word lines;
a bit line contact pad deposited on the contact window; and
bit lines formed on the substrate, the bit lines and the active regions intersecting each other at staggered locations to connect the bit line contact pads, the bit line contact pads being formed under the regions of the bit lines covering the active regions without completely filling the contact windows;
the active region is also provided with an ion re-implantation region which is positioned in the contact window and does not cover the bit line contact pad and the bit line region so as to slow down the electric field intensity of the contact window outside the overlapping region of the bit line.
In some embodiments, the contact window is formed by locally etching a middle portion of the active region.
In some embodiments, the source and drain regions on both sides of the active region are further formed as ion re-implantation diffusion regions adjacent to the word line on sides near the word line.
In some embodiments, isolation structures are disposed in the substrate, the isolation structures being formed between adjacent ones of the active regions.
In some embodiments, the word line is buried in the substrate in a linear extension, and the ion re-implantation region has an implantation depth equal to or greater than a first implantation depth of a top surface of the word line from an upper surface of the substrate, but less than an ion implantation depth of the active region.
In some embodiments, the bit lines are arranged in a wavy extension on the substrate such that a section length of the bit lines overlapping the isolation structures is greater than twice a section length of the bit lines overlapping the active region.
In some implementations, the word line includes a word line body to form a top surface of the word line and a word line conductive layer surrounding the word line body, a top end of the word line conductive layer being greater than a first buried depth of the top surface of the word line from the upper surface of the substrate, but less than an implantation depth of the ion re-implantation region.
In some embodiments, the overlap area of the word line conductive layer and the ion re-implantation region is smaller than the overlap area of the word line conductive layer and the active region.
According to the transistor structure of the semiconductor memory and the manufacturing method thereof, in the manufacturing process of the bit line, a narrow uncovered area is formed in the contact window, ions are injected into the source drain region to form a low-concentration ion re-injection area and an ion re-injection diffusion area, so that the electric field intensity outside the overlapping area of the contact window on the bit line is slowed down, the purpose of improving electric leakage is achieved, and meanwhile, the influence on a current path and a resistance value of a bit line contact is not caused due to the fact that the areas of the ion re-injection area and the ion re-injection diffusion area are small.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
FIG. 1a is a top view of the surface of a substrate after an active region has been formed in the substrate in accordance with one embodiment of the present invention;
FIG. 1b is a cross-sectional view taken along line A-A of FIG. 1 a;
FIG. 2a is a top view of the substrate surface after forming isolation structures in active areas, in accordance with one embodiment of the present invention;
FIG. 2b is a cross-sectional view taken along line A-A of FIG. 2 a;
FIG. 3a is a top view of the substrate surface after forming word lines in the substrate in accordance with one embodiment of the present invention;
FIG. 3B is a cross-sectional view taken along line B-B in FIG. 3 a;
FIG. 4a is a top view of the surface of a substrate after deposition of a protective layer over the active area and word lines in accordance with one embodiment of the present invention;
FIG. 4B is a cross-sectional view taken along line B-B in FIG. 4 a;
FIG. 5a is a top view of a substrate surface after etching a contact window in accordance with one embodiment of the present invention;
FIG. 5B is a cross-sectional view taken along line B-B in FIG. 5 a;
fig. 6a is a top view of the substrate surface after depositing conductive material in the contact window in accordance with one embodiment of the present invention;
FIG. 6B is a cross-sectional view taken along line B-B in FIG. 6 a;
FIG. 7a is a top view of the substrate surface after deposition of bit line material and generation of photoresist patterns in accordance with one embodiment of the present invention;
FIG. 7B is a cross-sectional view taken along line B-B in FIG. 7 a;
FIG. 8a is a top view of the surface of a substrate after etching of a bit line material in accordance with one embodiment of the present invention;
FIG. 8B is a cross-sectional view taken along line B-B of FIG. 8 a;
FIG. 9a is a top view of the substrate surface after etching conductive material to form bit line contact pads and ion re-implantation regions in accordance with one embodiment of the present invention;
FIG. 9B is a cross-sectional view taken along line B-B in FIG. 9 a;
FIG. 10a is a top view of the surface of a substrate after ion re-implantation in accordance with one embodiment of the present invention;
FIG. 10B is a cross-sectional view taken along line B-B in FIG. 10a showing ions being implanted into the active region through the ion re-implantation region and scattered;
FIG. 10c is a cross-sectional view taken along line B-B of FIG. 10a after formation of an ion implantation re-diffusion region;
FIG. 11a is a top view of the substrate surface after deposition of a protective layer and covering the bit lines in accordance with one embodiment of the present invention;
FIG. 11B is a cross-sectional view taken along line B-B in FIG. 11 a;
FIG. 12a is a top view of the surface of a substrate after formation of a capacitive touch pad in accordance with one embodiment of the invention;
fig. 12B is a cross-sectional view taken along line B-B in fig. 12 a.
Reference numerals illustrate:
110: a substrate;
111: an active region; 111A, 111B, 111C: a source drain region;
111D: a contact window; 111E: uncovered areas of the contact window;
111F: ion re-implantation regions; 111G: ion re-implantation into the diffusion region;
112: an isolation structure;
120: a word line; 121: an insulating layer;
122: a word line conductive layer; 123: word line body
124 upper chambers of word lines;
130: bit line contact pads;
140: a bit line;
150: a protective layer;
160: a capacitor contact electrode plate;
200: a conductive material;
300: bit line material;
400: and a photoresist pattern corresponding to the bit line.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
The transistor structure of the semiconductor memory device and the method of manufacturing the same according to the present invention are described in detail below with reference to fig. 1a to 12b.
The embodiment of the invention provides a manufacturing method of a transistor structure of a semiconductor memory, which comprises the following steps.
In step S101, a substrate 110 is provided, and a plurality of active regions 111 are formed in the substrate 110, as shown in fig. 1a, 1b. Specifically, a substrate 110 is provided, in one embodiment, the substrate 110 is P-type or N-type; a photoresist is coated on the surface of the substrate 110 and a photoresist pattern (not shown) is formed, and a dopant opposite to the dopant type in the substrate 110 is implanted into the substrate 110 through the photoresist pattern to form a plurality of active regions 111, and in one embodiment, the implanted dopant is N-type (e.g., phosphorus, arsenic, antimony, etc.) when the substrate 110 is P-type, and the implanted dopant is P-type (e.g., boron, gallium, etc.) when the substrate 110 is N-type. The active regions 111 are arranged with each other to form an active region array. Fig. 1a is a top view of the surface of a substrate 110 after active regions 111 are formed in the substrate 110 in accordance with one embodiment of the present invention. Fig. 1b is a cross-sectional view taken along line A-A of fig. 1a, as shown, with active regions 111 formed on the surface of substrate 110 and not extending through substrate 110, with the two active regions 111 being separated from each other.
In step S102, the regions of the substrate 110 where the active regions 111 are separated from each other are etched, see fig. 2a, 2b. Specifically, a photoresist is deposited on the surface of the substrate 110 and a photoresist pattern (not shown) is formed, and regions of the active regions 111 separated from each other are etched by the photoresist pattern, as shown in fig. 2 a. In one embodiment, the etch depth is greater than the depth of the dopant implantation of active region 111, see fig. 2b. Subsequently, an isolation material is deposited to form isolation structures 112 between active regions 111, as shown in FIG. 2b, in one embodiment the isolation material comprises SiO 2 。
In step S103, a plurality of buried word lines 120 are formed in the substrate 110, see fig. 3a, 3b. Specifically, a plurality of recesses (not shown) are etched in the substrate 110, and in one embodiment, the method of etching includes wet etching. In one embodiment, the grooves are formed in the substrate 110 in a straight line extending manner and penetrate the active regions 111 and the isolation structures 112 between the active regions 111, the grooves are parallel to each other and intersect the active regions 111 at a certain angle, and each active region 111 intersects two of the grooves and is partitioned into three source-drain regions 111A, 111B, 111C. An insulating layer 121, a word line conductive layer 122, a seed layer (not shown), and a word line body 123 are sequentially deposited along the inner walls of the grooves to form word lines 120, and upper portions of the word line conductive layer 122, the seed layer, and the word line body 123 are removed by etching to form upper chambers 124 of the word lines 120, as shown in fig. 3a and 3b. The insulating layer 121 serves to insulate the word line 120 from the surrounding substrate 110 and active region 111. In one embodiment, the insulating layer 121 comprises silicon dioxide; the word line conductive layer 122 functions to prevent the diffusion of atoms of the word line body 123 to the insulating layer 121, the active region 111, and the substrate 110, and in one embodiment, the word line conductive layer 122 includes titanium or titanium nitride, etc.; the seed layer serves as a nucleation center for the wordline body 123 for guiding deposition of a subsequent wordline body 123, in one embodiment the seed layer has the same composition as the wordline body 123; the function of the word line body 123 is to form a body portion of the word line 120. In one embodiment, the word line body 123 comprises metal tungsten or the like.
The word lines 120 extend in a direction in which the active regions 111 and the isolation structures 112 are alternately arranged, and intersect the active regions 111 and the isolation structures 112, wherein each active region 111 intersects two word lines 120.
In step S104, a passivation layer 150 is deposited to cover the surface of the active region 111 and the word line 120 and fill the upper chamber 124 of the word line 120, as shown in fig. 4a and 4 b. The protection layer 150 serves to prevent contamination of impurities and to insulate the surface of the active region 111 and the upper portion of the word line 120 (i.e., the word line conductive layer 122, the seed layer, and the upper portion of the word line body 123), and in one embodiment, the protection layer 150 comprises silicon nitride or the like.
In step S105, the protection layer 150 in the central region between the two intersecting word lines 120 in the active region 111 of the substrate 110 is etched to the source/drain region 111A and the isolation structure 112 to form a through contact 111D, see fig. 5a and 5b. In one embodiment, the sidewalls of contact 111D do not contact the sidewalls of word line 120, separating a portion of active drain region 111A. In addition, as shown in the figure, after the contact window 111D is etched, the bottom of the contact window 111D exposes the silicon surface layer of the source/drain region 111A and the isolation material of the isolation structure 112.
In step S106, a conductive material 200 is deposited in the contact 111D and on the substrate 110 in the areas between the active regions 111, as shown in fig. 6a, 6 b. The upper surface of the conductive material 200 is flush with the protective layer 150. In one embodiment, the conductive material 200 comprises doped polysilicon or the like.
In step S107, a bit line material 300 is deposited and a photoresist pattern 400 corresponding to the bit line 140 is generated. Specifically, as shown in fig. 7a and 7b, a bit line material 300 is deposited on the entire surface of the substrate 110 to cover the protective layer 150 and the conductive material 200, and a photoresist is coated on the bit line material 300 and a photoresist pattern 400 corresponding to the bit line 140 is formed.
In step S108, the bit line material 300 is etched using the photoresist pattern 400 and the photoresist pattern 400 is removed, thereby forming a plurality of bit lines 140. As shown in fig. 8a and 8B, the bit lines 140 are preferably formed on the substrate 110 in a wavelike extending manner, and are regularly arranged at a certain interval, each bit line 140 is staggered with the plurality of active regions 111, the word lines 120 and the conductive material 200, and the section length of the bit lines 140 overlapped on the isolation structure 112 is greater than the section length of the bit lines 140 overlapped on the active regions 111 by more than two times, so that the source and drain regions 111A, 111B and 111C at two sides of the active regions 111 have a larger exposed area for installing the capacitor contact electrode plate 160.
In step S109, the conductive material 200 is etched using the bit line 140 as a mask to form the bit line contact pad 130 in the contact 111D, see fig. 9a and 9b. Specifically, the conductive material 200 in the contact 111D is etched to remove the conductive material 200 outside of the under bit line 140. Because bit line 140 is interleaved with active region 111, the overlapping area of bit line 140 and active region 111 is not fully matched in shape and size to contact 111D, such that the portion of conductive material 200 over active region 111 is not fully covered by bit line 140, uncovered conductive material 200 is etched away and conductive material 200 that is covered under bit line 140 is left, thereby forming bit line contact pad 130 under the area where bit line 140 covers active region 111, bit line contact pad 130 does not fully fill contact 111D, and bit line contact pad 130 is connected to the portion of bit line 140 that is interleaved over active region 111.
Meanwhile, the conductive material 200 on the active region 111 uncovered by the bit line 140 is etched to form an uncovered region 111E of the contact 111D, and expose the source/drain region 111A of the active region 111. In other words, the uncovered region 111E of the contact 111D is formed in the contact 111D and does not cover the bit line contact pad 130 and the bit line 140.
In step S110, ions are implanted into the active region 111 through the uncovered region 111E of the contact 111D, so as to form an ion re-implantation region 111F in the source/drain region 111A of the active region 111, as shown in fig. 10a, 10b, and 10c. In one embodiment, the shape of the ion re-implantation region 111F over the active region 111 comprises a triangle. Referring to fig. 10b, the dashed arrows in the uncovered region 111E of the contact 111D represent the direction of implanted ions, which in one embodiment are implanted using an ion implantation technique (Iron Implantation). The ions are also scattered (Scattering) when they are implanted into the source and drain regions 111A, 111B, 111C, thereby forming ion re-implantation diffusion regions 111G at the sides of the source and drain regions 111A, 111B, 111C near the word line 120. The vertical downward solid arrows in the active region 111 represent the direction of ion implantation, while the diagonal solid arrows represent the direction of scattering of ions in the source and drain regions 111B, 111C (solid arrows attached with reference numerals are not included). Fig. 10a and 10c show a top view and a cross-sectional view, respectively, of ion implantation followed by formation of an ion re-implantation region 111F and an ion re-implantation diffusion region 111G. In one embodiment, the ion re-implantation diffusion 111G is adjacent to a sidewall of the word line 120. The formation of the ion re-implantation region 111F and the ion re-implantation diffusion region 111G may slow down the electric field strength of the contact 111D outside the overlapping region of the bit line 140.
The implantation depth of the ion re-implantation region 111F is equal to or greater than the implantation depth of the top surface of the word line 120 from the upper surface of the substrate 110, but less than the ion implantation depth of the active region 111.
In addition, it should be noted that the implanted ions have a type opposite to the originally doped ions in the active region 111, so that the concentration of the originally doped ions in the ion re-implantation region 111F is lower than the concentration of the originally doped ions in the active region 111, thereby reducing the electric field strength of the contact 111D outside the overlapping region of the bit line 140 and reducing or preventing the occurrence of device leakage.
In one embodiment, when the substrate 110 is P-type, the active region 111 (i.e., the source/drain regions 111A, 111B, 111C) is heavily doped with N + P of opposite type is implanted through the uncovered region 111E of the contact 111D + In the case of the type ion, an ion implantation region 111F is formed, and at the same time, P + The type ions scatter in the source/drain regions 111A, 111B, 111C to form P + Ions of the type ions are re-implanted into the diffusion region 111G. Due to P + Dilution of ions to cause ion re-implantation into region 111F and ion re-implantation into diffusion region 111GN of (2) + The doping concentration is reduced to become lightly doped N - An area.
In another embodiment, when the substrate 110 is N-type, the active region 111 (i.e. source/drain regions 111A, 111B, 111C) is heavily doped with P + N of opposite type is implanted through the uncovered region 111E of the contact 111D + In the case of the type ion, an ion implantation region 111F is formed, and at the same time, N + The type ions scatter in the source/drain regions 111A, 111B, 111C to form N + Ions of the type ions are re-implanted into the diffusion region 111G. Due to N + Dilution of ions to cause ion re-implantation of region 111F and ion re-implantation of P in diffusion region 111G + The doping concentration is reduced to become lightly doped P - An area.
Because the ion re-implantation region 111F and the ion re-implantation diffusion region 111G have a smaller range, the current path and resistance of the bit line contact (i.e., the contact between the bit line contact pad 130 and the source/drain region 111A) under the bit line 140 are not affected.
In step S111, a protective layer 150 is deposited over the entire substrate 110 surface and covering the bit lines 140, see fig. 11a, 11b. As shown in fig. 11b, the deposited protective layer 150 fills the ion re-implantation region 111F.
In step S112, holes are punched from the surface of the protection layer 150 to the surfaces of the source and drain regions 111B and 111C over the source and drain regions 111B and 111C, and conductive material is deposited to form the capacitor contact plate 160, see fig. 12a and 12B. As shown in fig. 12B, the capacitor contact plate 160 is electrically contacted with the source and drain regions 111B and 111C, and the ion re-implantation diffusion region 111G is located below the capacitor contact plate 160. In one embodiment, the conductive material forming the capacitive contact pad 160 comprises polysilicon, metallic tungsten, or the like.
In another aspect of the present invention, embodiments of a transistor structure of a semiconductor memory are also provided corresponding to a method of manufacturing a transistor structure of a semiconductor memory. As shown in fig. 10a, 10c, in one embodiment, the transistor structure of the semiconductor memory includes a substrate 110, a word line 120, a bit line contact pad 130, a bit line 140, and a protective layer 150.
Wherein, the substrate 110 is provided therein withA plurality of active regions 111 are disposed, and the active regions 111 are arranged to be spaced apart from each other to form an active region array, see fig. 10a; the active region 111 is formed on the surface of the substrate 110 and does not penetrate the substrate 110, as shown in fig. 10c. An isolation structure 112 is formed between the active regions 111, and in one embodiment, the isolation material comprises SiO 2 。
The word lines 120 are formed in the substrate 110 in a buried manner, the word lines 120 are formed in the substrate 110 in a linear extending manner and penetrate through the active regions 111 and the isolation structures 112 between the active regions 111, the word lines 120 are parallel to each other and intersect the active regions 111 at a certain angle, each word line 120 intersects a plurality of active regions 111, and each active region 111 intersects two word lines 120 and is partitioned into three source drain regions 111A, 111B, 111C. The word line 120 includes an insulating layer 121, a word line conductive layer 122, a seed layer (not shown), and a word line body 123 in this order from the sidewall toward the central axis, the word line body 123 forming the top surface of the word line 120, the word line conductive layer 122 covering the word line body 123; an upper chamber 124 is further formed at an upper portion of the word line 120, and the upper chamber 124 is formed by etching an upper portion of the word line conductive layer 122, the seed layer, and the word line body 123. In one embodiment, insulating layer 121 comprises silicon dioxide, word line conductive layer 122 comprises titanium or titanium nitride, etc., word line body 123 comprises metallic tungsten, etc., and the seed layer is the same material as word line body 123.
The source/drain region 111A further has a contact 111D between two adjacent word lines 120, and the contact 111D is formed by partially etching the source/drain region 111A. In one embodiment, the sidewalls of contact 111D do not contact the sidewalls of word line 120, separating a portion of active drain region 111A. A bit line contact pad 130 is deposited in the contact 111D, and in one embodiment, the bit line contact pad 130 comprises polysilicon or the like.
The bit lines 140 are formed on the substrate 110 in a wavelike extending manner, and are regularly arranged at a certain interval, each bit line 140 intersects with the plurality of active regions 111 and the word lines 120 at intervals, and the length of the section of the bit line 140 overlapped on the isolation structure 112 is greater than the length of the section of the bit line 140 overlapped on the active region 111 by more than two times, so that the source/drain regions 111A, 111B and 111C at two sides of the active region 111 have larger exposed areas for installing the capacitor contact electrode plate 160. The bit line contact pad 130 is formed under the region of the bit line 140 covering the active region 111 without completely filling the contact 111D, and is connected to the bit line 140 at the staggered portion on the active region 111.
The contact 111D also has an uncovered region 111E in the contact 111D that does not cover the bit line contact pad 130 and bit line 140, and ions are implanted into the active region 111 through the uncovered region 111E of the contact 111D.
Ion re-implantation regions 111F and ion re-implantation diffusion regions 111G are formed on the sides of the active region 111 (i.e., source-drain regions 111A, 111B, 111C) near the word line 120, and in one embodiment, the ion re-implantation regions 111F are formed by ion implantation techniques, the ion re-implantation diffusion regions 111G are formed by scattering in the active region 111 after ion implantation, and the ion re-implantation diffusion regions 111G are adjacent to the word line 120. The implanted ions are of a type opposite to the originally doped ions in the active region 111 such that the concentration of the originally doped ions in the ion re-implantation region 111F and the ion re-implantation diffusion region 111G is lower than the concentration of the originally doped ions in the active region 111, thereby slowing down the electric field strength of the contact window 111D outside the overlapping region of the bit line 140 and reducing or preventing the occurrence of device leakage. In one embodiment, when the substrate 110 is P-type, the active region 111 (i.e., the source/drain regions 111A, 111B, 111C) is heavily doped with N + P of opposite type is implanted through the uncovered region 111E of the contact 111D + After the type ion, an ion re-implantation region 111F is formed, and at the same time, P + The ions are scattered in the source/drain regions 111A, 111B, 111C to form P + Ions of the type ions are re-implanted into the diffusion region 111G. Due to P + Dilution of ions to cause ion re-implantation of N in the region 111F and the region 111G + The doping concentration is reduced to become lightly doped N - An area.
In another embodiment, when the substrate 110 is N-type, the active region 111 (i.e. source/drain regions 111A, 111B, 111C) is heavily doped with P + N of opposite type is implanted through the uncovered region 111E of the contact 111D + After the ion, an ion re-implantation region is formed111F, at the same time, N + The ions are scattered in the source/drain regions 111A, 111B, 111C to form N + Ions of the type ions are re-implanted into the diffusion region 111G. Due to N + Dilution of ions to cause ion re-implantation of region 111F and ion re-implantation of P in diffusion region 111G + The doping concentration is reduced to become lightly doped P - An area.
In one embodiment, the implantation depth of the ion re-implantation region 111F is equal to or greater than the first implantation depth of the top surface of the word line 120 from the upper surface of the substrate 110, but less than the ion implantation depth of the active region 111. In one embodiment, the second buried depth of the top end of the word line conductive layer 122 from the upper surface of the substrate 110 is greater than the first buried depth of the top surface of the word line 120 from the upper surface of the substrate 110, but less than the implantation depth of the ion re-implantation region 111F. In another embodiment, the overlap area of the word line conductive layer 122 and the ion re-implantation region 111F is smaller than the overlap area of the word line conductive layer 122 and the active region 111.
In one embodiment, a protective layer 150 is deposited on the word line 120 and in the area of the active region 111 other than the contact 111D, and in particular, the upper chamber 124 of the word line 120 is also filled with the protective layer 150, and in one embodiment, the protective layer 150 comprises silicon nitride or the like.
In another embodiment, a protective layer 150 is deposited over the entire substrate 110 surface and the protective layer 150 covers the bit lines 140, a capacitor contact plate 160 is formed in the protective layer 150 over the source and drain regions 111B, 111C, the upper end of the capacitor contact plate 160 exposing the protective layer 150 and the lower end being in electrical contact with the source and drain regions 111B, 111C, see fig. 12a, 12B. In one embodiment, the conductive material forming the capacitive contact pad 160 comprises polysilicon, metallic tungsten, or the like.
According to the transistor structure of the semiconductor memory and the manufacturing method thereof, a narrow uncovered region 111E is formed in the contact window 111D in the manufacturing process of the bit line 140, ions are implanted into the source drain region 111A to form the ion re-implantation region 111F and the ion re-implantation diffusion region 111G with low concentration, so that the electric field intensity of the contact window 111D outside the overlapping region of the bit line 140 is slowed down, the purpose of improving electric leakage is achieved, and meanwhile, the influence on a current path and a resistance of a bit line contact is not caused due to the small areas of the ion re-implantation region 111F and the ion re-implantation diffusion region 111G.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (16)
1. A method of fabricating a transistor structure of a semiconductor memory device, comprising:
providing a substrate and forming a plurality of active regions in the substrate;
forming a plurality of embedded word lines in the substrate, wherein each active area is intersected with two word lines;
etching a central region between the two intersecting word lines in the active region of the substrate to form a contact window;
depositing a conductive material on the contact window and the area of the substrate between the active areas;
forming a bit line on the substrate;
etching the conductive material by taking the bit line as a mask to form a bit line contact pad in the contact window, wherein the overlapped area of the bit line and the active area is not completely matched with the contact window in shape and size, so that the bit line contact pad is formed below the area of the bit line covering the active area and is not completely filled in the contact window, and the contact window comprises an area which is not covered by the bit line contact pad and the bit line;
and implanting ions into the active region through the uncovered region of the contact window to form an ion re-implantation region to mitigate the electric field strength of the contact window outside the overlapping region of the bit line.
2. The method of claim 1, wherein the shape of the ion re-implantation region on the active region comprises a triangle.
3. The method of claim 1, wherein the source and drain regions on both sides of the active region are further formed as ion re-implantation diffusion regions adjacent to the word line on sides near the word line.
4. The method of claim 1, wherein the ion re-implantation is of a type opposite to an originally doped ion type in the active region such that the ion re-implantation region has a lower concentration of the originally doped ion than the active region.
5. A method of manufacturing a transistor structure of a semiconductor memory device according to claim 1, 2, 3 or 4, wherein in the step of providing the substrate, an isolation structure is provided in the substrate, the isolation structure being formed between adjacent ones of the active regions.
6. The method of claim 5, wherein the word line is embedded in the substrate in a linear extension and penetrates the active region and the isolation structure between the active regions, and wherein the ion re-implantation region has an implantation depth equal to or greater than a first implantation depth of a top surface of the word line from an upper surface of the substrate but less than an ion implantation depth of the active region.
7. The method of manufacturing a transistor structure of a semiconductor memory device according to claim 6, wherein in the step of forming the bit lines, the bit lines are arranged on the substrate in a waved extension manner, and a length of a section of the bit lines overlapping the isolation structure is greater than twice a length of a section of the bit lines overlapping the active region.
8. The method of manufacturing a transistor structure of a semiconductor memory device according to claim 1, further comprising: after the word lines are formed, a protective layer is deposited on the surface of the active region and the word lines, and an opening groove of the protective layer is formed between the word lines so as to form the contact window of the active region subsequently.
9. A transistor structure of a semiconductor memory device, comprising:
a substrate in which an active region is formed;
a word line buried in the substrate and intersecting the active region;
the active region is provided with a contact window and is positioned between two adjacent word lines;
a bit line contact pad deposited on the contact window;
and a bit line formed on the substrate, the bit line intersecting the active region and being connected to the bit line contact pad at a staggered location, the bit line contact pad being formed under a region of the bit line covering the active region without completely filling the contact window; the active region is also provided with an ion re-implantation region which is positioned in the contact window and does not cover the bit line contact pad and the bit line region so as to slow down the electric field intensity of the contact window outside the overlapping region of the bit line.
10. The transistor structure of claim 9, wherein the contact window is formed by partially etching a middle portion of the active region.
11. The transistor structure of claim 10, wherein source and drain regions on both sides of the active region are further formed as ion re-implantation diffusion regions adjacent to the word line on sides near the word line.
12. A transistor structure of a semiconductor memory according to claim 9, wherein an isolation structure is provided in the substrate, the isolation structure being formed between adjacent active regions.
13. A transistor structure according to any of claims 9 to 12, wherein said word line is embedded in said substrate in a linear extension, and wherein an implantation depth of said ion re-implantation region is equal to or greater than a first implantation depth of a top surface of said word line from an upper surface of said substrate, but less than an ion implantation depth of said active region.
14. The transistor structure of claim 13, wherein the bit lines are arranged in a wavy extension on the substrate such that a section length of the bit lines overlapping on the isolation structure is greater than twice a section length of the bit lines overlapping on the active region.
15. The transistor structure of claim 13, wherein the word line comprises a word line body to form the top surface of the word line and a word line conductive layer surrounding the word line body, a second buried depth of a top end of the word line conductive layer from an upper surface of the substrate being greater than a first buried depth of the top surface of the word line from the upper surface of the substrate but less than an implantation depth of the ion re-implantation region.
16. The transistor structure of claim 15, wherein a overlap area of the word line conductive layer and the ion re-implantation region is smaller than a overlap area of the word line conductive layer and the active region.
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