CN110299324A - The transistor arrangement and its manufacturing method of semiconductor memory - Google Patents
The transistor arrangement and its manufacturing method of semiconductor memory Download PDFInfo
- Publication number
- CN110299324A CN110299324A CN201810241906.0A CN201810241906A CN110299324A CN 110299324 A CN110299324 A CN 110299324A CN 201810241906 A CN201810241906 A CN 201810241906A CN 110299324 A CN110299324 A CN 110299324A
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- Prior art keywords
- active area
- ion
- wordline
- bit line
- substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000005684 electric field Effects 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 25
- 238000002347 injection Methods 0.000 claims description 21
- 239000007924 injection Substances 0.000 claims description 21
- 239000011241 protective layer Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 6
- 238000005253 cladding Methods 0.000 claims description 2
- 230000015654 memory Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 15
- 238000001259 photo etching Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The present invention proposes the transistor arrangement and its manufacturing method of a kind of semiconductor memory, this method comprises: active area and intersecting therewith wordline is formed on the substrate；Contact hole is formed between two wordline and deposits conductive material；Bit line and staggered with active area is formed on the substrate；The conductive material that etching is not covered by bit line forms bit line contact pad；And ion is injected to active area by the uncovered area in contact hole, it forms ion and reinjects region, and reinject diffusion zone close to the side of wordline formation ion using the active area that is scattered in of ion.The present invention injects ion by uncovered area narrow in contact hole, formation ion reinjects region and ion reinjects diffusion zone, under the premise of not influencing the current path and resistance value of bit line contact, the concentration of the original doping of active area is reduced, slow down electric field strength and improves electric leakage.
Description
Technical field
The present invention relates to semiconductor memory technical fields, improve electric leakage more particularly, to using ion implanting scattering
The transistor arrangement and its manufacturing method of semiconductor memory.
Background technique
Traditional semiconductor memory cell is usually by MOS (Metal-Oxide Semiconductor, a metal oxygen
Compound semiconductor) transistor and capacitor constitute, and information is stored on the pole plate of capacitor in a manner of charge.However due to electricity
The contact pole plate of appearance is connected with the source-drain electrode area of transistor, and the PN junction leakage current of source-drain electrode area is easy that capacitor is made to generate electric leakage now
As the information for causing memory cell to store is unstable.The method of inhibition leakage current in background technique is in bit line contacting window
The ion opposite with doping original in source-drain electrode area is injected in region, to reduce the dense of the impurity of original doping in source-drain electrode area
Degree, and then slow down the electric field strength of the PN junction of source-drain electrode area, improve or inhibit the generation of leakage current.But due in bit line contacting window
Ion is injected in region, seriously affects the current path and resistance value in bit line contacting window region below bit line contact.How control bit
The area of line contact hole region ion implanting, eliminate influence of the ion implanting to current path and resistance value below bit line contact at
For a project of the art.
Summary of the invention
The embodiment of the present invention provides a kind of transistor junction for scattering using ion implanting and improving the semiconductor memory of electric leakage
Structure and its manufacturing method are at least provided a kind of beneficial with solving or alleviating one or more technical problems in the prior art
Selection.
In a first aspect, the embodiment of the invention provides a kind of manufacturing method of the transistor arrangement of semiconductor memory, packet
It includes:
Substrate is provided, and forms multiple active areas in the substrate；
The wordline of multiple flush types is formed in the substrate, each active area intersects with two wordline；
The middle section in the active area of the substrate between two wordline of intersection is etched, to form contact
Window；
Conductive material is deposited in the contact hole and the substrate on region between the active area；
Bit line is formed on the substrate；
Using the bit line as conductive material described in mask etching, to form bit line contact pad in the contact hole, wherein
The region that coincides of the bit line and the active area is non-fully matched with the contact hole in shape and size, makes the bit line
Engagement pad is formed in the bit line and covers under the region of the active area and not exclusively fill up the contact hole, the contact hole packet
Include the region for not covering institute's bitline contact pad and the bit line；And
Ion is injected to the active area by the uncovered area of the contact hole, reinjects region to form ion,
To slow down electric field strength of the contact hole outside the overlapping areas of the bit line.
In some embodiments, it includes triangle that the ion, which reinjects shape of the region on the active area,.
In some embodiments, the source-drain electrode area of the active area two sides is more formed as in the side close to the wordline
Ion reinjects diffusion zone, and the ion reinjects diffusion zone and adjoins the wordline.
In some embodiments, the ionic of the kenel of the reflooded ion and original doping in the active area
State original is mixed on the contrary, ion is made to reinject the ion concentration of original doping described in region lower than described in the active area
Miscellaneous ion concentration.
In some embodiments, in the step of providing the substrate, isolation structure is set in the substrate, described
Isolation structure is formed between the adjacent active area.
In some embodiments, the wordline extends straight mode and is embedded in the substrate, and has through described
The isolation structure between source region and the active area, the injection depth that the ion reinjects region, which is equal to, is greater than the word
First length of embedment of upper surface of the top surface of line apart from the substrate, but it is less than the ion implant depth of the active area.
In some embodiments, in the step of forming the bit line, the bit line extension mode wave-shaped is arranged
Over the substrate, and the section length that overlaps on the isolation structure of the bit line is greater than the bit line and overlaps in described has
Twice of section length or more in source region.
In some embodiments, the manufacturing method further include: after forming the wordline, deposit protective layer in described
In surfaces of active regions and the wordline, and the open slot of the protective layer is formed between the wordline, for being subsequently formed
State the contact hole of active area.
Second aspect, the embodiment of the invention provides a kind of transistor arrangements of semiconductor memory, comprising:
Substrate forms active area in the substrate；
Wordline in the substrate with flush type setting, and intersects with the active area；The active area has contact
Window, between the two neighboring wordline；
Bit line contact pad, deposition are formed on the contact hole；And
Bit line is formed on the substrate, and the bit line connect institute's bitline contact with the staggered position of the active area
Pad, institute's bitline contact pad are formed under the region that the bit line covers the active area without being fully filled with the contact hole；
Wherein, the active area also there is ion to reinject region, not cover in the contact hole and the bit line
The region of engagement pad and the bit line, to slow down electric field strength of the contact hole outside the overlapping areas of the bit line.
In some embodiments, the contact hole is formed by the intermediate position of active area described in local etching.
In some embodiments, the source-drain electrode area of the active area two sides is more formed as in the side close to the wordline
Ion reinjects diffusion zone, and the ion reinjects diffusion zone and adjoins the wordline.
In some embodiments, isolation structure is provided in the substrate, the isolation structure is formed in adjacent described
Between active area.
In some embodiments, the wordline extends straight mode and is embedded in the substrate, and the ion is infused again
The injection depth for entering region is equal to the first length of embedment of upper surface of the top surface for being greater than the wordline apart from the substrate, but small
In the ion implant depth of the active area.
In some embodiments, bit line extension mode wave-shaped arranges over the substrate, so that institute's rheme
The section length that line overlaps on the isolation structure is greater than twice of section length that the bit line overlaps on the active area
More than.
In some embodiments, the wordline includes the wordline main body to form the wordline top surface and cladding institute
State the wordline conductive layer of wordline main body, the second length of embedment of upper surface of the top of the wordline conductive layer apart from the substrate
Greater than the first length of embedment of upper surface of the top surface apart from the substrate of the wordline, but it is less than the ion and reinjects region
Injection depth.
In some embodiments, the region that coincides that the wordline conductive layer and the ion reinject region is less than described
The region that coincides of wordline conductive layer and the active area.
The transistor arrangement and its manufacturing method of the semiconductor memory of the embodiment of the present invention, using in bit line manufacturing process
Formed in contact hole narrow uncovered area injected into source-drain electrode area ion formed low concentration ion reinject region
Diffusion zone is reinjected with ion, to slow down electric field strength of the contact hole outside the overlapping areas of bit line, reaches improvement leakage
The purpose of electricity, simultaneously because ion reinject region and ion to reinject diffusion region area narrow, do not cause to bit line contact
Current path and resistance value influence.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings depict only according to the present invention
Disclosed some embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 a is the top view for forming the substrate surface after active area in the substrate of one embodiment of the invention；
Fig. 1 b is the cross-sectional view in Fig. 1 a along line A-A；
Fig. 2 a is the top view of the substrate surface after active section forms isolation structure of one embodiment of the invention；
Fig. 2 b is the cross-sectional view in Fig. 2 a along line A-A；
Fig. 3 a is the top view for forming the substrate surface after wordline in the substrate of one embodiment of the invention；
Fig. 3 b is the cross-sectional view in Fig. 3 a along line B-B；
Fig. 4 a is the vertical view that the substrate surface after protective layer is deposited on active area and wordline of one embodiment of the invention
Figure；
Fig. 4 b is the cross-sectional view in Fig. 4 a along line B-B；
Fig. 5 a is the top view for etching contact hole backsight bottom surface of one embodiment of the invention；
Fig. 5 b is the cross-sectional view in Fig. 5 a along line B-B；
Fig. 6 a is the top view that the substrate surface after conductive material is deposited in contact hole of one embodiment of the invention；
Fig. 6 b is the cross-sectional view in Fig. 6 a along line B-B；
Fig. 7 a in depositing bitlines material and generates bowing for photoetching offset plate figure backsight bottom surface for one embodiment of the invention
View；
Fig. 7 b is the cross-sectional view in Fig. 7 a along line B-B；
Fig. 8 a is the top view of the etching bit line material backsight bottom surface of one embodiment of the present of invention；
Fig. 8 b is the cross-sectional view in Fig. 8 a along line B-B；
Fig. 9 a is that the etching conductive material of one embodiment of the present of invention forms bit line contact pad and ion reinjects region
The top view of backsight bottom surface；
Fig. 9 b is the cross-sectional view in Fig. 9 a along line B-B；
Figure 10 a is that the ion of one embodiment of the present of invention reinjects the top view of backsight bottom surface；
Figure 10 b be Figure 10 a in along line B-B display ion by ion reinject region injection active area and scattering cut open
View；
Figure 10 c is that the formation ion in Figure 10 a along line B-B reinjects the cross-sectional view after diffusion zone；
Figure 11 a is the deposition protective layer of one embodiment of the present of invention and the top view for covering the substrate surface after bit line；
Figure 11 b is the cross-sectional view in Figure 11 a along line B-B；
Figure 12 a is the top view of the formation capacitance contact pole plate backsight bottom surface of one embodiment of the present of invention；
Figure 12 b is the cross-sectional view in Figure 12 a along line B-B.
Drawing reference numeral explanation:
110: substrate；
111: active area；111A, 111B, 111C: source-drain electrode area；
111D: contact hole；111E: the uncovered area of contact hole；
111F: ion reinjects region；111G: ion reinjects diffusion zone；
112: isolation structure；
120: wordline；121: insulating layer；
122: wordline conductive layer；123: wordline main body
The upper chamber of 124 wordline；
130: bit line contact pad；
140: bit line；
150: protective layer；
160: capacitance contact pole plate；
200: conductive material；
300: bit line material；
400: photoetching offset plate figure corresponding with bit line.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be modified by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
It is carried out below with reference to transistor arrangement and its manufacturing method of Fig. 1 a to Figure 12 b to semiconductor memory of the invention
Detailed description.
The manufacturing method of the transistor arrangement for the semiconductor memory that the embodiment of the present invention provides, includes the following steps.
Step S101 provides substrate 110, and multiple active areas 111 are formed in substrate 110, as shown in Fig. 1 a, 1b.Tool
For body, substrate 110 is provided, in one embodiment, substrate 110 is p-type or N-type；Photoresist is coated simultaneously on 110 surface of substrate
Photoetching offset plate figure (not shown) is formed, it is opposite with the doping kenel in substrate 110 to the injection of substrate 110 by photoetching offset plate figure
Doping to form multiple active areas 111, in one embodiment, when substrate 110 is p-type, the doping of injection is N-type
(such as phosphorus, arsenic, antimony), when substrate 110 is N-type, the doping of injection is p-type (such as boron, gallium).The phase each other of active area 111
Between arrange, formed active area array.Fig. 1 a is the lining of one embodiment of the invention formed after active area 111 in substrate 110
The top view on 110 surface of bottom.Fig. 1 b is the cross-sectional view in Fig. 1 a along line A-A, as shown, active area 111 is formed in substrate 110
Surface and not through substrate 110, two active areas 111 are separated.
Step S102, the region that active area 111 is separated in etched substrate 110, referring to fig. 2 a, 2b.Specifically,
110 surface of substrate deposition photoresist simultaneously forms photoetching offset plate figure (not shown), etches active area 111 each other by photoetching offset plate figure
The region of separation, as shown in Figure 2 a.In one embodiment, etching depth is greater than the depth that the doping of active area 111 injects,
B referring to fig. 2.Then, depositing isolation material between active area 111 to form isolation structure 112, as shown in Figure 2 b, in one kind
In embodiment, isolated material includes SiO2。
Step S103 forms the wordline 120 of multiple flush types, referring to Fig. 3 a, 3b in substrate 110.Specifically, serving as a contrast
Multiple groove (not shown) are etched in bottom 110, in one embodiment, the method for etching includes wet etching.In a kind of implementation
In example, the groove extends straight mode and is formed in substrate 110, and through between active area 111 and active area 111 every
From structure 112, the groove is parallel to each other and intersects angled, and each active area 111 and two institutes with active area 111
Groove is stated to intersect and be divided into three source-drain electrode areas 111A, 111B, 111C.Along the inner wall of groove be sequentially depositing insulating layer 121,
Wordline conductive layer 122, seed layer (not shown) and wordline main body 123 remove word using the method for etching to form wordline 120
The upper section of line conductive layer 122, seed layer and wordline main body 123 is to form the upper chamber 124 of wordline 120, such as Fig. 3 a, figure
Shown in 3b.The effect of insulating layer 121 is that the substrate 110 of wordline 120 and surrounding and active area 111 is made to insulate, in a kind of embodiment
In, insulating layer 121 includes silica；The effect of wordline conductive layer 122 is to prevent wordline main body 123 to insulating layer 121, active
The diffusion of the atom of area 111 and substrate 110, in one embodiment, wordline conductive layer 122 include titanium or titanium nitride etc.；Seed layer
As the nuclearing centre of wordline main body 123, for guiding the deposition of subsequent wordline main body 123, in one embodiment, seed layer
Ingredient it is identical as wordline main body 123；The effect of wordline main body 123 is created as the main part of wordline 120, in a kind of implementation
In example, wordline main body 123 is including tungsten etc..
Wordline 120 extends along active area 111 and the alternately arranged direction of isolation structure 112, and with active area 111 and be isolated
Structure 112 intersects, wherein each active area 111 intersects with two wordline 120.
Step S104 deposits protective layer 150 to cover 111 surface of active area and wordline 120 and the top for filling wordline 120
Chamber 124, as shown in Fig. 4 a, Fig. 4 b.The effect of protective layer 150 is to prevent the pollution of impurity and make 111 surface of active area and word
Line 120 top (i.e. wordline conductive layer 122, seed layer and wordline main body 123 top) insulation, in one embodiment, protect
Sheath 150 is including silicon nitride etc..
Step S105 etches the middle section in the active area 111 of substrate 110 between two wordline 120 of intersection
Protective layer 150 is to source-drain electrode area 111A and isolation structure 112, to form the contact hole 111D of perforation, referring to Fig. 5 a and figure
5b.In one embodiment, the side wall of contact hole 111D is not contacted with the side wall of wordline 120, and centre is separated with source-drain electrode area 111A
A part.In addition, as shown, source-drain electrode area 111A's exposed in the bottom of contact hole 111D after etching contact hole 111D
The isolated material of silicon surface layer and isolation structure 112.
Step S106, in contact hole 111D and substrate 110 deposits conductive material on region between active area 111
200, as shown in Fig. 6 a, 6b.The upper surface of conductive material 200 is concordant with protective layer 150.In one embodiment, conductive material
200 include the polysilicon etc. of doping.
Step S107, depositing bitlines material 300 and generation photoetching offset plate figure 400 corresponding with bit line 140.It is specific and
Speech, as shown in Fig. 7 a, 7b, entire substrate 110 surface depositing bitlines material 300 with protective mulch 150 and conductive material
200, and coat photoresist on above-mentioned bit line material 300 and form photoetching offset plate figure 400 corresponding with bit line 140.
Step S108 performs etching bit line material 300 using above-mentioned photoetching offset plate figure 400 and removes the photoetching offset plate figure
400, form multiple bit lines 140.As shown in Fig. 8 a, 8b, it is preferable that the extension mode wave-shaped of bit line 140 is formed in substrate 110
On, it regularly arranges at certain intervals each other, each bit line 140 and multiple active areas 111, wordline 120 and conduction material
Expect that 200 is staggered, and the section length that bit line 140 overlaps on isolation structure 112 overlaps in active area 111 greater than bit line 140
On twice of section length or more so that source-drain electrode area 111A, 111B, 111C of 111 two sides of active area have and bigger appear face
Product, to install capacitance contact pole plate 160.
Step S109 is mask etching conductive material 200 to form bit line contact pad in contact hole 111D with bit line 140
130, referring to Fig. 9 a, 9b.Specifically, being performed etching to the conductive material 200 in contact hole 111D, to remove under bit line 140
Conductive material 200 other than side.Since bit line 140 and active area 111 interlock, the region that coincides of bit line 140 and active area 111 exists
It is non-fully matched with contact hole 111D in shape and size, so that part of the conductive material 200 on active area 111 not quilt completely
Bit line 140 covers, and not covered conductive material 200 is etched away and covers the conductive material 200 below bit line 140 and stayed
Under, to form bit line contact pad 130 under the region that bit line 140 covers active area 111, bit line contact pad 130 is not exclusively filled out
Full contact hole 111D, and the staggered position on active area 111 is connected bit line contact pad 130 with bit line 140.
Meanwhile it is above-mentioned be not etched away by the conductive material 200 on active area 111 that bit line 140 covers after formed and contact
The uncovered area 111E of window 111D, and expose the source-drain electrode area 111A of active area 111.In other words, contact hole 111D is not
Overlay area 111E is formed in contact hole 111D and does not cover the region of bit line contact pad 130 and bit line 140.
Step S110 injects ion into active area 111 by the uncovered area 111E of above-mentioned contact hole 111D, with
The source-drain electrode area 111A of active area 111 forms ion and reinjects region 111F, such as Figure 10 a, 10b, 10c.In one embodiment,
It includes triangle that ion, which reinjects shape of the region 111F on active area 111,.Referring to Figure 10 b, contact hole 111D's is not covered
Dotted arrow in the 111E of region represents the direction of injection ion, in one embodiment, using ion implantation technique (Iron
Implantation injection ion) is carried out.Ion also occurs that scattering (Scattering) when injecting source-drain electrode area 111A, from
And ion is formed in the side of the close wordline 120 of source-drain electrode area 111A, 111B, 111C and reinjects diffusion zone 111G.It is active
Solid arrow vertically downward in area 111 represents the direction of ion implanting, and slanting solid arrow represents ion in source and drain
Scattering direction (not including the incidental solid arrow of appended drawing reference) in polar region 111B, 111C.Figure 10 a, 10c respectively indicate from
Formation ion reinjects region 111F after son injection and ion reinjects the top view and cross-sectional view of diffusion zone 111G.In one kind
In embodiment, ion reinjects diffusion zone 111G and the side wall of wordline 120 mutually adjoins.Ion reinjects region 111F and ion
The formation of diffusion zone 111G is reinjected, electric field strength of the contact hole 111D outside the overlapping areas of bit line 140 can be slowed down.
The injection depth that ion reinjects region 111F is equal to or more than upper table of the top surface of wordline 120 apart from substrate 110
The length of embedment in face, but it is less than the ion implant depth of active area 111.
In addition, it is necessary to explanation, the kenel and the ion kenel phase of original doping in active area 111 of the ion of injection
Instead, so that ion reinjects ion of the ion concentration lower than the original doping in active area 111 of original doping in the 111F of region
Concentration, to slow down electric field strength of the contact hole 111D outside the overlapping areas of bit line 140 and component is reduced or prevented to leak electricity
It generates.
In one embodiment, when substrate 110 is p-type, active area 111 (i.e. source-drain electrode area 111A, 111B, 111C) is
Heavy doping N+Type injects the opposite P of kenel by the uncovered area 111E of contact hole 111D+When type ion, forms ion and infuse again
Enter region 111F, meanwhile, P+Type ion can scatter in source-drain electrode area 111A, 111B, 111C, to form P+Type ion
Ion reinject diffusion zone 111G.Due to P+The dilution of type ion, makes that ion reinjects region 111F and ion reinjects
N in diffusion zone 111G+Type doping concentration reduces, and becomes the N being lightly doped-Region.
In another embodiment, when substrate 110 is N-type, active area 111 (i.e. source-drain electrode area 111A, 111B, 111C)
For heavy doping P+Type injects the opposite N of kenel by the uncovered area 111E of contact hole 111D+When type ion, ion is formed again
Injection zone 111F, meanwhile, N+Type ion can scatter in source-drain electrode area 111A, 111B, 111C, to form N+Type from
The ion of son reinjects diffusion zone 111G.Due to N+The dilution of type ion, makes that ion reinjects region 111F and ion is infused again
Enter the P in diffusion zone 111G+Type doping concentration reduces, and becomes the P being lightly doped-Region.
Due to ion reinject region 111F and ion to reinject diffusion zone 111G range smaller, will not be to bit line 140
The current path and resistance value of the bit line contact (i.e. the contact of bit line engagement pad 130 and source-drain electrode area 111A) of lower section have an impact.
Step S111 deposits protective layer 150 on entire 110 surface of substrate and covers bit line 140, referring to Figure 11 a, 11b.Such as
Shown in Figure 11 b, post-depositional protective layer 150 fills ion and reinjects region 111F.
Step S112, above source-drain electrode area 111B, 111C 150 surface of self-insurance sheath punch to source-drain electrode area 111B and
The surface 111C, and conductive material is deposited to form capacitance contact pole plate 160, referring to Figure 12 a, 12b.As shown in Figure 12b, capacitor connects
It touches pole plate 160 and source-drain electrode area 111B, 111C is in electrical contact, and ion reinjects diffusion zone 111G and is located at capacitance contact pole plate
160 lower section.In one embodiment, the conductive material for forming capacitance contact pole plate 160 includes polysilicon, tungsten etc..
Another aspect of the present invention, the manufacturing method of the transistor arrangement corresponding to semiconductor memory additionally provide half
The embodiment of the transistor arrangement of conductor reservoir.As shown in Figure 10 a, 10c, in one embodiment, semiconductor memory
Transistor arrangement includes substrate 110, wordline 120, bit line contact pad 130, bit line 140 and protective layer 150.
Wherein, multiple source regions 111 are provided in substrate 110, active area 111 is spaced each other, active area array is formed,
Referring to Figure 10 a；Active area 111 is formed in the surface of substrate 110 and not through substrate 110, as shown in figure l0c.In active area 111
Between be formed with isolation structure 112, in one embodiment, isolated material includes SiO2。
Wordline 120 is formed in substrate 110 with embedded mode, and wordline 120 extends straight mode and is formed in substrate 110
In, and through isolation structure 112 between active area 111 and active area 111, wordline 120 it is parallel to each other and with 111 phase of active area
Hand over angled, each wordline 120 intersects with multiple active areas 111, and each active area 111 intersects with two wordline 120
And it is divided into three source-drain electrode areas 111A, 111B, 111C.Wordline 120 from side wall successively include to central axis insulating layer 121,
Wordline conductive layer 122, seed layer (not shown), wordline main body 123, wordline main body 123 form the top surface of wordline 120, and wordline is led
Electric layer 122 coats wordline main body 123；It is more formed with upper chamber 124 at the top position of wordline 120, upper chamber 124 passes through
It etches the upper section of wordline conductive layer 122, seed layer and wordline main body 123 and is formed.In one embodiment, insulating layer
121 include silica, and wordline conductive layer 122 includes titanium or titanium nitride etc., and wordline main body 123 is including tungsten etc., seed layer
It is identical as the material of wordline main body 123.
Source-drain electrode area 111A also has contact hole 111D, and between two neighboring wordline 120, contact hole 111D passes through office
Portion etches source-drain electrode area 111A and is formed.In one embodiment, the side wall of contact hole 111D and the side wall of wordline 120 do not connect
Touching, centre are separated with a part of source-drain electrode area 111A.Bit line contact pad 130, deposition is formed in contact hole 111D, in a kind of reality
It applies in example, bit line contact pad 130 is including polysilicon etc..
The extension mode wave-shaped of bit line 140 is formed on substrate 110, is regularly arranged at certain intervals each other
Column, each bit line 140 and multiple active areas 111 and wordline 120 are staggered, and bit line 140 overlaps in the area on isolation structure 112
Segment length is greater than twice of section length or more that bit line 140 overlaps on active area 111, so that the source and drain of 111 two sides of active area
Polar region 111A, 111B, 111C have bigger displaying area, to install capacitance contact pole plate 160.Bit line contact pad 130 is formed in
Bit line 140 cover active area 111 region under without being fully filled with contact hole 111D, and with bit line 140 on active area 111 phase
Staggered position is connected.
Contact hole 111D also has uncovered area 111E, is located in contact hole 111D and does not cover bit line contact pad
130 and bit line 140 region, ion is injected to active area 111 by the uncovered area 111E of contact hole 111D.
Ion is formed with close to the avris of wordline 120 at active area 111 (i.e. source-drain electrode area 111A, 111B, 111C) to infuse again
Enter region 111F and ion reinject diffusion zone 111G, in one embodiment, ion reinject region 111F be by from
What sub- injection technique was formed, it is by the scattering shape after ion implanting in active area 111 that ion, which reinjects diffusion zone 111G,
At, ion reinjects diffusion zone 111G and adjoins wordline 120.Original doping in the kenel and active area 111 of the ion of injection
Ion kenel on the contrary, making the ion that ion reinjects region 111F and ion reinjects original doping in diffusion zone 111G
Concentration lower than the original doping in active area 111 ion concentration, to slow down contact hole 111D in 140 crossover area of bit line
Overseas electric field strength and the generation for reducing or preventing component to leak electricity.In one embodiment, active when substrate 110 is p-type
Area 111 (i.e. source-drain electrode area 111A, 111B, 111C) is heavy doping N+Type is infused by the uncovered area 111E of contact hole 111D
Enter the opposite P of kenel+After type ion, forms ion and reinject region 111F, meanwhile, P+Type ion source-drain electrode area 111A,
It is scattered in 111B, 111C, forms P+The ion of type ion reinjects diffusion zone 111G.Due to P+The dilution of type ion, makes ion
It reinjects region 111F and ion reinjects N in diffusion zone 111G+Type doping concentration reduces, and becomes the N being lightly doped-Region.
In another embodiment, when substrate 110 is N-type, active area 111 (i.e. source-drain electrode area 111A, 111B, 111C)
For heavy doping P+Type injects the opposite N of kenel by the uncovered area 111E of contact hole 111D+After type ion, ion is formed again
Injection zone 111F, meanwhile, N+Type ion scatters in source-drain electrode area 111A, 111B, 111C, forms N+The ion of type ion is again
Inject diffusion zone 111G.Due to N+The dilution of type ion, makes that ion reinjects region 111F and ion reinjects diffusion zone
P in 111G+Type doping concentration reduces, and becomes the P being lightly doped-Region.
In one embodiment, ion reinject region 111F injection depth be equal to or more than wordline 120 top surface away from
First length of embedment of the upper surface from substrate 110, but it is less than the ion implant depth of active area 111.In one embodiment,
Second length of embedment of upper surface of the top of wordline conductive layer 122 apart from substrate 110 is greater than the top surface of wordline 120 apart from substrate
First length of embedment of 110 upper surface, but it is less than the injection depth that ion reinjects region 111F.In another embodiment
In, wordline conductive layer 122 and ion reinject the region that coincides of region 111F less than wordline conductive layer 122 and active area 111
Coincide region.
In one embodiment, the region in wordline 120 and other than active area 111 is on contact hole 111D is also deposited with
Protective layer 150 is especially also filled with protective layer 150 in the upper chamber 124 of wordline 120, in one embodiment, protection
Layer 150 is including silicon nitride etc..
In another embodiment, matcoveredn 150 is all deposited on entire 110 surface of substrate and protective layer 150 covers position
Line 140 is formed with capacitance contact pole plate 160, capacitance contact pole plate in the protective layer 150 above source-drain electrode area 111B, 111C
Protective layer 150 is exposed in 160 upper end, and lower end and source-drain electrode area 111B, 111C are in electrical contact, referring to Figure 12 a, 12b.In a kind of reality
It applies in example, the conductive material for forming capacitance contact pole plate 160 includes polysilicon, tungsten etc..
The transistor arrangement and its manufacturing method of the semiconductor memory of the embodiment of the present invention, were made using bit line 140
Narrow uncovered area 111E is formed in journey in contact hole 111D and injects ion formation low concentration into source-drain electrode area 111A
Ion reinject region 111F and ion reinjects diffusion zone 111G, to slow down contact hole 111D in bit line 140
Electric field strength outside overlapping areas achievees the purpose that improve electric leakage, simultaneously because ion reinjects region 111F and ion is infused again
Enter that diffusion zone 111G area is narrow, does not cause the influence of the current path and resistance value to bit line contact.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.Moreover, particular features, structures, materials, or characteristics described
It may be combined in any suitable manner in any one or more of the embodiments or examples.In addition, without conflicting with each other, this
The technical staff in field can be by the spy of different embodiments or examples described in this specification and different embodiments or examples
Sign is combined.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic." first " is defined as a result, the feature of " second " can be expressed or hidden
It include at least one this feature containing ground.In the description of the present invention, the meaning of " plurality " is two or more, unless otherwise
Clear specific restriction.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (16)
1. a kind of manufacturing method of the transistor arrangement of semiconductor memory characterized by comprising
Substrate is provided, and forms multiple active areas in the substrate；
The wordline of multiple flush types is formed in the substrate, each active area intersects with two wordline；
The middle section in the active area of the substrate between two wordline of intersection is etched, to form contact hole；
Conductive material is deposited in the contact hole and the substrate on region between the active area；
Bit line is formed on the substrate；
Using the bit line as conductive material described in mask etching, to form bit line contact pad in the contact hole, wherein described
The region that coincides of bit line and the active area is non-fully matched with the contact hole in shape and size, makes institute's bitline contact
Pad is formed in the bit line and covers under the region of the active area and not exclusively fill up the contact hole, and the contact hole includes not
Cover the region of institute's bitline contact pad and the bit line；And
Ion is injected to the active area by the uncovered area of the contact hole, region is reinjected to form ion, to subtract
Delay electric field strength of the contact hole outside the overlapping areas of the bit line.
2. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 1, which is characterized in that it is described from
It includes triangle that son, which reinjects shape of the region on the active area,.
3. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 1, which is characterized in that described to have
The source-drain electrode area of source region two sides is more formed as ion in the side close to the wordline and reinjects diffusion zone, and the ion is infused again
Enter diffusion zone and adjoins the wordline.
4. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 1, which is characterized in that reinject
The ion kenel and original doping in the active area ion kenel on the contrary, reinjecting the ion in region
Ion concentration of the ion concentration of the original doping lower than the original doping in the active area.
5. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 1,2,3 or 4, feature exist
In in the step of providing the substrate, isolation structure is set in the substrate, and the isolation structure is formed in adjacent described
Between active area.
6. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 5, which is characterized in that the word
Line extends straight mode and is embedded in the substrate, and through the isolation junction between the active area and the active area
Structure, the injection depth that the ion reinjects region are equal to the of upper surface of the top surface apart from the substrate greater than the wordline
One length of embedment, but it is less than the ion implant depth of the active area.
7. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 6, which is characterized in that formed
In the step of bit line, the bit line extension mode wave-shaped is arranged over the substrate, and the bit line overlaps in institute
The section length on isolation structure is stated to be greater than twice of section length or more that the bit line overlaps on the active area.
8. the manufacturing method of the transistor arrangement of semiconductor memory according to claim 1, which is characterized in that also wrap
It includes:
After forming the wordline, deposition protective layer is in the surfaces of active regions and the wordline, and between the wordline
The open slot of the protective layer is formed, for being subsequently formed the contact hole of the active area.
9. a kind of transistor arrangement of semiconductor memory characterized by comprising
Substrate forms active area in the substrate；
Wordline in the substrate with flush type setting, and intersects with the active area；The active area has contact hole, position
Between the two neighboring wordline；
Bit line contact pad, deposition are formed on the contact hole；And
Bit line is formed on the substrate, and the bit line connect institute's bitline contact pad, institute with the staggered position of the active area
Bitline contact pad is formed in the bit line and covers under the region of the active area without being fully filled with the contact hole；
Wherein, the active area also there is ion to reinject region, not cover in the contact hole and institute's bitline contact
The region of pad and the bit line, to slow down electric field strength of the contact hole outside the overlapping areas of the bit line.
10. the transistor arrangement of semiconductor memory according to claim 9, which is characterized in that the contact hole passes through
The intermediate position of active area described in local etching and formed.
11. the transistor arrangement of semiconductor memory according to claim 10, which is characterized in that the active area two sides
Source-drain electrode area be more formed as ion in the side close to the wordline and reinject diffusion zone, the ion reinjects diffusion region
The wordline is adjoined in domain.
12. the transistor arrangement of semiconductor memory according to claim 9, which is characterized in that be arranged in the substrate
There is isolation structure, the isolation structure is formed between the adjacent active area.
13. according to the transistor arrangement of the described in any item semiconductor memories of claim 9 to 12, which is characterized in that described
Wordline extends straight mode and is embedded in the substrate, and the injection depth that the ion reinjects region, which is equal to, is greater than the word
First length of embedment of upper surface of the top surface of line apart from the substrate, but it is less than the ion implant depth of the active area.
14. the transistor arrangement of semiconductor memory according to claim 13, which is characterized in that the bit line is in wave
Shape extends mode and arranges over the substrate, so that the bit line overlaps in the section length on the isolation structure greater than described
Bit line overlaps in twice of section length or more on the active area.
15. the transistor arrangement of semiconductor memory according to claim 13, which is characterized in that the wordline includes using
To form the wordline main body of the wordline top surface and the wordline conductive layer of the cladding wordline main body, the wordline conductive layer
Second length of embedment of upper surface of the top apart from the substrate is greater than upper surface of the top surface of the wordline apart from the substrate
The first length of embedment, but be less than the ion and reinject the injection depth in region.
16. the transistor arrangement of semiconductor memory according to claim 15, which is characterized in that the wordline conductive layer
The region that coincides for reinjecting region with the ion is less than the region that coincides of the wordline conductive layer and the active area.
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Cited By (1)
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| WO2022033164A1 (en) * | 2020-08-14 | 2022-02-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for semiconductor structure |
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