JP6524279B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor device including a trench gate type MOSFET and a method of manufacturing the same.

As an example of a trench gate type MOSFET, for example, the semiconductor device of Patent Document 1 includes an n ⁻ -type first base layer in which a gate trench is formed, a gate insulating film formed on the inner surface of the gate trench, and a gate insulating film. An inner-filled gate electrode, an interlayer insulating film formed to cover the gate electrode, and a p ^- type first layer formed on the surface of the n ⁻ -type first base layer and shallower than the bottom of the gate trench A second base layer, an n ⁺ -type source layer formed on the surface of the p-type second base layer, and a self-aligned contact trench formed through the n ⁺ -type source layer and into the p-type second base layer; is connected to the p-type second base layer at the bottom of the self-aligned contact grooves in the side of the self-aligned contact trenches, a source electrode connected to the n ⁺ -type source layer, n ^- -type first It includes a n ⁺ -type drain layer formed on the back surface of the over scan layer and a drain electrode formed on the n ⁺ -type drain layer.

JP, 2010-62477, A JP, 2010-021176, A

A semiconductor device according to the present invention includes a semiconductor layer in which a gate trench is formed, and a source region of a first conductivity type which is formed to be exposed on the surface side of the semiconductor layer and which forms a part of the side surface of the gate trench. the so formed as to the source region in contact with the source region to the back surface side of the semiconductor layer, a second conductivity type channel region which forms part of the side surface of the gate trench, a surface of said semiconductor layer A channel contact region of a second conductivity type formed in the channel region so as to be exposed to the side, and having a first end and a second end in the width direction along the surface of the semiconductor layer; The drain region of the first conductivity type formed on the back surface side of the semiconductor layer to be in contact with the channel region and forming the bottom surface of the gate trench, and the inside of the gate trench And a gate electrode embedded inside the gate insulating film in the gate trench, the channel region is formed along the side surface of the gate trench, and a channel is formed at the time of operation. a channel portion formed, before SL protrudes to the rear surface side to the end of the channel portion of the back surface side of the semiconductor layer, the lower position of the first end and the second end portion of said channel contact region And two convex portions in the form of a paraboloid in cross section each having a first top and a second top .

FIG. 1 is a schematic plan view of a trench gate type MOS transistor according to an embodiment of the present invention. FIG. 2 is a bird's-eye view of the trench gate type MOS transistor of FIG. 1 and shows a cross section taken along line II-II of FIG. 3A is a view showing a part of the manufacturing process of the trench gate type MOS transistor of FIG. 2; FIG. FIG. 3B is a view showing the next process of FIG. 3A. FIG. 3C is a view showing the next process of FIG. 3B. FIG. 3D is a view showing the next process of FIG. 3C. FIG. 3E is a view showing the next process of FIG. 3D. FIG. 3F is a view showing the next process of FIG. 3E. FIG. 3G is a view showing the next process of FIG. 3F. FIG. 3H is a view showing the next process of FIG. 3G. FIG. 3I is a view showing the next process of FIG. 3H. FIG. 3J is a view showing the next process of FIG. 3I. 4 (a) to 4 (d) are diagrams showing a modification of the ion implantation method of FIG. 3G, and FIG. 4 (a) shows one-stage injection, and FIG. 4 (b) to FIG. An example is shown respectively. FIG. 5 is a graph showing the relationship between the dose of B11 ions and the breakdown voltage. FIG. 6 is a view showing a modified example of the convex portion of the trench gate type MOS transistor of FIG. FIG. 7 is a view for explaining an ion implantation method when forming the convex portion of FIG. FIG. 8 is a diagram showing a first modification of the arrangement of unit cells of the trench gate type MOS transistor of FIG. FIG. 9 is a diagram showing a second modification of the arrangement of unit cells of the trench gate type MOS transistor of FIG. FIG. 10 is a schematic plan view of a MOS transistor according to an embodiment of the reference example. 11 is a bird's-eye view of the MOS transistor of FIG. 10, and shows a cross section taken along line XI-XI of FIG. FIG. 12A is a view showing a part of the manufacturing process of the MOS transistor of FIG. FIG. 12B is a view showing the next process of FIG. 12A. FIG. 12C is a view showing the next process of FIG. 12B. FIG. 12D is a view showing the next process of FIG. 12C. FIG. 12E is a view showing the next process of FIG. 12D. FIG. 12F is a view showing the next process of FIG. 12E. FIG. 12G is a view showing the next process of FIG. 12F. FIG. 12H is a view showing the next process of FIG. 12G. 13 (a) and 13 (b) show the on and off states of the MOS transistor in FIG. 11, and FIG. 13 (a) shows the on state and FIG. 13 (b) shows the off state. . FIG. 14 is a diagram showing a first modification of the arrangement of unit cells of the MOS transistor of FIG. FIG. 15 is a diagram showing a second modification of the arrangement of unit cells of the MOS transistor of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
FIG. 1 is a schematic plan view of a trench gate type MOS transistor according to an embodiment of the present invention. FIG. 2 is a bird's-eye view of the trench gate type MOS transistor of FIG. 1 and shows a cross section taken along line II-II of FIG.
Referring to FIG. 1, a MOS transistor 1 as a semiconductor device is a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a plurality of stripe-shaped unit cells 2 arranged in parallel to one another. Each unit cell 2 is partitioned by the striped gate trenches 3 and the distance between adjacent gate trenches 3 (trench pitch P) is, for example, 0.9 μm to 1.5 μm. Further, in each unit cell 2, one long (long in plan view) contact trench 4 extending from one end in the longitudinal direction toward the other end of the unit cell 2 is formed in each unit cell 2.

Next, referring to FIG. 2, MOS transistor 1 is provided with a Si substrate 5 of n ⁺ type (for example, concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ⁻³ ). The Si substrate 5 functions as a drain of the MOS transistor 1. The n-type impurities include phosphorus (P), arsenic (As), and the like. same as below.
On the surface 6 (upper surface) of the Si substrate 5, an n ⁻ -type (for example, a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁵ cm ⁻³ ) Si epitaxial layer 8 having a lower concentration than the Si substrate 5 is stacked There is. The thickness of the Si epitaxial layer 8 as a semiconductor layer is, for example, 3 μm to 10 μm.

In the Si epitaxial layer 8, gate trenches 3 having side surfaces 11 and bottom surfaces 12 dug down from the surface 9 toward the Si substrate 5 are formed in a stripe shape. As a result, a plurality of stripe-shaped unit cells 2 partitioned by the side surfaces 11 of the stripe-shaped gate trenches 3 are formed in the Si epitaxial layer 8.
The depth _{D 1} of the gate trench 3 as measured from the surface 9 of the Si epitaxial layer 8 is, for example, a 1.0Myuemu～1.5Myuemu, specifically a 1.0 .mu.m.

Around the gate trench 3 in the Si epitaxial layer 8, an n ⁺ -type source region 13 and a p ⁻ -type (for example, a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ ) channel region 14 are formed. The layers 8 are formed in this order from the side close to the surface 9. The channel region 14 contains, for example, boron (B), aluminum (Al) or the like as a p-type impurity. same as below.

The source region 13 is formed in the surface layer portion of each unit cell 2 so as to be exposed to the surface 9 of the Si epitaxial layer 8 and to form an upper portion (a part) of the side surface 11 of the gate trench 3. The thickness T ₁ of the source region 13 along the direction from the surface 9 toward the Si substrate 5 is, for example, 0.2 μm to 0.4 μm. When the thickness is defined in the following description, it refers to the thickness along the direction from the surface 9 of the Si epitaxial layer 8 to the Si substrate 5 unless otherwise noted.

Channel region 14 forms a lower portion (a part) of side surface 11 of gate trench 3 so as to be in contact with source region 13 on the side of Si substrate 5 with respect to source region 13 (the back surface 10 side of Si epitaxial layer 8). It is formed to be.
On the other hand, the region on the Si substrate 5 side with respect to the channel region 14 in the Si epitaxial layer 8 is an n ⁻ -type drain region 15 in which the state after the epitaxial growth is maintained. The drain region 15 is in contact with the channel region 14 on the side of the Si substrate 5 with respect to the channel region 14, and forms the bottom surface 12 of the gate trench 3.

  A gate insulating film 16 is formed on the inner surface of the gate trench 3 so as to cover the entire area. Then, in the gate trench 3, the gate electrode 17 is buried in the gate trench 3 by embedding polysilicon doped with n-type impurities at a high concentration inside the gate insulating film 16. Thus, a vertical MOS transistor 1 structure is formed in which source region 13 and drain region 15 are spaced apart from each other via channel region 14 in the vertical direction perpendicular to surface 9 of Si epitaxial layer 8.

  In each unit cell 2, a contact trench 4 is formed which penetrates the source region 13 from the surface 9 of the Si epitaxial layer 8 and the deepest portion reaches the channel region 14. The opening width W of the contact trench 4 is constant in the depth direction, and is, for example, 0.2 μm to 0.5 μm. The source region 13 is exposed on the side surface 18 of the contact trench 4, and the channel region 14 is exposed on the bottom surface 19 of the contact trench 4.

A channel contact region 20 of p ⁺ type (for example, a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ ) is formed in the channel region 14 exposed to the bottom surface 19 of the contact trench 4. The channel contact region 20 is formed in a straight line on the entire bottom surface 19 of the contact trench 4 along the longitudinal direction of the contact trench 4.
An interlayer insulating film 21 is formed on the Si epitaxial layer 8. The interlayer insulating film 21 is formed with a contact hole 22 exposing the contact trench 4.

  Although not shown, a source electrode is formed on interlayer insulating film 21, and this source electrode is connected to all unit cells 2 (source region 13 and channel contact region) via each contact trench 4. 20) collectively. That is, the source electrode is a common wiring to all unit cells 2. In addition, a drain electrode is formed on the back surface 7 of the Si substrate 5 so as to cover the entire area. The drain electrode is a common electrode for all unit cells 2.

In this embodiment, in each unit cell 2, the portion directly below the contact trench 4 of the channel region 14 protrudes (raises) in a mountain shape in a direction away from the channel contact region 20.
Specifically, channel region 14 has both ends near channel portion 23 of channel region 14 in which the channel is formed when MOS transistor 1 operates, and the lower position of the central portion in the width direction of bottom surface 19 of contact trench 4 from both ends. It protrudes in the shape of a parabola drawn so that one peak (apex 25) may come to. Thus, the channel region 14 has, as a portion partitioned by the parabola, a convex portion 24 protruding toward the back surface 10 with respect to the end of the channel portion 23 on the back surface 10 side of the Si epitaxial layer 8 .

The top 25 (peak of the parabola) of the convex portion 24 is located on the back surface 10 side of the Si epitaxial layer 8 with respect to the bottom surface 12 of the gate trench 3 within a range not contacting the Si substrate 5 (that is, the gate trench 3) and is formed in a straight line along the contact trench 4). In addition, the conductivity type of the convex portion 24 is the same p ⁻ type (for example, the concentration is 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ ) same as that of the channel region 14, and the impurity concentration is p ⁺ type (for example, The concentration is preferably 1/100 or less of the channel contact region 20 of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ .

Further, in the channel region 14, the thickness T ₂ of the channel portion 23 is, for example, 0.5 μm to 0.9 μm, and specifically, 0.8 μm. The thickness _{T 3} until the top 25 of the convex portion 24 is, for example, a 1.0Myuemu～1.6Myuemu, specifically a 1.4 [mu] m.
3A to 3J are diagrams showing a part of the manufacturing process of the trench gate type MOS transistor of FIG. 2 and showing a cut surface at the same position as that of FIG.

In order to manufacture the MOS transistor 1, as shown in FIG. 3A, a CVD (Chemical Vapor Deposition: chemical vapor deposition) method, an LPE (Liquid Phase Epitaxy: liquid phase epitaxy) method, an MBE (Molecular Beam Epitaxy: molecular beam epitaxy). Si crystal is grown on the surface 6 of the Si substrate 5 while doping n-type impurities by the epitaxial growth method such as the. Thus, the n ⁻ -type Si epitaxial layer 8 (drain region 15) is formed on the Si substrate 5. Next, p-type impurities and n-type impurities are sequentially implanted toward the surface 9 of the Si epitaxial layer 8. After implantation, annealing is performed (for example, at 900 ° C. to 1000 ° C., for 10 minutes to 30 minutes) to activate each implanted impurity to simultaneously form the channel region 14 and the source region 13. Next, for example, a SiO ₂ film 26 is formed on the surface 9 of the Si epitaxial layer 8 by the CVD method, and an SiN film 27 is formed on the SiO ₂ film 26 to form the SiO ₂ film 26 and the SiN film 27. A hard mask 28 composed of a two-layer film is formed. The thickness of the SiO ₂ film 26 is, eg, 50 Å to 100 Å, and the thickness of the SiN film 27 is, eg, 1000 Å to 1500 Å.

Next, as shown in FIG. 3B, the Si epitaxial layer 8 is etched using the hard mask 28. Thereby, the Si epitaxial layer 8 is dry etched from the surface 9 to form the gate trench 3. At the same time, a plurality of unit cells 2 are formed in the Si epitaxial layer 8.
Next, as shown in FIG. 3C, gate insulating film 16 is formed on the inner surface (side surface 11 and bottom surface 12) of gate trench 3 by thermal oxidation (for example, 10 minutes to 30 minutes at 850.degree. C. to 950.degree. C.). Form

  Next, as shown in FIG. 3D, doped polysilicon (electrode material) is deposited from above the Si epitaxial layer 8 by, eg, CVD. The deposition of polysilicon continues until at least the surface 9 of the Si epitaxial layer 8 is hidden. Thereafter, the deposited polysilicon is etched back until the etch back surface is flush with the surface 9 of the Si epitaxial layer 8. Thereby, gate electrode 17 made of polysilicon remaining in gate trench 3 is formed.

Next, as shown in FIG. 3E, for example, SiO ₂ (insulating material) is deposited from above the Si epitaxial layer 8 by the CVD method to form the interlayer insulating film 21.
Next, as shown in FIG. 3F, contact holes 22 are formed in the interlayer insulating film 21 by dry etching, for example. After contact hole 22 is formed, exposed Si epitaxial layer 8 is etched using interlayer insulating film 21 as a mask. Thereby, the Si epitaxial layer 8 is dry etched from the surface 9, and the contact trench 4 is formed in a self-aligned manner with the interlayer insulating film 21.

Next, as shown in FIG. 3G, an impurity (B11 ion) is made to enter in a direction perpendicular to the bottom surface 12 of the contact trench 4 to form Si at the interface 29 between the channel region 14 and the drain region 15. One stage of impurity implantation is performed at a depth position on the surface 9 side of the epitaxial layer 8 (near the interface 29 in the channel region 14). The implantation energy of impurity ions is, for example, 100 keV to 140 keV, preferably about 140 keV. The dose of impurity ions is, for example, 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , preferably 6 × 10 ¹² cm ⁻² to 8 × 10 ¹² cm ⁻² .

After implantation, annealing (for example, at 900 ° C. to 950 ° C. for 0.5 minutes to 1 minute) diffuses / activates the implanted p-type impurity, as shown in FIG. Fourteen convex portions 24 are formed.
Next, as shown in FIG. 3I, impurities (BF ₂ ions) are injected in a direction perpendicular to the bottom surface 12 of the contact trench 4 at an implantation energy of about 40 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² As a result, one stage of impurity implantation is carried out at a depth position near the bottom surface 12 in the channel region 14.

After the implantation, annealing (for example, at 900 ° C. to 950 ° C. for 0.5 minutes to 1 minute) diffuses and activates the implanted p-type impurity, as shown in FIG. Region 20 is formed.
Thereafter, a source electrode (not shown), a drain electrode (not shown) and the like are formed to obtain the MOS transistor 1 shown in FIG.

  As described above, according to this embodiment, a portion of the channel region 14 has the vicinity of the channel portion 23 of the channel region 14 at both ends, and one peak at a position below the central portion in the width direction of the bottom surface 19 of the contact trench 4 from the both ends. It protrudes as a convex part 24 in the shape of a parabola drawn so that it may come. Thus, the area of the pn junction interface can be made larger than that of the conventional structure in which the depth from the surface 9 of the Si epitaxial layer 8 to the interface (pn junction interface) between the channel region 14 and the drain region 15 is constant. It can be enlarged without affecting the channel characteristic of 1. That is, since only the portion immediately below the contact trench 4 of the channel region 14 is protruded without changing the length (channel length) of the channel portion 23, there is almost no influence on the channel characteristics. Therefore, the area of the depletion layer extending from the pn junction also increases, so that the depletion layer receives a voltage in a large area. As a result, the voltage received per unit area of the depletion layer can be reduced.

  Therefore, the amount L of protrusion (for example, 0.2 μm to 0.1 μm in this embodiment) of gate trench 3 to the back surface 10 side of Si epitaxial layer 8 with respect to the interface between channel portion 23 and drain region 15 is small. Even if the breakdown voltage can not be ensured only by the depletion layer extending from the interface of the small area between the gate insulating film 16 and the drain region 15 (the gate trench 3 is shallow), the large depletion layer is present near the convex portion 24 of the channel region 14 As it exists, the breakdown voltage of the MOS transistor 1 as a whole can be improved.

Therefore, the gate trench 3 can be made shallow to reduce the facing area between the gate electrode 17 and the drain region 15, and the capacitance between the gate and the drain can be reduced while sufficiently maintaining the withstand voltage between the source and the drain.
Moreover, since the convex portion 24 of the channel region 14 protrudes in the direction away from the channel contact region 20, the contact between the channel contact region 20 and the depletion layer extending from the interface between the convex portion 24 and the drain region 15 is prevented. Can. Therefore, the fall of the proof pressure resulting from both contact can be avoided.

  Further, such a convex portion 24 is an impurity toward the bottom surface 12 of the contact trench 4 which is lowered by one step with respect to the surface 9 of the Si epitaxial layer 8 by using the conventional ion implantation (ion implantation) technology. It can be easily formed by injecting ions. Furthermore, since the projection 24 can be formed by injecting impurity ions perpendicularly to the bottom surface 12 of the contact trench 4, precise angle adjustment is not required at the time of impurity ion implantation, and switching of the implantation angle is performed. Is not necessary.

Note that the ion implantation method and implantation depth for forming the convex portion 24 are changed according to the shape and depth of the gate trench 3 and the shape and size of the impurity regions such as the source region 13 and the channel region 14. be able to.
For example, as shown in FIG. 4A, the impurity is located at a depth position on the back surface 10 side (near the interface 29 in the drain region 15) of the Si epitaxial layer 8 with respect to the interface 29 between the channel region 14 and the drain region 15. Can be injected one stage.

  Further, as shown in FIG. 4B, by changing the implantation energy in the range of 80 keV to 180 keV, some of the implantation depths of the impurity ions (B11 ions) are on the surface 9 side of the Si epitaxial layer 8, Impurity ions are multi-stagely implanted in multiple stages such that the region defined by the implanted portion straddles the surface 29 side and the back surface 10 side of the Si epitaxial layer 8 with respect to the interface 29 so that the rest is on the back surface 10 side. It can also be done.

  Furthermore, in the case of employing multistage implantation, as shown in FIG. 4C, the impurity ions are implanted so that the implantation depth of all the impurity ions is on the back surface 10 side of the Si epitaxial layer 8 with respect to the interface 29. Alternatively, as shown in FIG. 4D, impurity ions are implanted such that the implantation depth of all the impurity ions is on the surface 9 side of the Si epitaxial layer 8 with respect to the interface 29. May be

As described above, the convex portions 24 having various shapes can be formed by selecting the ion implantation method such as single-stage and multi-stage or the ion implantation depth. Therefore, the convex portion 24 having an appropriate shape can be formed in accordance with the shape and depth of the gate trench 3 and the shape and size of the impurity region such as the source region 13 and the channel region 14.
In addition, the breakdown voltage between the drain and the source can be improved by setting the dose amount of the impurity (B11 ion) in the range of 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² . Specifically, as shown in FIG. 5 (implantation energy = 140 keV), the breakdown voltage is set to 36 V or more when the dose of B11 ion is in the range of 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² We were able to.

Moreover, the shape of the convex part 24 does not need to be a shape divided by one parabola in cross sectional view, for example, may be a shape divided by two parabola.
Specifically, as in the convex portion 31 of the channel region 30 in FIG. 6, the vicinity of the channel portion 23 is at both ends, and the lower end of the bottom surface 19 of the contact trench 4 in the width direction It is preferable to project two parabolic projections drawn so that the peaks (tops 32) come one by one. In this case, the top portions 32 of the respective convex portions 31 are linearly arranged in parallel to one another along the contact trenches 4. In addition, it is preferable that one convex portion 31 and the other convex portion 31 be axisymmetrical with a vertical line passing through the widthwise central portion of the bottom surface 19 of the contact trench 4 as the axis of symmetry s. The opposite top portion 33 is preferably located on the back surface 10 side of the Si epitaxial layer 8 with respect to the bottom surface 12 of the gate trench 3 (that is, at a deeper position than the bottom surface 12 of the gate trench 3).

Then, the convex portion 31 of FIG. 6, for example, in place of the FIG. 3G step, an implantation angle theta ₁ which is inclined by 7 ° to 14 ° to the bottom surface 12 of the contact trench 4, the width direction end of the contact trench 4 The first step of implanting impurity ions toward the portion, and the implantation direction of impurity ions in the first step at an implantation angle θ ₂ inclined at 7 ° to 14 ° with respect to the bottom surface 12 of the contact trench 4 The second step of implanting impurity ions toward the other end in the width direction of the contact trench 4 can be performed.

According to this method, at the time of transition from the first step to the second step, switching of the implantation angle of impurity ions (θ ₁ → θ ₂ ) is necessary, but the convex portion 31 has a plurality of peak portions 32 (peaks). Because of this, the area of the interface between the convex portion 31 and the drain region 15 can be further increased. As a result, the voltage received per unit area of the depletion layer can be further reduced.
Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms.

For example, the arrangement form of the unit cells 2 does not have to be in the form of stripes, and may be in the form of a matrix as shown in FIG. 8 or in a zigzag form as shown in FIG.
In addition, the shape of each unit cell 2 is not limited to the stripe shape (FIG. 1) and the quadrangular prisms (FIG. 8 and FIG. 9), for example, other polygonal prisms such as triangular prisms, pentagonal prisms and hexagonal prisms. Good.
Further, in the MOS transistor 1, a configuration in which the conductivity type of each semiconductor portion is inverted may be employed. For example, in the MOS transistor 1, the p-type portion may be n-type and the n-type portion may be p-type.

Also, instead of the Si epitaxial layer 8, for example, a SiC epitaxial layer can be used.
Further, the convex portion of the channel region does not have to be directly under the contact trench 4 like the convex portions 24 and 31 and can be formed in various places without affecting the channel characteristics of the MOS transistor 1 .

In addition, various design changes can be made within the scope of matters described in the claims.
Also, features extracted from the description of this specification and the drawings are shown below.
For example, the semiconductor device includes a semiconductor layer in which a gate trench is formed, and a source region of a first conductivity type which is formed to be exposed on the surface side of the semiconductor layer and which forms a part of the side surface of the gate trench. A channel region of a second conductivity type formed on the back surface side of the semiconductor layer with respect to the source region so as to be in contact with the source region and forming a part of the side surface of the gate trench A drain region of a first conductivity type formed on the back surface side of the semiconductor layer to be in contact with the channel region and forming a bottom surface of the gate trench; a gate insulating film formed on an inner surface of the gate trench; And a gate electrode buried inside the gate insulating film in the gate trench, and the channel region extends along the side surface of the gate trench. Is formed, including a channel portion in which a channel is formed during operation, the convex portion protruding to the rear side against the end of the channel portion of the back surface side of the semiconductor layer.

  According to this configuration, a portion of the channel region protrudes as a convex portion on the back surface side of the semiconductor layer at a portion different from the portion (channel portion) in which the channel is formed during operation. Thus, the area of the pn junction interface affects the channel characteristics of the semiconductor device, as compared to the conventional structure in which the depth from the surface of the semiconductor layer to the interface (pn junction interface) between the channel region and the drain region is constant. Can be enlarged without giving Therefore, the area of the depletion layer extending from the pn junction also increases, so that the depletion layer receives a voltage in a large area. As a result, the voltage received per unit area of the depletion layer can be reduced.

  Therefore, the amount of protrusion of the gate trench to the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region is small (the gate trench is shallow), and the depletion layer extends from the interface with a small area between the gate insulating film and the drain region. Even when the breakdown voltage can not be ensured only by this, a depletion layer having a large area is present near the convex portion of the channel region, so that the breakdown voltage of the entire semiconductor device can be improved.

Therefore, the gate trench can be made shallow to reduce the facing area between the gate electrode and the drain region, and the capacitance between the gate and the drain can be reduced, while sufficiently maintaining the withstand voltage between the source and the drain.
In the semiconductor device, a contact trench which penetrates the source region from the surface of the semiconductor layer and whose deepest portion reaches the channel region, and a channel contact region of a second conductivity type formed on the bottom surface of the contact trench It is preferable that the convex portion be formed immediately below the channel contact region.

  In the semiconductor device having such a configuration, for example, a source region of the first conductivity type formed to be exposed to the front side, and a second source region formed on the back side with respect to the source region to be in contact with the source region. The source region and the channel region are penetrated to a semiconductor layer having a channel region of the conductivity type and a drain region of the first conductivity type formed on the back surface side to be in contact with the channel region with respect to the channel region. Forming a gate electrode by forming a gate trench where the deepest portion reaches the drain region, forming a gate insulating film on the inner surface of the gate trench, and embedding an electrode material inside the gate insulating film Forming a contact trench which penetrates the source region and whose deepest portion reaches the channel region in the semiconductor layer. And implanting ions of a second conductivity type so as to reach the vicinity of the interface between the channel region and the drain region through the bottom of the contact trench, so that the side surface of the gate trench is directly below the contact trench. Forming a convex portion protruding toward the back surface side with respect to the end portion on the back surface side of the semiconductor layer of the channel portion of the channel region formed along the bottom surface, and the bottom surface of the contact trench of the semiconductor layer By implanting ions of the second conductivity type in the vicinity, the semiconductor device can be manufactured by a method of manufacturing a semiconductor device including the step of forming a channel contact region in the channel region.

  According to this method, by using the conventional ion implantation (ion implantation) technique, the second conductivity type ions are made to be incident toward the bottom of the contact trench which is lowered by one step with respect to the surface of the semiconductor layer. The protrusion can be easily formed in the channel region. Note that, depending on the type of material of the semiconductor layer, annealing may be performed after the implantation of the second conductivity type ions to diffuse the second conductivity type ions into the semiconductor layer. Such diffusion can be similarly performed when forming the channel contact region.

In addition, since the convex portion to be formed protrudes in the direction away from the channel contact region toward the back surface side of the semiconductor layer, contact between the depletion layer and the channel contact region extending from the interface between the convex portion and the drain region is prevented. can do. Therefore, the fall of the proof pressure resulting from both contact can be avoided.
In this case, the top of the convex portion directly below the channel contact region may be formed along the lower position of the widthwise central portion of the bottom surface of the contact trench.

The semiconductor device having such a configuration may be manufactured, for example, by performing the step of vertically implanting the second conductivity type ion vertically to the bottom surface of the contact trench in the method of manufacturing the semiconductor device. it can.
According to this method, precise angle adjustment is not required at the time of implantation of the second conductivity type ions, and switching of the implantation angle is not necessary. Since it is good, a convex part can be formed more easily.

On the other hand, the top of the convex portion immediately below the channel contact region may be formed along the lower position of the widthwise end of the bottom surface of the contact trench.
The semiconductor device having such a configuration is manufactured, for example, by executing the step of obliquely implanting the second conductivity type ions at an implantation angle inclined to the bottom surface of the contact trench in the method of manufacturing the semiconductor device. can do.

When the tops of the protrusions are formed along the lower position of the widthwise end of the bottom of the contact trench, in particular, a plurality of tops formed parallel to each other along the lower positions of the widthwise both ends of the bottom Is preferred. That is, it is preferable that the convex portion protrudes so as to have a plurality of peaks (peaks) instead of a single peak (peak).
In the semiconductor device having such a configuration, a first step of implanting the second conductivity type ion toward one end in the width direction of the bottom surface of the contact trench when obliquely implanting the second conductivity type ion, and Performing a second step of implanting second conductivity type ions in a direction intersecting the incident direction of the second conductivity type ions in the first step toward the other widthwise end of the bottom surface of the contact trench; It can be manufactured by

According to this method, it is necessary to switch the implantation angle of the second conductivity type ion at the transition from the first step to the second step, but since the convex portion has a plurality of peaks (peaks), the convex portion and The area of the interface with the drain region can be further increased. As a result, the voltage received per unit area of the depletion layer can be further reduced.
Further, in the semiconductor device, it is preferable that a top portion of the convex portion is located on the back surface side of the semiconductor layer with respect to the bottom surface of the gate trench, and the impurity concentration of the convex portion is the channel contact Preferably, it is 1/100 or less of the concentration of the region. When the impurity concentration of the convex portion satisfies the above condition, the withstand voltage can be further improved.

The semiconductor layer may be made of a Si semiconductor layer.
Further, in the method of manufacturing the semiconductor device, the step of forming the convex portion includes a one-step implantation step of implanting the second conductivity type ion at a predetermined depth from the bottom surface of the contact trench. Alternatively, the method may include a multistage implantation process of implanting the ions of the second conductivity type over a plurality of stages to a predetermined depth from the bottom surface of the contact trench by changing the implantation energy.

Furthermore, in the one-step implantation step, the second conductivity type ion is implanted at any depth position on the front surface side and the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. It is also good.
In the multi-stage implantation step, a region defined by a plurality of stages of implantation portions such that some of the implantation depth of the second conductivity type ion is on the front surface side of the semiconductor layer and the rest is on the back surface side. Alternatively, ions of the second conductivity type may be implanted so as to straddle the front surface side and the rear surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. Further, the second conductivity type ions are implanted so that the implantation depth of all the second conductivity type ions is on the front surface side or the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. It may be injected.

As described above, convex portions with various shapes can be formed by selecting the ion implantation method in one or more stages and the ion implantation depth. Therefore, a convex portion having an appropriate shape can be formed in accordance with the shape and depth of the gate trench and the shape and size of the impurity region such as the source region and the channel region.
<Invention according to reference example>
(Background art of reference example)
For example, the semiconductor device of Patent Document 2 is known as an example of the MOSFET.

The semiconductor device can be a p-channel power MOSFET (metal-oxide-semiconductor field-effect transistor) including a trench gate. The semiconductor device includes a semiconductor substrate including ap ⁺ -type silicon substrate, a p-type semiconductor layer formed thereon, and an n-type channel layer formed thereon.
The semiconductor device further includes an n ⁺ -type body region formed on the surface of the semiconductor substrate on the channel layer, and a p ⁺ -type source region surrounding four sides of the body region in plan view. The semiconductor device is formed on the gate trench which penetrates the channel layer and reaches the p-type semiconductor layer, the gate oxide film formed on the side surface of the gate trench, and the bottom of the gate trench A thick film oxide film having a large thickness and a gate electrode formed on the gate oxide film and the thick oxide film in the gate trench and filling the gate trench are included.

In the semiconductor device, a source electrode formed over the semiconductor substrate, an interlayer insulating film formed over the gate electrode to insulate the gate electrode from the source electrode, and a surface of the semiconductor substrate on which the source electrode is formed are And a drain electrode provided in contact with the silicon substrate on the back surface on the opposite side.
(Issues to be solved by the reference example)
In Patent Document 2, after polysilicon exposed to the outside of a gate trench is removed by etch back to form a gate electrode, impurity ions are selectively implanted into a semiconductor substrate and heat treatment is performed to form a source region. There is.

However, in such a method, the depth of the source region due to the ion implantation becomes deeper than the design value, and there is a possibility that a part of the channel layer immediately below may be transformed into the source region. Due to this deterioration, the channel layer becomes thinner than the design value, and the channel length becomes short.
The reason for this is that since the processing accuracy of the etch back is low, the upper surface (etch back surface) of the gate electrode after the etch back is often recessed with respect to the surface of the semiconductor substrate. Therefore, when implanting impurity ions into the surface of the semiconductor substrate, part of the impurity ions is also implanted into the semiconductor substrate from the side surface of the gate trench exposed near the etch back surface of the gate electrode.

An object of the reference example is to provide a semiconductor device capable of precisely controlling a channel length as designed and a manufacturing method thereof.
Another object of the reference example is to provide a semiconductor device capable of achieving both high breakdown voltage and low on resistance and a method of manufacturing the same.
(Embodiment of Reference Example)
Hereinafter, embodiments of the reference example will be described in detail with reference to the attached drawings.

FIG. 10 is a schematic plan view of a MOS transistor according to an embodiment of the reference example. 11 is a bird's-eye view of the MOS transistor of FIG. 10, and shows a cross section taken along line XI-XI of FIG.
Referring to FIG. 10, MOS transistor 41 as a semiconductor device includes a plurality of stripe-shaped unit cells 42 arranged in parallel to one another. Each unit cell 42 is partitioned by the striped gate trenches 43, and the distance between adjacent gate trenches 43 (trench pitch P) is, for example, 0.9 μm to 1.5 μm. Further, in each unit cell 42, one long (long in plan view) contact trench 44 extending from one end in the longitudinal direction toward the other end is formed in each unit cell 42.

Next, referring to FIG. 11, MOS transistor 41 includes a substrate 45 as a semiconductor layer made of n ⁺ -type (for example, concentration 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ⁻³ ) Si. . The substrate 45 functions as a drain of the MOS transistor 41. The n-type impurities include phosphorus (P), arsenic (As), and the like. same as below.
On the surface 46 (upper surface) of the substrate 45, an epitaxial layer 48 made of n ⁻ -type (for example, a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁵ cm ⁻³ ) lower in concentration than the substrate 45 is stacked. There is. The thickness of the epitaxial layer 48 as the semiconductor layer is, for example, 3 μm to 50 μm, and the thickness of the semiconductor layer including the substrate and the epitaxial layer is, for example, 70 μm to 300 μm.

In epitaxial layer 48, gate trench 43 having side surface 51 and bottom surface 52 dug down from surface 49 toward substrate 45 is formed in a stripe shape. Thus, a plurality of stripe-shaped unit cells 42 partitioned by the side surface 51 of the stripe-shaped gate trench 43 are formed in the epitaxial layer 48.
The gate trench 43 has a depth _{D 1} measured from the surface 49 of the epitaxial layer 48 is, for example (specifically, 40 [mu] m) 30-50 microns are deep trench, through the epitaxial layer 48, the deepest portion Are located midway in the thickness direction of the substrate 45.

A gate insulating film 53 integrally covering the inner surface of the gate trench 43 and the peripheral portion of the gate trench 43 on the surface 49 of the epitaxial layer 48 is formed. The thickness of the gate insulating film is, for example, 0.025 μm to 0.15 μm.
A gate electrode 54 is formed to face the epitaxial layer 48 with the gate insulating film 53 interposed therebetween. Gate electrode 54 is made of, for example, polysilicon heavily doped with impurities.

The gate electrode 54 is epitaxially grown on both sides in the width direction (lateral direction) of the gate trench 43 from the trench 55 filled in the gate trench 43 and the end on the opening end side of the trench 55 It integrally includes a planar portion 56 drawn along the surface 49 of the layer 48, and is formed in a T-shape in cross section.
A p ⁻ -type (for example, a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ ) channel layer 57 is formed around gate trench 43 in the vicinity (surface portion) of surface 49 of epitaxial layer 48. There is. The channel layer 57 contains, for example, boron (B), aluminum (Al) or the like as a p-type impurity. same as below. Further, in the epitaxial layer 48, the portion on the back surface 50 side of the epitaxial layer 48 with respect to the channel layer 57 is the drain layer 58.

The channel layer 57 sandwiches the gate trench 43 from both sides in the width direction at the corner (trench corner 59) of the gate trench 43 formed by the intersection of the side surface 51 of the gate trench 43 and the surface 49 of the epitaxial layer 48. And exposed to both the surface 49 of the epitaxial layer 48 and the side surface 51 of the gate trench 43. Thus, in the channel layer 57, an L-shape in which the side surface portion 60 facing the trench 55 of the gate electrode 54 and the surface portion 61 facing the planar portion 56 of the gate electrode 54 intersect perpendicularly at the trench corner 59 Is formed. The depth of the channel layer 57 (the depth of the side surface portion 60) _{D 2} is shallower than the gate trenches 43, for example, a 0.5Myuemu～3.0Myuemu.

A source layer 62 is formed on the surface portion of the epitaxial layer 48 in the channel layer 57 so as to be exposed to the surface 49. The source layer 62 is a source well formed so that the whole of the periphery and the lower part is surrounded by the channel layer 57, and the channel layer 57 is interposed between the source layer 62 and the drain layer 58.
The source layer 62 penetrates by a predetermined amount below the end of the planar portion 56 of the gate electrode 54 and overlaps a portion of the planar portion 56, and is adjacent to the surface portion 61 of the channel layer 57 on the opposite side of the gate trench 43. An overlap portion 63 and a contact portion 64 exposed on a side surface 65 (described later) of the contact trench 44 are integrally provided.

Source layer 62 varies in depth depending on the position along surface 49 of epitaxial layer 48, and, for example, overlap portion 63 is shallower than contact portion 64. Specifically, the depth _{D 3} of the overlapping portion 63 is, for example, a 0.2Myuemu～1.0Myuemu, the depth _{D 4} of the contact portion 64 is, for example, 0.3Myuemu～1.1Myuemu. The depth of the source layer 62 is three times or less the thickness of the gate insulating film 53 when measured from any position along the surface 49 of the epitaxial layer 48.

  In each unit cell 42, a contact trench 44 which penetrates the source layer 62 from the surface 49 of the epitaxial layer 48 and reaches the channel layer 57 at the deepest portion is formed. The opening width W of the contact trench 44 is constant in the depth direction, and is, for example, 0.2 μm to 0.5 μm. The contact portion 64 of the source layer 62 is exposed on the side surface 65 of the contact trench 44, and the channel layer 57 is exposed on the bottom surface 66 of the contact trench 44.

Then, in the channel layer 57 exposed to the bottom surface 66 of the contact trench 44, a p ⁺ -type (for example, a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ ) channel contact region 67 is formed. The channel contact region 67 is formed linearly on the entire bottom surface 66 of the contact trench 44 along the longitudinal direction of the contact trench 44.
An interlayer insulating film 68 is formed on the epitaxial layer 48 so as to cover the gate electrode 54 (planar portion 56). In the interlayer insulating film 68, a contact hole 69 for exposing the contact trench 44 is formed.

  Although not shown, a source electrode is formed on the interlayer insulating film 68, and the source electrode is formed on all the unit cells 42 (the source layer 62 and the channel contact region) via the contact trenches 44. 67) collectively. That is, the source electrode is a wiring common to all unit cells 42. In addition, a drain electrode is formed on the back surface 47 of the substrate 45 so as to cover the entire area. The drain electrode is a common electrode to all unit cells 42.

12A to 12H are diagrams showing a part of the manufacturing process of the MOS transistor of FIG. 11 in the order of steps, showing a cut surface at the same position as FIG.
In order to manufacture the MOS transistor 41, as shown in FIG. 12A, CVD (Chemical Vapor Deposition: chemical vapor deposition), LPE (Liquid Phase Epitaxy: liquid phase epitaxy), MBE (Molecular Beam Epitaxy: molecular beam epitaxy). Si crystal is grown on the surface 46 of the substrate 45 while being doped with n-type impurity ions by the epitaxial growth method such as the. Thus, the n ⁻ -type epitaxial layer 48 (drain layer 58) is formed on the substrate 45. Next, p-type impurity ions (B ions) are implanted toward the surface 49 of the epitaxial layer 48. After implantation, annealing (for example, at 900 ° C. to 1000 ° C., 10 minutes to 30 minutes) activates the implanted p-type impurity ions to form channel layer 57.

Next, as shown in FIG. 12B, for example, a SiO ₂ film 70 is formed on the surface 49 of the epitaxial layer 48 by the CVD method, and an SiN film 71 is formed on the SiO ₂ film 70 to form a SiO ₂ film. A hard mask 72 consisting of a two-layer film of 70 and a SiN film 71 is formed. The thickness of the SiO ₂ film 70 is, eg, 50 Å to 100 Å, and the thickness of the SiN film 71 is, eg, 1000 Å to 1500 Å. Next, the hard mask 72 is used to etch the epitaxial layer 48 and a part of the substrate 45 so as to penetrate the channel layer 57 and the drain layer 58. Thereby, epitaxial layer 48 is dry etched from surface 49 to form gate trench 43. At the same time, a plurality of unit cells 42 are formed in the epitaxial layer 48.

Next, as shown in FIG. 12C, gate insulating film 53 is formed on the inner surface (side surface 51 and bottom surface 52) of gate trench 43 by, eg, thermal oxidation (for example, 10 minutes to 30 minutes at 850 ° C. to 950 ° C.). Form At this time, the SiO ₂ film 70 of the hard mask 72 is integrated with the gate insulating film 53 at the trench corner 59 and becomes the gate insulating film 53 on the surface 49 of the epitaxial layer 48. Thereafter, the SiN film 71 of the hard mask 72 is removed.

  Next, as shown in FIG. 12D, doped polysilicon is deposited from above the epitaxial layer 48, for example, by the CVD method. The deposition of polysilicon continues until at least the gate trench 43 is filled and the surface 49 of the epitaxial layer 48 is hidden. Thereby, the electrode material layer 73 is formed. Next, a photoresist 74 having a predetermined pattern is formed on the electrode material layer 73, and the electrode material layer 73 is selectively etched by dry etching using the photoresist 74 as a mask.

Thus, as shown in FIG. 12E, from the trench 55 filled in the gate trench 43 and the end of the open end of the trench 55, the width direction (lateral direction) of the gate trench 43 with respect to the end Gate electrode 54 integrally including planar portion 56 drawn along surface 49 of epitaxial layer 48 on both sides of.
Next, as shown in FIG. 12E, using the gate electrode 54 a (planar portions 56) as a mask, an implantation angle theta ₁ which is inclined by 3 ° to 14 ° relative to the surface 49 of the epitaxial layer 48, the epitaxial layer An n-type impurity ion (As ion) is implanted toward the surface 49 of 48 (first step).

Next, from the opposite side of the implantation position in the first step with respect to gate trench 43, the n-type impurity in the first step at an implantation angle θ ₂ inclined at 3 ° to 14 ° with respect to surface 49 of epitaxial layer 48. The same n-type impurity ion is implanted toward the surface 49 of the epitaxial layer 48 so as to cross the ion incident direction. After implantation, annealing is performed (for example, at 900 ° C. to 1000 ° C., for 10 minutes to 30 minutes) to activate the implanted n-type impurity ions so that the source layer is self-aligned to planar portion 56. 62 are formed.

In the first step and the second step, an overlap portion 63 is formed in the source layer 62 below the planar portion 56 of the gate electrode 54, but a portion where the overlap portion 63 is formed in the channel layer 57 Is covered with the planar portion 56 at the time of ion implantation. Therefore, unlike the portion (contact portion 64) into which n-type impurity ions are directly implanted, the overlap portion 63 is formed relatively shallow (D ₃ <D ₄ ).

Next, as shown in FIG. 12F, SiO ₂ (insulating material) is deposited from above the epitaxial layer 48 by, eg, CVD to form an interlayer insulating film 68.
Next, as shown in FIG. 12G, contact holes 69 are formed in the interlayer insulating film 68 by dry etching, for example. After contact hole 69 is formed, exposed epitaxial layer 48 is etched using interlayer insulating film 68 as a mask. Thus, epitaxial layer 48 is dry etched from surface 49, and contact trench 44 is formed in a self-aligned manner with respect to interlayer insulating film 68.

Next, as shown in FIG. 12H, a contact in a direction perpendicular to the bottom surface 66 of trench 44, p-type impurity ions (BF ₂ ions at an implantation energy and 1 × ¹⁰ 15 ^cm dose of about ^-2 about 40keV 1) to inject a single stage of impurity at a depth position near the bottom surface 66 in the channel layer 57. After implantation, annealing (for example, at 900 ° C. to 950 ° C. for 0.5 minutes to 1 minute) diffuses and activates the implanted p-type impurity ions to form channel contact region 67. .

Thereafter, a source electrode (not shown), a drain electrode (not shown) and the like are formed to obtain the MOS transistor 41 shown in FIG.
As described above, according to the MOS transistor 41, a voltage higher than the threshold voltage is applied to the gate electrode 54 in the state where the drain voltage is applied between the source layer 62 and the drain layer 58 (between the source and the drain). An electric field is generated from the gate electrode 54 (ON state). As a result, as shown in FIG. 13A, a channel can be formed in the side surface portion 60 of the channel layer 57 along the side surface 51 of the gate trench 43 and at the same time the surface 49 of the epitaxial layer 48 is formed. A channel can be formed in the surface portion 61 of the channel layer 57 to allow current to flow in the lateral direction. That is, in the channel layer 57, a vertical channel and a lateral channel are formed, and these channels meet at the trench corner 59 to form an L-shaped channel as a whole.

The channel length of the L-shaped channel is the sum of the channel lengths of the vertical channel and the horizontal channel. The channel length in the vertical direction is determined by the depth of the side surface portion 60 of the channel layer 57, and the channel length in the lateral direction is determined by the width of the surface portion 61 of the channel layer 57.
In the present embodiment, in the process of FIG. 12A, if the channel layer 57 is formed with the designed depth based on the implantation conditions of the p-type impurity ion, then the source layer 62 shown in FIG. At the time of n-type impurity ion implantation, the side surface portion 60 of the channel layer 57 is covered with the planar portion 56 (mask) of the gate electrode 54. Therefore, it is not affected by the n-type impurity ion. In the present embodiment, since n-type impurity ions are obliquely implanted, some n-type impurity ions are implanted below the planar portion 56, but the amount is very small, and the implantation position is also planar. Since it remains at the end of the portion 56, the side portion 60 of the channel layer 57 is not affected by the n-type impurity ion. Therefore, in the present embodiment, since the depth of the side surface portion 60 of the channel layer 57 can be held precisely as designed, the channel length in the vertical direction can be precisely controlled as designed.

  On the other hand, the width of the surface portion 61 of the channel layer 57 is influenced by the formation accuracy of the source layer 62 formed on the side, but in the present embodiment, as shown in FIG. The source layer 62 is formed in a self-aligned manner with respect to the planar portion 56 (mask) of the gate electrode 54 formed. As a result, excessive advancement of the source layer 62 to the surface portion 61 of the channel layer 57 covered by the planar portion 56 can be prevented. Therefore, the electrode material layer 73 is etched as designed to form the planar portion 56. The width of the surface portion 61 of the channel layer 57 can be precisely controlled as designed. As a result, the channel length in the lateral direction can also be precisely controlled as designed, as can the channel length in the vertical direction.

  Further, according to this MOS transistor 41, a part of source layer 62 is formed to overlap with planar part 56 of gate electrode 54 as overlap part 63, so that channel layer 57 adjacent to this overlap part 63 is formed. The surface portion 61 can be made to face the planar portion 56 of the gate electrode 54 with certainty. As a result, highly reliable transistor operation can be performed.

Such an overlap portion 63 can be easily formed by positively injecting n-type impurity ions below the planar portion 56 by adopting oblique implantation as shown in FIG. 12E. .
Furthermore, according to this MOS transistor 41, since gate trench 43 is a deep trench which penetrates channel layer 57 and drain layer 58 from surface 49 of epitaxial layer 48 to reach substrate 45, when MOS transistor 41 is turned on. Carriers (electrons) contained in the drain layer 58 can be attracted to the vicinity of the side surface 51 of the gate trench 43 by the electric field from the gate electrode 54. The attracted carriers are accumulated so as to be uniformly distributed along the side surface 51 in the depth direction of the gate trench 43, and form a layered carrier accumulation layer 75 in the vicinity of the side surface 51 of the gate trench 43.

When the MOS transistor 41 is on, the carrier storage layer 75 can be used as a current path. Therefore, the on-resistance of MOS transistor 41 can be reduced regardless of the inherent resistance value of epitaxial layer 48. Therefore, the epitaxial layer 48 can be thickened to achieve high breakdown voltage while maintaining low on-resistance.
As mentioned above, although embodiment of the reference example was described, the reference example can also be implemented by other forms.

For example, the arrangement form of the unit cells 42 does not have to be a stripe, and may be a matrix as shown in FIG. 14 or a zigzag as shown in FIG.
In addition, the shape of each unit cell 42 is not limited to the stripe shape (FIG. 10) or the quadrangular prism (FIGS. 14 and 15), for example, other polygonal prisms such as triangular prism, pentagon prism, hexagonal prism, etc. Good.

Further, in the MOS transistor 41, a configuration in which the conductivity type of each semiconductor portion is inverted may be employed. For example, in the MOS transistor 41, the p-type portion may be n-type and the n-type portion may be p-type.
Further, ion implantation for forming source layer 62 is not limited to oblique implantation in which ions are implanted in a direction inclined with respect to surface 49 of epitaxial layer 48, for example, perpendicular to surface 49 of epitaxial layer 48. Vertical implantation may be employed to implant ions in a direction.

Also, instead of the epitaxial layer 48, for example, a SiC epitaxial layer can be used.
(Features to be understood from the disclosure of the embodiment of the reference example)
For example, from the disclosure of the embodiment of the reference example, the inventions of the following (1) to (14) can be grasped.
(1) A semiconductor layer of a first conductivity type in which a gate trench is formed,
An electrode facing the semiconductor layer with a gate insulating film interposed therebetween, and a trench portion filled in the gate trench and an end portion on the opening end side of the trench portion laterally along the surface of the semiconductor layer A gate electrode integrally including a planar portion taken out;
A layer of a second conductivity type formed on a surface portion of the semiconductor layer so as to be exposed on both the surface of the semiconductor layer and the side surface of the gate trench and having a depth shallower than the gate trench, A channel layer including a surface portion facing the planar portion of the gate electrode and a side surface portion facing the trench portion of the gate electrode;
A semiconductor device comprising: a source layer of a first conductivity type formed in the channel layer to be exposed to the surface of the semiconductor layer and adjacent to the surface portion of the channel layer on the opposite side of the gate trench .
(2) The semiconductor device according to (1), wherein the source layer has an overlap portion which is inserted below the end portion of the planar portion by a predetermined amount and overlaps a portion of the planar portion.
(3) The semiconductor device according to (2), wherein the overlapping portion of the source layer is shallower than the remaining portion of the source layer.
(4) The semiconductor device according to any one of (1) to (3), wherein the depth of the source layer is three times or less the thickness of the gate insulating film.
(5) The gate trench is a deep trench in which a storage layer of the first conductivity type carrier included in the semiconductor layer can be formed along the side surface by an electric field from the gate electrode when the semiconductor device is turned on. The semiconductor device as described in any one of (1)-(4) containing.
(6) The semiconductor layer includes a substrate of a first conductivity type, and an epitaxial layer formed on the substrate and having a lower impurity concentration than the substrate,
The semiconductor device according to (5), wherein the deep trench includes a trench which penetrates the epitaxial layer and reaches the substrate.
(7) The semiconductor device according to any one of (1) to (6), wherein the thickness of the semiconductor layer is 70 μm to 300 μm.
(8) The semiconductor device according to any one of (1) to (7), wherein a depth of the gate trench is 30 μm to 50 μm.
(9) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed to partition unit cells arranged in a stripe shape.
(10) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed to partition unit cells arranged in a matrix.
(11) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed to partition unit cells arranged in a staggered manner.
(12) forming a channel layer to be exposed on the surface of the semiconductor layer by implanting ions of the second conductivity type into the semiconductor layer of the first conductivity type;
Forming a gate trench deeper than the depth of the channel layer by etching the semiconductor layer from the surface so as to penetrate the channel layer;
Forming a gate insulating film on the inner surface of the gate trench and the surface of the semiconductor layer;
Depositing an electrode material on the gate dielectric until the gate trench is filled and the surface of the semiconductor layer is covered;
By patterning the portion outside the gate trench of the electrode material by etching, the trench portion filled in the gate trench and the edge portion on the opening end side of the trench portion extend along the surface of the semiconductor layer laterally. Forming a gate electrode integrally including the planar portion taken out;
In the state where the lower portion of the planar portion of the channel layer is covered with the planar portion, the planar portion is implanted with ions of the first conductivity type through the surface of the semiconductor layer. And the step of forming the source layer in a self-aligned manner.
(13) In the step of forming the source layer, a portion of the source layer enters a predetermined amount below an end of the planar portion to form an overlapping portion overlapping with the portion of the planar portion. (12) The method of manufacturing a semiconductor device according to (12), including the step of obliquely implanting the first conductivity type ions at an implantation angle which is inclined with respect to the surface of the semiconductor layer.
(14) The step of forming the gate trench includes the step of forming a stripe trench so that unit cells are arranged in a stripe shape in the semiconductor layer,
The step of obliquely implanting the first conductivity type ion includes a first step of obliquely implanting the first conductivity type ion from one side in the width direction to the stripe trench, and a step of the first step of implanting the stripe trench The semiconductor process according to (13), including a second step of obliquely implanting the first conductivity type ion in a direction intersecting the incident direction of the first conductivity type ion in the first step from the opposite side of the implantation position Device manufacturing method.
(Effect of the above features to be grasped)
The semiconductor device of (1) can be manufactured, for example, by the method of manufacturing a semiconductor device of (12).

According to the inventions of (1) and (12), the channel formed on the side surface of the channel layer by the electric field from the gate electrode and flowing the current in the vertical direction along the side surface of the gate trench In order to form a bi-directional channel of the channel which allows current to flow laterally along the surface of the semiconductor layer.
The vertical channel length is determined by the depth of the side portion of the channel layer, and the lateral channel length is determined by the width of the surface portion of the channel layer.

  In the invention of the reference example, if the channel layer is formed with the designed depth based on the implantation conditions of the second conductivity type ions, then, at the time of the first conductivity type ion implantation for forming the source layer, the channel Since the side surface of the layer is covered with the planar portion (mask) of the gate electrode, it is not affected by the first conductivity type ions. Therefore, since the depth of the side portion of the channel layer can be precisely maintained as designed, the channel length in the vertical direction can be precisely controlled as designed.

  On the other hand, the width of the surface portion of the channel layer depends on the formation accuracy of the source layer formed laterally, but in the invention of the reference example, the planar portion of the gate electrode formed by the etching technique excellent in processing accuracy The source layer is formed in a self-aligned manner with respect to the mask). Since excessive advancement of the source layer to the surface portion of the channel layer covered by the planar portion can be prevented, the width of the surface portion of the channel layer is made by etching the electrode material as designed to form the planar portion. It can be precisely controlled as designed. As a result, the channel length in the lateral direction can also be precisely controlled as designed, as can the channel length in the vertical direction.

In the semiconductor device of the reference example, as described in (2), the source layer has an overlap portion which enters a predetermined amount below the end of the planar portion and overlaps with a part of the planar portion. Is preferred. In this case, as described in (3), the overlapping portion of the source layer may be shallower than the remaining portion of the source layer.
According to this configuration, the surface portion of the channel layer reliably faces the planar portion of the gate electrode, so that highly reliable transistor operation can be performed.

In the semiconductor device of the reference example, as described in (4), the depth of the source layer may be three times or less the thickness of the gate insulating film.
In the semiconductor device of the reference example, as described in (5), when the semiconductor device is turned on, the gate trench is made of the first conductivity type carrier contained in the semiconductor layer by an electric field from the gate electrode. It is preferred to include a deep trench in which the accumulation layer can be formed along its side.

According to this configuration, a low resistance carrier storage layer is formed in the semiconductor layer, and this carrier storage layer can be used as a current path when the semiconductor device is on. Therefore, the on resistance of the semiconductor device can be lowered regardless of the intrinsic resistance value of the semiconductor layer. Therefore, the semiconductor layer can be thickened to achieve high breakdown voltage while maintaining low on-resistance.
Specifically, as described in (6), when the semiconductor layer includes a substrate of a first conductivity type and an epitaxial layer formed on the substrate and having a lower impurity concentration than the substrate, the deep layer Preferably, the trench comprises a trench through the epitaxial layer to the substrate.

As a result, since the carrier concentration can be formed in the entire thickness direction of the epitaxial layer which has a low impurity concentration and hinders the reduction of the on-resistance, the effect of the reduction of the on-resistance is large.
In the semiconductor device of the reference example, as described in (7), the thickness of the semiconductor layer may be 70 μm to 300 μm, and as described in (8), the depth of the gate trench is It may be 30 μm to 50 μm.

Also, the gate trenches may be unit cells arranged in a stripe as described in (9), unit cells arranged in a matrix as described in (10), and as described in (11). It may be formed to partition unit cells of any form represented by the unit cells arranged in a staggered manner.
In the semiconductor device manufacturing method of the reference example, as described in (13), in the step of forming the source layer, a part of the source layer enters a predetermined amount below an end of the planar portion. It is preferable to include the step of obliquely implanting the first conductivity type ions at an implantation angle inclined to the surface of the semiconductor layer so that an overlap portion overlapping with a part of the planar portion is formed.

By this method, since the first conductivity type ions can be positively implanted below the planar portion, the overlap portion of the source layer can be easily formed.
In addition, as described in (14), in the case where the step of forming the gate trench includes the step of forming a stripe trench so that unit cells are arranged in a stripe shape in the semiconductor layer, the first conductivity type ion In the step of obliquely implanting, the first step of obliquely implanting the ions of the first conductivity type from one side in the width direction to the stripe trench, and the opposite side of the implantation position of the first step with respect to the stripe trench It is preferable to include a second step of obliquely implanting the first conductivity type ion in a direction intersecting the incident direction of the first conductivity type ion in the first step.

Reference Signs List 1 MOS transistor 2 unit cell 3 gate trench 4 contact trench 5 Si substrate 6 front surface 7 (for Si substrate) back surface 8 (for Si substrate) 8 Si epitaxial layer 9 front surface (for Si epitaxial layer) 10 back surface 11 (for Si epitaxial layer) Side surface 12 (gate trench) bottom surface 13 (gate trench) bottom surface 13 source region 14 channel region 15 drain region 16 gate insulating film 17 gate electrode 18 side surface (of contact trench) 19 bottom surface (of contact trench) 20 channel contact region 21 interlayer insulation film 22 contact hole 23 channel portion 24 projecting portion 25 top 26 SiO ₂ film 27 SiN film 28 hard mask 29 surface 30 channel region 31 protrusions 32 top 33 top 41 MOS transistor 42 unit cells 43 Gate trench 44 Contact trench 45 Substrate 46 Surface 47 (Substrate) Back surface 48 Epitaxial layer 49 Surface 50 (Epitaxial layer) Surface 50 (Epitaxial layer) Back surface 51 (Gate trench) Bottom 52 (Gate trench) 53 Gate insulating film 54 Gate electrode 55 Trench portion 56 (for gate electrode) Planar portion 57 (for gate electrode) 57 Channel layer 58 Drain layer 59 Trench corner portion 60 Side portion (for channel layer) 61 Surface portion (for channel layer) 62 Source layer 63 (the contact trench) overlap portion 64 contact portion 65 side 66 (the contact trench) bottom 67 channel contact region 68 interlayer insulating film 69 contact hole 70 SiO ₂ film 71 SiN film 72 hard mask 73 electrode member Layer 74 photoresist 75 carrier accumulation layer

Claims (36)

A semiconductor layer in which a gate trench is formed,
A source region of a first conductivity type which is formed to be exposed on the surface side of the semiconductor layer and which forms a part of the side surface of the gate trench;
A channel region of a second conductivity type formed on the back surface side of the semiconductor layer with respect to the source region so as to be in contact with the source region and forming a part of the side surface of the gate trench;
A channel contact region of a second conductivity type formed in the channel region so as to be exposed to the surface side of the semiconductor layer, and having a first end and a second end in the width direction along the surface of the semiconductor layer;
A drain region of a first conductivity type formed on the back surface side of the semiconductor layer with respect to the channel region so as to be in contact with the channel region and forming a bottom surface of the gate trench;
A gate insulating film formed on the inner surface of the gate trench;
A gate electrode buried inside the gate insulating film in the gate trench,
Said channel region is formed along the side surface of the gate trench, and a channel portion in which a channel is formed during operation, the back side to the end of the channel portion of the back side of the front Symbol semiconductor layer A semiconductor device comprising : two projecting portions having a first top and a second top and having a first top and a second top at positions below the first end and the second end of the channel contact region . The channel region includes a recess formed to extend from the surface of the semiconductor layer to the back surface side of the semiconductor layer relative to an interface between the source region and the channel region.
The semiconductor device according to claim 1 , wherein the channel portion has an impurity concentration different from that of the bottom of the recess. The recess includes a contact trench which penetrates the source region from the surface of the semiconductor layer and the deepest portion reaches the channel region.
It said channel contact region is formed in the bottom surface of the contact trench,
The semiconductor device according to claim 2 , wherein the impurity concentration of the convex portion is 1/100 or less of the concentration of the channel contact region. The recess includes a contact trench which penetrates the source region from the surface of the semiconductor layer and the deepest portion reaches the channel region.
It said channel contact region is formed in the bottom surface of the contact trench,
The semiconductor device according to claim 2 , wherein the convex portion is formed immediately below the channel contact region. The first top and the second top portion of the convex portion, along said lower position of the widthwise ends of the bottom surface of the contact trench are parallel to each other, the semiconductor device according to claim 4. The said 1st top part and the said 2nd top part of the said convex part are located in the said back surface side of the said semiconductor layer with respect to the said bottom face of the said gate trench as described in any one of Claims 1-5 . Semiconductor device. The semiconductor device according to any one of claims 1 to 6 , wherein the semiconductor layer is made of a Si semiconductor layer. The semiconductor device according to any one of claims 1 to 7 , wherein an end of the channel portion is located on the surface side of the semiconductor layer with respect to the bottom surface of the gate trench. The first top and the second top portion of the convex portion, the lower position of the width direction first end of the bottom surface and the second end portion of said contact trench, respectively, are located, according to claim 4 Semiconductor devices. The semiconductor device according to claim 9 , wherein the first top and the second top are formed parallel to each other along the contact trench. 11. The semiconductor device according to claim 10 , wherein the first top and the second top are formed in line symmetry with a vertical line passing through a widthwise center of the bottom of the contact trench as an axis of symmetry s. The semiconductor device according to claim 11 , wherein an opposite top of the channel region on the symmetry axis s is positioned deeper than the bottom surface of the gate trench. The Si semiconductor layer includes a Si substrate, and a Si epitaxial layer formed on the Si substrate and having an impurity concentration lower than that of the Si substrate,
The semiconductor device according to claim 7 , wherein the first top and the second top of the protrusion are not in contact with the Si substrate. The thickness of the channel portion is 0.5Myuemu～0.9Myuemu, thickness of up to the first top and the second top portion of the convex portion is 1.0Myuemu～1.6Myuemu, claims 1 to 13 The semiconductor device according to any one of the above. The semiconductor device according to any one of claims 1 to 14 , wherein an amount of projection of the gate trench from an interface between the channel portion and the drain region is 0.2 μm to 0.1 μm. The contact trench is formed in a stripe shape,
The semiconductor device according to claim 4 , wherein the convex portion is formed in a stripe shape along the stripe contact trench. The semiconductor device according to claim 4 , wherein the contact trench is formed shallower than the gate trench. The semiconductor device according to any one of claims 1 to 17 , wherein the gate insulating film includes a silicon oxide film. A semiconductor layer having a first surface and a second surface and having a trench formed on the first surface;
A first region of a first conductivity type which is formed to be exposed to the first surface side of the semiconductor layer and which forms a part of the side surface of the trench;
A second region of a second conductivity type formed on the second surface side with respect to the first region and forming a part of the side surface of the trench;
A third region of a first conductivity type formed on the second surface side with respect to the second region and forming a bottom surface of the trench;
An insulating film formed on the inner surface of the trench;
And a first electrode embedded inside the insulating film in the trench,
The second region is a first portion disposed closer to the first surface of the semiconductor layer than a bottom surface of the trench, and a portion extending from the first portion toward the second surface of the semiconductor layer from the bottom surface of the trench And a second portion which protrudes in contact with the first portion and is formed to be exposed on the first surface side of the semiconductor layer, and a first end in a width direction along the first surface of the semiconductor layer and Integrally includes a third portion having two ends ,
The second portion defines an interface between the second region and the third region, and the interface is inclined with respect to the first surface of the semiconductor layer ,
The second portion of the second region is parabolic in two cross-sectional views having a first top and a second top at positions below the first end and the second end of the third portion, respectively. A semiconductor device being formed . 20. The semiconductor device according to claim 19 , further comprising: a recess formed from a first surface to a second surface of the semiconductor layer and disposed immediately above the second portion of the second region. Wherein the third portion of the second region is formed on the bottom surface of the recess, that have a higher impurity concentration than the first portion, the semiconductor device according to claim 20. 22. The semiconductor device according to claim 20 , wherein the second portion of the second region has a width wider than the widest width of the recess. The semiconductor device according to any one of claims 19 to 22 , wherein the third region is partially formed between the side surface of the trench and the boundary surface. 22. The semiconductor device according to claim 21 , wherein the first portion of the second region has an impurity concentration different from that of the third portion of the second region. 25. The semiconductor device according to claim 24 , wherein the impurity concentration of the second portion is 1/100 or less of the concentration of the third portion. Wherein the first top and the second top portion of the second portion, along the lower position of the widthwise ends of the bottom surface of the recess are parallel to each other, the semiconductor device according to claim 20. The semiconductor device according to any one of claims 19 to 26 , wherein the semiconductor layer comprises a Si semiconductor layer. The first top and the second top portion of the second portion, the lower position of the first end width direction of the bottom surface and the second end portion of the recess, respectively, are located, according to claim 20 Semiconductor devices. The semiconductor device according to claim 28 , wherein the first top and the second top are formed parallel to each other along the recess. The semiconductor device according to claim 29 , wherein the first top and the second top are formed in line symmetry with a vertical line passing through a widthwise center of the bottom surface of the recess as a symmetry axis s. The Si semiconductor layer includes a Si substrate, and a Si epitaxial layer formed on the Si substrate and having an impurity concentration lower than that of the Si substrate,
The semiconductor device according to claim 27 , wherein the first top and the second top of the second portion are not in contact with the Si substrate. The thickness of the first portion is a 0.5Myuemu～0.9Myuemu, thickness of up to the first top and the second top portion of the second portion is 1.0Myuemu～1.6Myuemu, claim 19 31. The semiconductor device according to any one of to 31 . The semiconductor device according to any one of claims 19 to 32, wherein an amount of protrusion of the trench from an interface between the first portion and the third region is 0.2 μm to 0.1 μm . The recess is formed in a stripe shape,
The semiconductor device according to claim 20 , wherein the second portion is formed in a stripe shape along the stripe-shaped concave portion. The semiconductor device according to claim 20 , wherein the recess is formed shallower than the trench. The semiconductor device according to any one of claims 19 to 35 , wherein the insulating film includes a silicon oxide film.

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