JP6976286B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor equipment comprising a trench gate type MOSFET.

As an example of a trench-gate MOSFET, for example, the semiconductor device of Patent Document 1, n gate trenches are formed ^- -type first base layer, a gate insulating film formed on the inner surface of the gate trench, the gate insulating film a gate electrode which is filled on the inside, an interlayer insulating film formed to cover the gate electrode, n ^- are formed on the surface of the mold first base layer, a p-type are formed shallower than the bottom surface of the gate trench The 2 base layer, the n ⁺ type source layer ^{formed on the surface of the p-type second base layer, the self-aligned contact groove formed through the n +} type source layer and into the p-type second base layer, and the self-aligned contact groove. It is formed on the bottom surface of the self-aligned contact groove, connected to the p-type second base layer, and on the side surface of the self-aligned contact groove, the source electrode connected to the ^{n + type source layer and the back surface of the n −} type first base layer. It is provided with an n ⁺ type drain layer and a drain electrode formed on the ^{n + type drain layer.}

Japanese Unexamined Patent Publication No. 2010-62477 Japanese Unexamined Patent Publication No. 2010-021176

The semiconductor device of the present invention has a semiconductor layer having a first surface and a second surface, a first trench formed on the first surface of the semiconductor layer, and a first surface formed on the first surface of the semiconductor layer. With respect to the two trenches, the first conductive type region formed so as to be exposed on the first surface side of the semiconductor layer and forming a part of the side surface of the first trench, and the first region. With respect to the second conductive type second region formed on the second surface side of the semiconductor layer so as to be in contact with the first region and forming a part of the side surface of the first trench, and the second region. The semiconductor layer is formed on the second surface side of the semiconductor layer so as to be in contact with the second region, and is formed on the third region of the first conductive type forming the bottom surface of the first trench and the inner surface of the first trench. The first electrode is included, and the first electrode embedded inside the insulating film in the first trench is included, and the second region is relatively formed on the first surface side of the semiconductor layer. A portion and a second portion formed below the first portion and projecting from the first portion to a depth located on the second surface side of the semiconductor layer with respect to the bottom surface of the first trench. The second portion of the second region, which is integrally included, is a convex portion protruding with the vicinity of the bottom of the first trench as an end portion, and forms a curved surface with the third region. The top of the second portion of the second region is located between the first trench and the second trench, and the distance from the top of the second portion to the first trench and the first trench. The distance from the top of the two portions to the second trench is approximately the same.

FIG. 1 is a schematic plan view of a trench gate type MOS transistor according to an embodiment of the present invention. FIG. 2 is a bird's-eye view of the trench gate type MOS transistor of FIG. 1 and shows a cut surface at the cut line II-II of FIG. FIG. 3A is a diagram showing a part of the manufacturing process of the trench gate type MOS transistor of FIG. FIG. 3B is a diagram showing the next step of FIG. 3A. FIG. 3C is a diagram showing the next step of FIG. 3B. FIG. 3D is a diagram showing the next step of FIG. 3C. FIG. 3E is a diagram showing the next step of FIG. 3D. FIG. 3F is a diagram showing the next step of FIG. 3E. FIG. 3G is a diagram showing the next step of FIG. 3F. FIG. 3H is a diagram showing the next step of FIG. 3G. FIG. 3I is a diagram showing the next step of FIG. 3H. FIG. 3J is a diagram showing the next step of FIG. 3I. 4 (a) to 4 (d) are views showing a modification of the ion implantation method of FIG. 3G, where FIG. 4 (a) is for one-stage implantation and FIGS. 4 (b) to 4 (d) are for multi-stage implantation. Examples are shown respectively. FIG. 5 is a graph showing the relationship between the dose amount of B11 ions and the breakdown voltage. FIG. 6 is a diagram showing a modified example of the convex portion of the trench gate type MOS transistor of FIG. 1. FIG. 7 is a diagram for explaining an ion implantation method when forming the convex portion of FIG. 6. FIG. 8 is a diagram showing a first modification of the arrangement form of the unit cell of the trench gate type MOS transistor of FIG. FIG. 9 is a diagram showing a second modification of the arrangement form of the unit cell of the trench gate type MOS transistor of FIG. FIG. 10 is a schematic plan view of the MOS transistor according to the embodiment of the reference example. 11 is a bird's-eye view of the MOS transistor of FIG. 10, showing a cut surface at the cut line XI-XI of FIG. FIG. 12A is a diagram showing a part of the manufacturing process of the MOS transistor of FIG. FIG. 12B is a diagram showing the next step of FIG. 12A. FIG. 12C is a diagram showing the next step of FIG. 12B. FIG. 12D is a diagram showing the next step of FIG. 12C. FIG. 12E is a diagram showing the next step of FIG. 12D. FIG. 12F is a diagram showing the next step of FIG. 12E. FIG. 12G is a diagram showing the next step of FIG. 12F. FIG. 12H is a diagram showing the next step of FIG. 12G. 13 (a) and 13 (b) are diagrams showing the on and off states of the MOS transistor of FIG. 11, where FIG. 13 (a) shows the on state and FIG. 13 (b) shows the off state. .. FIG. 14 is a diagram showing a first modification of the arrangement form of the unit cell of the MOS transistor of FIG. FIG. 15 is a diagram showing a second modification of the arrangement form of the unit cell of the MOS transistor of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a trench gate type MOS transistor according to an embodiment of the present invention. FIG. 2 is a bird's-eye view of the trench gate type MOS transistor of FIG. 1 and shows a cut surface at the cut line II-II of FIG.
With reference to FIG. 1, the MOS transistor 1 as a semiconductor device is a trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a plurality of striped unit cells 2 arranged in parallel with each other. Each unit cell 2 is partitioned by a striped gate trench 3, and the distance between adjacent gate trenches 3 (trench pitch P) is, for example, 0.9 μm to 1.5 μm. Further, in the unit cell 2, a long (planar view rectangular) contact trench 4 extending from one end in the longitudinal direction toward the other end is formed in each unit cell 2.

Next, referring to FIG. 2, the MOS transistor 1 includes an n ⁺ type (for example, a concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ^-3 ) Si substrate 5. The Si substrate 5 functions as a drain of the MOS transistor 1. The n-type impurities include phosphorus (P), arsenic (As) and the like. same as below.
^{An n-} type (for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁵ cm ^-3 ) Si epitaxial layer 8 having a lower concentration than that of the Si substrate 5 is laminated on the surface 6 (upper surface) of the Si substrate 5. There is. The thickness of the Si epitaxial layer 8 as the semiconductor layer is, for example, 3 μm to 10 μm.

In the Si epitaxial layer 8, a gate trench 3 having a side surface 11 and a bottom surface 12 is formed in a striped shape, which is dug from the surface 9 toward the Si substrate 5. As a result, the Si epitaxial layer 8 is formed with a plurality of striped unit cells 2 partitioned by the side surfaces 11 of the striped gate trench 3.
_{The depth D 1} of the gate trench 3 measured from the surface 9 of the Si epitaxial layer 8 is, for example, 1.0 μm to 1.5 μm, specifically 1.0 μm.

In the Si epitaxial layer 8, around the gate trench 3, an n ⁺ type source region 13 and a p ⁻ type (for example, a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ^-3 ) channel region 14 are Si epitaxial. The layers 8 are formed in this order from the side closest to the surface 9. The channel region 14 contains, for example, boron (B), aluminum (Al), and the like as p-type impurities. same as below.

The source region 13 is exposed on the surface 9 of the Si epitaxial layer 8 and is formed on the surface layer portion of each unit cell 2 so as to form an upper portion (part) of the side surface 11 of the gate trench 3. _{The thickness T 1} of the source region 13 along the direction from the surface 9 to the Si substrate 5 is, for example, 0.2 μm to 0.4 μm. When the thickness is defined in the following description, it means the thickness along the direction from the surface 9 of the Si epitaxial layer 8 toward the Si substrate 5 unless otherwise specified.

The channel region 14 is in contact with the source region 13 on the Si substrate 5 side (the back surface 10 side of the Si epitaxial layer 8) with respect to the source region 13 and forms a lower portion (part) of the side surface 11 of the gate trench 3. It is formed to do.
On the other hand, in the Si epitaxial layer 8, the area of the Si substrate 5 side with respect to the channel region 14, remains after the epitaxial growth is maintained, n ^- has a -type drain region 15. The drain region 15 is in contact with the channel region 14 on the Si substrate 5 side with respect to the channel region 14, and forms the bottom surface 12 of the gate trench 3.

A gate insulating film 16 is formed on the inner surface of the gate trench 3 so as to cover the entire area thereof. Then, in the gate trench 3, the gate electrode 17 is embedded in the gate trench 3 by embedding polysilicon in which n-type impurities are doped at a high concentration inside the gate insulating film 16. In this way, the vertical MOS transistor 1 structure is configured in which the source region 13 and the drain region 15 are arranged apart from each other via the channel region 14 in the vertical direction perpendicular to the surface 9 of the Si epitaxial layer 8.

Each unit cell 2 is formed with a contact trench 4 that penetrates the source region 13 from the surface 9 of the Si epitaxial layer 8 and reaches the channel region 14 at the deepest portion. The opening width W of the contact trench 4 is constant in the depth direction thereof, and is, for example, 0.2 μm to 0.5 μm. The source region 13 is exposed on the side surface 18 of the contact trench 4, and the channel region 14 is exposed on the bottom surface 19 of the contact trench 4.

^{A p +} type (for example, a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 ) channel contact region 20 is formed in the channel region 14 exposed on the bottom surface 19 of the contact trench 4. The channel contact region 20 is formed linearly on the entire bottom surface 19 of the contact trench 4 along the longitudinal direction of the contact trench 4.
An interlayer insulating film 21 is formed on the Si epitaxial layer 8. A contact hole 22 that exposes the contact trench 4 is formed in the interlayer insulating film 21.

Although not shown, a source electrode is formed on the interlayer insulating film 21, and the source electrode is used as a unit cell 2 (source region 13 and channel contact region) via each contact trench 4. It is in contact with 20) all at once. That is, the source electrode has common wiring for all unit cells 2. Further, a drain electrode is formed on the back surface 7 of the Si substrate 5 so as to cover the entire area thereof. This drain electrode is a common electrode for all unit cells 2.

Then, in this embodiment, in each unit cell 2, the portion directly below the contact trench 4 of the channel region 14 protrudes (raises) in a cross-sectional view in a direction away from the channel contact region 20.
Specifically, the channel region 14 has both ends near the channel portion 23 of the channel region 14 in which the channel is formed during the operation of the MOS transistor 1, and is located below the center portion in the width direction of the bottom surface 19 of the contact trench 4 from both ends. It protrudes in a parabolic shape drawn so that one peak (top 25) comes to the surface. As a result, the channel region 14 has a convex portion 24 protruding toward the back surface 10 side with respect to the end portion of the channel portion 23 on the back surface 10 side of the Si epitaxial layer 8 as a portion partitioned by the parabola. ..

The top 25 (parabolic peak) of the convex portion 24 is located on the back surface 10 side of the Si epitaxial layer 8 with respect to the bottom surface 12 of the gate trench 3 within a range not in contact with the Si substrate 5 (that is, the gate trench). (Deeper than the bottom surface 12 of 3), it is formed linearly along the contact trench 4. Further, the conductive type of the convex portion 24 is the same p ⁻ type as the channel region 14 (for example, the concentration is 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ^-3 ), and the impurity concentration thereof is the p ⁺ type (for example, for example). The concentration is preferably 1/100 or less of the channel contact region 20 of ^{1 × 10 19} to 1 × 10 ²⁰ cm ^-3).

Further, in the channel region 14, the thickness T ₂ of the channel portion 23 is, for example, 0.5 μm to 0.9 μm, specifically 0.8 μm. _{The thickness T 3} of the convex portion 24 up to the top 25 is, for example, 1.0 μm to 1.6 μm, specifically 1.4 μm.
3A to 3J are views showing a part of the manufacturing process of the trench gate type MOS transistor of FIG. 2, and show a cut surface at the same position as that of FIG.

To manufacture the MOS transistor 1, as shown in FIG. 3A, a CVD (Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, and an MBE (Molecular Beam Epitaxy) method are used. ) Method or other epitaxial growth method is used to grow Si crystals on the surface 6 of the Si substrate 5 while doping n-type impurities. As a result, an n ^- type Si epitaxial layer 8 (drain region 15) is formed on the Si substrate 5. Next, p-type impurities and n-type impurities are injected in order toward the surface 9 of the Si epitaxial layer 8. After the injection, an annealing treatment (for example, 900 ° C. to 1000 ° C. for 10 minutes to 30 minutes) activates each of the injected impurities to form the channel region 14 and the source region 13 at the same time. Then, for example, by a CVD method, an SiO ₂ film 26 is formed on the surface 9 of the Si epitaxial layer 8, by forming the SiN film 27 is formed over the SiO ₂ film 26, the SiO ₂ film 26 and the SiN film 27 A hard mask 28 composed of a two-layer film is formed. The thickness of the SiO ₂ film 26 is, for example, 50 Å to 100 Å, and the thickness of the SiN film 27 is, for example, 1000 Å to 1500 Å.

Next, as shown in FIG. 3B, the Si epitaxial layer 8 is etched using this hard mask 28. As a result, the Si epitaxial layer 8 is dry-etched from the surface 9 to form the gate trench 3. At the same time, a plurality of unit cells 2 are formed on the Si epitaxial layer 8.
Next, as shown in FIG. 3C, the gate insulating film 16 is formed on the inner surface (side surface 11 and bottom surface 12) of the gate trench 3 by, for example, a thermal oxidation method (for example, 850 ° C. to 950 ° C. for 10 minutes to 30 minutes). To form.

Next, as shown in FIG. 3D, for example, the doped polysilicon (electrode material) is deposited from above the Si epitaxial layer 8 by the CVD method. The polysilicon deposits continue until at least the surface 9 of the Si epitaxial layer 8 is hidden. Then, the deposited polysilicon is etched back until the etch back surface is flush with the surface 9 of the Si epitaxial layer 8. As a result, the gate electrode 17 made of polysilicon remaining in the gate trench 3 is formed.

Next, as shown in FIG. 3E, for example, by the CVD method, SiO ₂ (insulating material) is deposited from above the Si epitaxial layer 8 to form the interlayer insulating film 21.
Next, as shown in FIG. 3F, a contact hole 22 is formed in the interlayer insulating film 21 by, for example, dry etching. After the contact hole 22 is formed, the exposed Si epitaxial layer 8 is etched using the interlayer insulating film 21 as a mask. As a result, the Si epitaxial layer 8 is dry-etched from the surface 9 to form the contact trench 4 in a self-aligned manner with respect to the interlayer insulating film 21.

Next, as shown in FIG. 3G, by injecting an impurity (B11 ion) in a direction perpendicular to the bottom surface 12 of the contact trench 4, Si is provided with respect to the interface 29 between the channel region 14 and the drain region 15. One step of impurities is injected into the depth position on the surface 9 side of the epitaxial layer 8 (near the interface 29 in the channel region 14). The injection energy of the impurity ion is, for example, 100 keV to 140 keV, preferably about 140 keV. The dose amount of the impurity ion is, for example, 4 × 10 ¹² cm ^-2 to 1 × 10 ¹³ cm ^-2 , preferably 6 × 10 ¹² cm ^-2 to 8 × 10 ¹² cm ^-2 .

After injection, annealing treatment (for example, 900 ° C to 950 ° C for 0.5 minutes to 1 minute) diffuses and activates the injected p-type impurities, as shown in FIG. 3H, to diffuse and activate the channel region. The convex portion 24 of 14 is formed.
_{Next, as shown in FIG. 3I, impurities (BF 2} ions) are incident in a direction perpendicular to the bottom surface 12 of the contact trench 4 with an injection energy of about 40 keV and a dose amount of about ^{1 × 10 15} cm- ^2. By doing so, impurities are injected one step at a depth position near the bottom surface 12 in the channel region 14.

After injection, annealing treatment (for example, 900 ° C to 950 ° C for 0.5 minutes to 1 minute) diffuses and activates the injected p-type impurities as shown in FIG. 3J, resulting in channel contact. Region 20 is formed.
After that, the MOS transistor 1 shown in FIG. 2 is obtained by forming a source electrode (not shown), a drain electrode (not shown), and the like.

As described above, according to this embodiment, a part of the channel region 14 has both ends in the vicinity of the channel portion 23 of the channel region 14, and one peak is located below the center portion in the width direction of the bottom surface 19 of the contact trench 4 from both ends. It protrudes as a convex portion 24 in a parabolic shape drawn so as to come. As a result, the area of the pn junction interface is reduced to the area of the MOS transistor as compared with the conventional structure in which the depth from the surface 9 of the Si epitaxial layer 8 to the interface (pn junction interface) between the channel region 14 and the drain region 15 is constant. It can be increased without affecting the channel characteristics of 1. That is, since only the portion directly below the contact trench 4 of the channel region 14 is projected without changing the length (channel length) of the channel portion 23, there is almost no effect on the channel characteristics. Therefore, the area of the depletion layer spreading from the pn junction also becomes large, and the depletion layer receives a voltage in a large area. As a result, the voltage received per unit area of the depletion layer can be reduced.

Therefore, the protrusion amount L (for example, 0.2 μm to 0.1 μm in this embodiment) of the gate trench 3 toward the back surface 10 side of the Si epitaxial layer 8 is small with respect to the interface between the channel portion 23 and the drain region 15. (The gate trench 3 is shallow), and even if the depletion layer spreading from the interface between the gate insulating film 16 and the drain region 15 with a small area cannot secure the withstand voltage, a large area depletion layer is formed near the convex portion 24 of the channel region 14. Since it exists, the withstand voltage of the MOS transistor 1 as a whole can be improved.

Therefore, while sufficiently maintaining the withstand voltage between the source and the drain, the gate trench 3 can be made shallow to reduce the facing area between the gate electrode 17 and the drain region 15, and the capacitance between the gate and the drain can be reduced.
Moreover, since the convex portion 24 of the channel region 14 projects in a direction away from the channel contact region 20, contact between the depletion layer extending from the interface between the convex portion 24 and the drain region 15 and the channel contact region 20 is prevented. Can be done. Therefore, it is possible to avoid a decrease in withstand voltage due to contact between the two.

Further, such a convex portion 24 is an impurity toward the bottom surface 12 of the contact trench 4, which is one step lower than the surface 9 of the Si epitaxial layer 8 by utilizing the conventional ion implantation technique. It can be easily formed by implanting ions. Further, since the impurity ion can be incident perpendicularly to the bottom surface 12 of the contact trench 4 to form the convex portion 24, it is not necessary to precisely adjust the angle when injecting the impurity ion, and the injection angle can be switched. Is not necessary.

The ion implantation method and the implantation depth for forming the convex portion 24 are changed according to the shape and depth of the gate trench 3 and the shape and size of the impurity regions such as the source region 13 and the channel region 14. be able to.
For example, as shown in FIG. 4A, impurities are present at a depth position on the back surface 10 side of the Si epitaxial layer 8 (near the interface 29 in the drain region 15) with respect to the interface 29 between the channel region 14 and the drain region 15. Can be injected in one stage.

Further, as shown in FIG. 4B, by changing the injection energy in the range of 80 keV to 180 keV, some of the injection depths of the impurity ions (B11 ions) are on the surface 9 side of the Si epitaxial layer 8. Impurity ions are injected in multiple stages so that the region defined by the injection portion straddles the front surface 9 side and the back surface 10 side of the Si epitaxial layer 8 with respect to the interface 29 so that the rest is on the back surface 10 side. You can also do it.

Further, when multi-stage injection is adopted, as shown in FIG. 4C, the impurity ions are added so that the injection depth of all the impurity ions is on the back surface 10 side of the Si epitaxial layer 8 with respect to the interface 29. Impurity ions may be injected, or as shown in FIG. 4D, the impurity ions are injected so that the injection depth of all the impurity ions is on the surface 9 side of the Si epitaxial layer 8 with respect to the interface 29. You may.

In this way, by selecting the ion injection method such as one-stage and multi-stage and the ion injection depth, the convex portions 24 having various shapes can be formed. Therefore, it is possible to form the convex portion 24 having an appropriate shape according to the shape and depth of the gate trench 3 and the shape and size of the impurity region such as the source region 13 and the channel region 14.
Further, by setting the dose amount of impurities (B11 ions) in ^{the range of 4 × 10 12} cm ^-2 to 1 × 10 ¹³ cm ^-2 , the breakdown voltage between the drain and the source can be improved. Specifically, as shown in FIG. 5 (injection energy = 140 keV), when the dose amount of B11 ions ^{is in the range of 4 × 10 12} cm ^-2 to 1 × 10 ¹³ cm ^-2 , the breakdown voltage is 36 V or more. We were able to.

Further, the shape of the convex portion 24 does not have to be a shape partitioned by one parabola in a cross-sectional view, and may be a shape partitioned by two parabolas, for example.
Specifically, as in the convex portion 31 of the channel region 30 in FIG. 6, the vicinity of the channel portion 23 is set as both ends, and the lower end positions of the bottom surface 19 of the contact trench 4 in the width direction and the lower end portions are respectively located from the both ends. It is preferable that the peaks (top 32) project in two parabolas drawn so as to come one by one. In this case, the top 32 of each convex portion 31 is aligned in a straight line parallel to each other along the contact trench 4. Further, the convex portion 31 on one side and the convex portion 31 on the other side are preferably axisymmetric with the perpendicular line passing through the central portion of the bottom surface 19 of the contact trench 4 in the width direction as the axis of symmetry s, and are on the axis of symmetry s. The top 33 on the opposite side is preferably located on the back surface 10 side of the Si epitaxial layer 8 with respect to the bottom surface 12 of the gate trench 3 (that is, at a position deeper than the bottom surface 12 of the gate trench 3).

Then, for example, instead of the process of FIG. 3G, the convex portion 31 of FIG. 6 has an injection angle θ ₁ inclined at 7 ° to 14 ° with respect to the bottom surface 12 of the contact trench 4, and is one end in the width direction of the contact trench 4. _{The first step of injecting the impurity ions toward the portion and the injection angle θ 2} inclined at 7 ° to 14 ° with respect to the bottom surface 12 of the contact trench 4 so as to intersect the incident direction of the impurity ions in the first step. It can be formed by performing a second step of injecting impurity ions toward the other end of the contact trench 4 in the width direction.

_{According to this method, it is necessary to switch the injection angle of impurity ions (θ 1} → θ ₂ ) at the time of transition from the first step to the second step, but the convex portion 31 has a plurality of tops 32 (peaks). Therefore, the area of the interface between the convex portion 31 and the drain region 15 can be further increased. As a result, the voltage received per unit area of the depletion layer can be further reduced.
Although the embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.

For example, the arrangement of the unit cells 2 does not have to be striped, but may be a matrix as shown in FIG. 8 or a staggered pattern as shown in FIG.
Further, the shape of each unit cell 2 is not limited to the stripe shape (FIG. 1) and the square columnar shape (FIGS. 8 and 9), and may be other polygonal columns such as a triangular columnar column, a pentagonal columnar column, and a hexagonal columnar column. good.
Further, in the MOS transistor 1, a configuration in which the conductive type of each semiconductor portion is inverted may be adopted. For example, in the MOS transistor 1, the p-type portion may be n-type and the n-type portion may be p-type.

Further, for example, a SiC epitaxial layer can be used instead of the Si epitaxial layer 8.
Further, the convex portion of the channel region does not need to be directly under the contact trench 4 like the convex portions 24 and 31, and can be formed in various places within a range that does not affect the channel characteristics of the MOS transistor 1. ..

In addition, various design changes can be made within the scope of the matters described in the claims.
In addition, the features extracted from the description in this specification and drawings are shown below.
For example, the semiconductor device includes a semiconductor layer in which a gate trench is formed, a first conductive type source region formed so as to be exposed on the surface side of the semiconductor layer, and forming a part of a side surface of the gate trench. With respect to the second conductive type channel region formed so as to be in contact with the source region on the back surface side of the semiconductor layer with respect to the source region and forming a part of the side surface of the gate trench, and the channel region. A first conductive type drain region formed on the back surface side of the semiconductor layer so as to be in contact with the channel region and forming the bottom surface of the gate trench, a gate insulating film formed on the inner surface of the gate trench, and the above. The channel region includes a gate electrode embedded inside the gate insulating film in the gate trench, a channel portion formed along the side surface of the gate trench, and a channel formed during operation, and the semiconductor layer. Includes a convex portion protruding toward the back surface side with respect to the end portion of the channel portion on the back surface side of the above.

According to this configuration, a part of the channel region protrudes as a convex portion on the back surface side of the semiconductor layer at a portion different from the portion (channel portion) in which the channel is formed during operation. As a result, the area of the pn junction interface affects the channel characteristics of the semiconductor device as compared with the conventional structure in which the depth from the surface of the semiconductor layer to the interface between the channel region and the drain region (pn junction interface) is constant. Can be increased without giving. Therefore, the area of the depletion layer spreading from the pn junction also becomes large, and the depletion layer receives a voltage in a large area. As a result, the voltage received per unit area of the depletion layer can be reduced.

Therefore, the amount of protrusion of the gate trench toward the back surface side of the semiconductor layer is small with respect to the interface between the channel region and the drain region (the gate trench is shallow), and the depletion layer extending from the interface of the small area between the gate insulating film and the drain region. Even if the withstand voltage cannot be ensured by itself, since the depletion layer having a large area exists in the vicinity of the convex portion of the channel region, the withstand voltage of the semiconductor device as a whole can be improved.

Therefore, while sufficiently maintaining the withstand voltage between the source and the drain, the gate trench can be made shallow to reduce the facing area between the gate electrode and the drain region, and the capacitance between the gate and the drain can be reduced.
Further, the semiconductor device has a contact trench that penetrates the source region from the surface of the semiconductor layer and reaches the channel region at the deepest portion, and a second conductive type channel contact region formed on the bottom surface of the contact trench. It is preferable that the convex portion is formed directly below the channel contact region.

The semiconductor device having such a configuration is, for example, a first conductive type source region formed so as to be exposed on the front surface side, and a second conductive type source region formed so as to be in contact with the source region on the back surface side with respect to the source region. The source region and the channel region are penetrated through a semiconductor layer having a conductive type channel region and a first conductive type drain region formed so as to be in contact with the channel region on the back surface side of the channel region. A gate electrode is formed by forming a gate trench whose deepest portion reaches the drain region, a step of forming a gate insulating film on the inner surface of the gate trench, and embedding an electrode material inside the gate insulating film. A step of forming a contact trench in the semiconductor layer that penetrates the source region and reaches the channel region at the deepest portion, and a step of forming a contact trench through the bottom surface of the contact trench to obtain the channel region and the drain region. By injecting the second conductive ion so as to reach the vicinity of the interface, the back surface side of the semiconductor layer of the channel portion of the channel region formed along the side surface of the gate trench immediately below the contact trench. By injecting a second conductive type ion into the vicinity of the bottom surface of the contact trench of the semiconductor layer in a step of forming a convex portion protruding toward the back surface side with respect to the end portion of the semiconductor layer, a channel contact region is formed in the channel region. It can be manufactured by a method for manufacturing a semiconductor device, which includes a step of forming the semiconductor device.

According to this method, the second conductive type ion is incident on the bottom surface of the contact trench, which is one step lower than the surface of the semiconductor layer, by using the conventional ion implantation technique. , Convex can be easily formed in the channel region. Depending on the type of material of the semiconductor layer, an annealing treatment may be performed after the injection of the second conductive type ion to diffuse the second conductive type ion into the semiconductor layer. Such diffusion can be similarly performed when forming the channel contact region.

Further, since the formed convex portion protrudes toward the back surface side of the semiconductor layer in a direction away from the channel contact region, the contact between the depletion layer extending from the interface between the convex portion and the drain region and the channel contact region is prevented. can do. Therefore, it is possible to avoid a decrease in withstand voltage due to contact between the two.
In this case, the top of the convex portion immediately below the channel contact region may be formed along the lower position of the central portion in the width direction of the bottom surface of the contact trench.

A semiconductor device having such a configuration can be manufactured, for example, by executing a step of vertically injecting the second conductive type ion perpendicularly to the bottom surface of the contact trench in the method for manufacturing the semiconductor device. can.
According to this method, it is not necessary to precisely adjust the angle when injecting the second conductive type ion, and it is not necessary to switch the injection angle, and the second conductive type ion can be always injected vertically. Since it is good, the convex portion can be formed more easily.

On the other hand, the top of the convex portion immediately below the channel contact region may be formed along the position below the widthwise end of the bottom surface of the contact trench.
A semiconductor device having such a configuration is manufactured, for example, by executing a step of obliquely injecting the second conductive ion at an injection angle inclined with respect to the bottom surface of the contact trench in the method for manufacturing the semiconductor device. can do.

The tops of the ridges are formed parallel to each other along the bottom of the bottom of the contact trench along the bottom of the widthwise ends of the contact trench, especially along the bottom of the width ends of the bottom. Is preferable. That is, it is preferable that the convex portion protrudes so as to have a plurality of peaks (peaks) instead of a single peak.
The semiconductor device having such a configuration includes the first step of injecting the second conductive ion toward one end in the width direction of the bottom surface of the contact trench when the second conductive ion is obliquely injected, and the first step. The second step of injecting the second conductive type ion in the direction intersecting the incident direction of the second conductive type ion in the first step toward the other end in the width direction of the bottom surface of the contact trench is executed. Can be manufactured by

According to this method, it is necessary to switch the injection angle of the second conductive ion at the time of transition from the first step to the second step. The area of the interface with the drain region can be further increased. As a result, the voltage received per unit area of the depletion layer can be further reduced.
Further, in the semiconductor device, the top of the convex portion is preferably located on the back surface side of the semiconductor layer with respect to the bottom surface of the gate trench, and the impurity concentration of the convex portion is the channel contact. It is preferably 1/100 or less of the concentration of the region. When the impurity concentration of the convex portion satisfies the above condition, the withstand voltage can be further improved.

Further, the semiconductor layer may be made of a Si semiconductor layer.
Further, in the method for manufacturing a semiconductor device, the step of forming the convex portion includes a one-step injection step of injecting the second conductive ion into a position at a predetermined depth from the bottom surface of the contact trench. Alternatively, it may include a multi-stage injection step of injecting the second conductive ion into a plurality of stages from the bottom surface of the contact trench to a predetermined depth by changing the injection energy.

Further, in the one-stage injection step, the second conductive ion is injected at a depth position on either the front surface side or the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. May be good.
Further, in the multi-stage injection step, a region defined by a plurality of stages of injection portions so that some of the injection depths of the second conductive ion are on the front surface side of the semiconductor layer and the rest are on the back surface side. However, the second conductive ion may be injected so as to straddle the front surface side and the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. Further, the second conductive type ion is provided so that the injection depth of all the second conductive type ions is on the front surface side or the back surface side of the semiconductor layer with respect to the interface between the channel region and the drain region. It may be injected.

In this way, by selecting the ion injection method such as one-stage and multi-stage and the ion injection depth, it is possible to form convex portions having various shapes. Therefore, it is possible to form a convex portion having an appropriate shape according to the shape / depth of the gate trench and the shape / size of the impurity region such as the source region and the channel region.
<Invention relating to a reference example>
(Background technology of reference example)
As an example of MOSFET, for example, the semiconductor device of Patent Document 2 is known.

This semiconductor device can be a p-channel power MOSFET (metal-oxide-semiconductor field-effect transistor) including a trench gate. The semiconductor device includes a semiconductor ^{substrate composed of a p +} type silicon substrate, a p-type semiconductor layer formed on the p + type silicon substrate, and an n-type channel layer formed on the p + type silicon substrate.
^{The semiconductor device further includes an n +} -shaped body region formed on the surface of the semiconductor substrate on the channel layer ^{and a p +} -shaped source region surrounding all four sides of the body region in a plan view. Further, the semiconductor device has a gate trench that penetrates the channel layer and reaches the p-type semiconductor layer, a gate oxide film formed on the side surface of the gate trench, and a gate oxide film formed on the bottom surface of the gate trench, which is larger than the gate oxide film. It includes a thick thick oxide film and a gate electrode formed on the gate oxide film and the thick film oxide film in the gate trench and embedding the gate trench.

Further, in the semiconductor device, the source electrode formed on the semiconductor substrate, the interlayer insulating film formed on the gate electrode and insulating the gate electrode and the source electrode, and the surface on which the source electrode of the semiconductor substrate is formed are formed. It includes a drain electrode provided in contact with a silicon substrate on the back surface on the opposite side.
(Problems that the reference example tries to solve)
In Patent Document 2, after the polysilicon exposed to the outside of the gate trench is removed by etchback to form a gate electrode, impurity ions are selectively injected into the semiconductor substrate and heat-treated to form a source region. There is.

However, in such a method, the depth of the source region due to ion implantation becomes deeper than the design value, and a part of the channel layer immediately below the source region may be denatured into the source region. Due to this alteration, the channel layer becomes thinner than the design value, and the channel length becomes shorter.
The reason for this is that the processing accuracy of the etch back is low, so that the upper surface (etch back surface) of the gate electrode after the etch back is often recessed with respect to the surface of the semiconductor substrate. Therefore, when the impurity ions are injected into the surface of the semiconductor substrate, a part of the impurity ions is also injected into the inside of the semiconductor substrate from the side surface of the gate trench exposed near the etch back surface of the gate electrode.

The purpose of the reference example is to provide a semiconductor device and a manufacturing method thereof capable of precisely controlling the channel length as designed.
Another object of the reference example is to provide a semiconductor device capable of achieving both high withstand voltage and low on-resistance and a method for manufacturing the same.
(Embodiment of Reference Example)
Hereinafter, embodiments of the reference example will be described in detail with reference to the accompanying drawings.

FIG. 10 is a schematic plan view of the MOS transistor according to the embodiment of the reference example. 11 is a bird's-eye view of the MOS transistor of FIG. 10, showing a cut surface at the cut line XI-XI of FIG.
With reference to FIG. 10, the MOS transistor 41 as a semiconductor device includes a plurality of striped unit cells 42 arranged in parallel with each other. Each unit cell 42 is partitioned by a striped gate trench 43, and the distance between adjacent gate trenches 43 (trench pitch P) is, for example, 0.9 μm to 1.5 μm. Further, in the unit cell 42, one long contact trench 44 extending from one end in the longitudinal direction toward the other end (rectangular in a plan view) is formed in each unit cell 42.

Next, referring to FIG. 11, the MOS transistor 41 includes a substrate 45 as a semiconductor layer ^{made of n +} type (for example, a concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ^{-3) Si.} .. The substrate 45 functions as a drain of the MOS transistor 41. The n-type impurities include phosphorus (P), arsenic (As) and the like. same as below.
An epitaxial layer 48 made ^{of n-} type (for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁵ cm ^-3 ) Si having a lower concentration than that of the substrate 45 is laminated on the surface 46 (upper surface) of the substrate 45. There is. The thickness of the epitaxial layer 48 as the semiconductor layer is, for example, 3 μm to 50 μm, and the thickness of the semiconductor layer including the substrate and the epitaxial layer is, for example, 70 μm to 300 μm.

In the epitaxial layer 48, a gate trench 43 having a side surface 51 and a bottom surface 52, which is dug from the surface 49 toward the substrate 45, is formed in a striped shape. As a result, the epitaxial layer 48 is formed with a plurality of striped unit cells 42 partitioned by the side surfaces 51 of the striped gate trench 43.
_{The gate trench 43 is a deep trench having a depth D 1} measured from the surface 49 of the epitaxial layer 48, for example, 30 μm to 50 μm (specifically, 40 μm), and penetrates the epitaxial layer 48 to the deepest portion thereof. Is located in the middle of the thickness direction of the substrate 45.

A gate insulating film 53 that integrally covers the inner surface of the gate trench 43 and the peripheral edge of the gate trench 43 on the surface 49 of the epitaxial layer 48 is formed. The thickness of the gate insulating film is, for example, 0.025 μm to 0.15 μm.
The gate electrode 54 is formed so as to face the epitaxial layer 48 with the gate insulating film 53 interposed therebetween. The gate electrode 54 is made of, for example, polysilicon with a high concentration of impurities doped.

The gate electrode 54 is epitaxially formed on both sides of the trench portion 55 filled in the gate trench 43 and the end portion of the trench portion 55 on the open end side in the width direction (lateral direction) of the gate trench 43 with respect to the end portion. The planar portion 56 drawn out along the surface 49 of the layer 48 is integrally included, and is formed in a T-shape in cross-sectional view.
^{A p-} type (for example, a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ^-3 ) channel layer 57 is formed around the gate trench 43 in the vicinity (surface portion) of the surface 49 of the epitaxial layer 48. There is. The channel layer 57 contains, for example, boron (B), aluminum (Al), and the like as p-type impurities. same as below. Further, in the epitaxial layer 48, the portion of the epitaxial layer 48 on the back surface 50 side with respect to the channel layer 57 is the drain layer 58.

The channel layer 57 sandwiches the gate trench 43 from both sides in the width direction at the corner portion (trench corner portion 59) of the gate trench 43 formed by the intersection of the side surface 51 of the gate trench 43 and the surface 49 of the epitaxial layer 48. It is formed on the surface 49 of the epitaxial layer 48 and is exposed on both the side surface 51 of the gate trench 43. As a result, the channel layer 57 has an L-shape in which the side surface portion 60 facing the trench portion 55 of the gate electrode 54 and the surface portion 61 facing the planar portion 56 of the gate electrode 54 vertically intersect at the trench corner portion 59. Is formed in. _{Further, the depth D 2} of the channel layer 57 (depth of the side surface portion 60) is shallower than that of the gate trench 43, for example, 0.5 μm to 3.0 μm.

A source layer 62 is formed on the surface portion of the epitaxial layer 48 in the channel layer 57 so as to be exposed on the surface 49. The source layer 62 is a source well formed so that the entire circumference and the lower portion thereof are surrounded by the channel layer 57, and the channel layer 57 is interposed between the source layer 62 and the drain layer 58.
The source layer 62 enters below the end of the planar portion 56 of the gate electrode 54 by a predetermined amount, overlaps a part of the planar portion 56, and is adjacent to the surface portion 61 of the channel layer 57 on the opposite side of the gate trench 43. The overlapping portion 63 and the contact portion 64 exposed on the side surface 65 (described later) of the contact trench 44 are integrally provided.

The depth of the source layer 62 differs depending on the position along the surface 49 of the epitaxial layer 48, and for example, the overlap portion 63 is shallower than the contact portion 64. Specifically, the depth D ₃ of the overlap portion 63 is, for example, 0.2 μm to 1.0 μm, and the depth D ₄ of the contact portion 64 is, for example, 0.3 μm to 1.1 μm. The depth of the source layer 62 is three times or less the thickness of the gate insulating film 53 when measured from any position along the surface 49 of the epitaxial layer 48.

Each unit cell 42 is formed with a contact trench 44 that penetrates the source layer 62 from the surface 49 of the epitaxial layer 48 and reaches the channel layer 57 at the deepest portion. The opening width W of the contact trench 44 is constant in the depth direction thereof, and is, for example, 0.2 μm to 0.5 μm. The contact portion 64 of the source layer 62 is exposed on the side surface 65 of the contact trench 44, and the channel layer 57 is exposed on the bottom surface 66 of the contact trench 44.

The channel layer 57 exposed on the bottom surface 66 of the contact trench 44 is formed with a p ⁺ type (for example, a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 ) channel contact region 67. The channel contact region 67 is formed linearly on the entire bottom surface 66 of the contact trench 44 along the longitudinal direction of the contact trench 44.
An interlayer insulating film 68 is formed on the epitaxial layer 48 so as to cover the gate electrode 54 (planar portion 56). A contact hole 69 that exposes the contact trench 44 is formed in the interlayer insulating film 68.

Although not shown, a source electrode is formed on the interlayer insulating film 68, and the source electrode is used for all unit cells 42 (source layer 62 and channel contact region) via each contact trench 44. It is in contact with 67) all at once. That is, the source electrode has common wiring for all unit cells 42. Further, a drain electrode is formed on the back surface 47 of the substrate 45 so as to cover the entire area thereof. This drain electrode is a common electrode for all unit cells 42.

12A to 12H are diagrams showing a part of the manufacturing process of the MOS transistor of FIG. 11 in the order of the processes, and show the cut surface at the same position as that of FIG.
To manufacture the MOS transistor 41, as shown in FIG. 12A, a CVD (Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, and an MBE (Molecular Beam Epitaxy) method are used. ) Method or other epitaxial growth method is used to grow Si crystals on the surface 46 of the substrate 45 while doping n-type impurity ions. Thus, on substrate 45, n ^- -type epitaxial layer 48 (drain layer 58) is formed. Next, p-type impurity ions (B ions) are injected toward the surface 49 of the epitaxial layer 48. After the injection, an annealing treatment (for example, 900 ° C. to 1000 ° C. for 10 minutes to 30 minutes) activates the injected p-type impurity ions to form the channel layer 57.

Next, as shown in FIG. 12B, for example, by a CVD method, to form a SiO ₂ film 70 on the surface 49 of the epitaxial layer 48, by forming the SiN film 71 on the SiO ₂ film 70, SiO ₂ film A hard mask 72 composed of a two-layer film of 70 and a SiN film 71 is formed. The thickness of the SiO ₂ film 70 is, for example, 50 Å to 100 Å, and the thickness of the SiN film 71 is, for example, 1000 Å to 1500 Å. Next, using this hard mask 72, a part of the epitaxial layer 48 and the substrate 45 is etched so as to penetrate the channel layer 57 and the drain layer 58. As a result, the epitaxial layer 48 is dry-etched from the surface 49 to form the gate trench 43. At the same time, a plurality of unit cells 42 are formed on the epitaxial layer 48.

Next, as shown in FIG. 12C, the gate insulating film 53 is formed on the inner surface (side surface 51 and bottom surface 52) of the gate trench 43 by, for example, a thermal oxidation method (for example, 850 ° C. to 950 ° C. for 10 minutes to 30 minutes). To form. At this time, the SiO ₂ film 70 of the hard mask 72 is integrated with the gate insulating film 53 at the trench corner 59 to become the gate insulating film 53 on the surface 49 of the epitaxial layer 48. After that, the SiN film 71 of the hard mask 72 is removed.

Next, as shown in FIG. 12D, the doped polysilicon is deposited from above the epitaxial layer 48, for example, by the CVD method. The polysilicon deposits continue until at least the gate trench 43 is filled and the surface 49 of the epitaxial layer 48 is hidden. As a result, the electrode material layer 73 is formed. Next, a photoresist 74 having a predetermined pattern is formed on the electrode material layer 73, and the electrode material layer 73 is selectively etched by dry etching using the photoresist 74 as a mask.

As a result, as shown in FIG. 12E, the width direction (lateral direction) of the gate trench 43 from the trench portion 55 filled in the gate trench 43 and the end portion of the trench portion 55 on the open end side with respect to the end portion. ), A gate electrode 54 including a planar portion 56 integrally drawn along the surface 49 of the epitaxial layer 48 is formed.
_{Next, as shown in FIG. 12E, the epitaxial layer is used at an injection angle θ 1} that is inclined from 3 ° to 14 ° with respect to the surface 49 of the epitaxial layer 48 by using the gate electrode 54 (planar portion 56) as a mask. N-type impurity ions (As ions) are injected toward the surface 49 of 48 (first step).

_{Next, at an injection angle θ 2} inclined from the opposite side of the injection position of the first step to the gate trench 43 with respect to the surface 49 of the epitaxial layer 48 by 3 ° to 14 °, n-type impurities in the first step. The same n-type impurity ion is injected toward the surface 49 of the epitaxial layer 48 so as to intersect the incident direction of the ion. After the injection, an annealing treatment (for example, at 900 ° C. to 1000 ° C. for 10 minutes to 30 minutes) activates the injected n-type impurity ions and self-aligns the source layer with respect to the planar portion 56. 62 is formed.

During the first step and the second step, the overlap portion 63 that has entered below the planar portion 56 of the gate electrode 54 is formed in the source layer 62, but the overlap portion 63 in the channel layer 57 is formed. Is covered with the planar portion 56 at the time of ion implantation. Therefore, unlike the portion (contact portion 64) in which the n-type impurity ion is directly injected, the overlap portion 63 is formed relatively shallow (D ₃ <D ₄ ).

Next, as shown in FIG. 12F, for example, by the CVD method, SiO ₂ (insulating material) is deposited from above the epitaxial layer 48 to form the interlayer insulating film 68.
Next, as shown in FIG. 12G, a contact hole 69 is formed in the interlayer insulating film 68 by, for example, dry etching. After forming the contact hole 69, the exposed epitaxial layer 48 is etched using the interlayer insulating film 68 as a mask. As a result, the epitaxial layer 48 is dry-etched from the surface 49, and the contact trench 44 is formed in a self-aligned manner with respect to the interlayer insulating film 68.

Next, as shown in FIG. 12H, p-type impurity ions (BF ₂ ions) with ^{an injection energy of about 40 keV and a dose amount of about 1 × 10 15} cm- ^{2 in the} direction perpendicular to the bottom surface 66 of the contact trench 44. ) Is incident on the channel layer 57 to inject one stage of impurities at a depth position near the bottom surface 66. After injection, annealing treatment (for example, 900 ° C to 950 ° C for 0.5 minutes to 1 minute) diffuses and activates the injected p-type impurity ions to form a channel contact region 67. ..

After that, the MOS transistor 41 shown in FIG. 11 can be obtained by forming a source electrode (not shown), a drain electrode (not shown), and the like.
As described above, according to the MOS transistor 41, a voltage equal to or higher than the threshold voltage is applied to the gate electrode 54 in a state where the drain voltage is applied between the source layer 62 and the drain layer 58 (between the source and the drain). An electric field is generated from the gate electrode 54 (ON state). As a result, as shown in FIG. 13A, a channel through which a current flows in the vertical direction along the side surface 51 of the gate trench 43 can be formed on the side surface portion 60 of the channel layer 57, and at the same time, on the surface 49 of the epitaxial layer 48. A channel through which current flows laterally can be formed on the surface portion 61 of the channel layer 57. That is, in the channel layer 57, bidirectional channels of a vertical channel and a lateral channel are formed, and these channels intersect at the trench angle portion 59 to form an L-shaped channel as a whole.

The channel length of the L-shaped channel is the sum of the channel lengths of the vertical channel and the horizontal channel. The vertical channel length is determined by the depth of the side surface portion 60 of the channel layer 57, and the lateral channel length is determined by the width of the surface portion 61 of the channel layer 57.
In the present embodiment, if the channel layer 57 is formed at the design depth based on the implantation conditions of the p-type impurity ion in the step of FIG. 12A, then the source layer 62 shown in FIG. 12E is formed. When the n-type impurity ion is implanted, the side surface portion 60 of the channel layer 57 is covered with the planar portion 56 (mask) of the gate electrode 54. Therefore, it is not affected by the n-type impurity ion. In this embodiment, since the n-type impurity ion is injected diagonally, a small amount of the n-type impurity ion is also injected below the planar portion 56, but the amount is very small and the injection position is also the planar. Since it stays at the end of the portion 56, the side surface portion 60 of the channel layer 57 is not affected by the n-type impurity ion. Therefore, in the present embodiment, the depth of the side surface portion 60 of the channel layer 57 can be precisely maintained as designed, so that the channel length in the vertical direction can be precisely controlled as designed.

On the other hand, the width of the surface portion 61 of the channel layer 57 depends on the forming accuracy of the source layer 62 formed beside the channel layer 57, but in the present embodiment, as shown in FIG. 12E, an etching technique having excellent processing accuracy is used. The source layer 62 is self-aligned with respect to the planar portion 56 (mask) of the formed gate electrode 54. Therefore, it is possible to prevent the source layer 62 from excessively advancing to the surface portion 61 of the channel layer 57 covered with the planar portion 56. Therefore, the electrode material layer 73 is etched as designed to form the planar portion 56. , The width of the surface portion 61 of the channel layer 57 can be precisely controlled as designed. As a result, the lateral channel length can be precisely controlled as designed, as is the vertical channel length.

Further, according to the MOS transistor 41, a part of the source layer 62 is formed as an overlap portion 63 so as to overlap the planar portion 56 of the gate electrode 54, so that the channel layer 57 adjacent to the overlap portion 63 is formed. The surface portion 61 can be reliably opposed to the planar portion 56 of the gate electrode 54. As a result, highly reliable transistor operation can be performed.

Then, as shown in FIG. 12E, such an overlap portion 63 can be easily formed by positively injecting n-type impurity ions below the planar portion 56 by adopting oblique injection. ..
Further, according to the MOS transistor 41, since the gate trench 43 is a deep trench that reaches the substrate 45 from the surface 49 of the epitaxial layer 48 through the channel layer 57 and the drain layer 58, when the MOS transistor 41 is turned on. The electric field from the gate electrode 54 can attract carriers (electrons) contained in the drain layer 58 to the vicinity of the side surface 51 of the gate trench 43. The attracted carriers are accumulated so as to be uniformly distributed along the side surface 51 in the depth direction of the gate trench 43, and form a layered carrier accumulation layer 75 in the vicinity of the side surface 51 of the gate trench 43.

Then, when the MOS transistor 41 is turned on, the carrier storage layer 75 can be used as a current path. Therefore, the on-resistance of the MOS transistor 41 can be lowered regardless of the inherent resistance value of the epitaxial layer 48. Therefore, it is possible to achieve a high withstand voltage by thickening the epitaxial layer 48 while maintaining a low on-resistance.
Although the embodiment of the reference example has been described above, the reference example can also be implemented in other embodiments.

For example, the arrangement of the unit cells 42 does not have to be striped, but may be a matrix as shown in FIG. 14 or a zigzag as shown in FIG.
Further, the shape of each unit cell 42 is not limited to the stripe shape (FIG. 10) and the square columnar shape (FIGS. 14 and 15), and may be other polygonal columns such as a triangular columnar shape, a pentagonal columnar shape, and a hexagonal columnar shape. good.

Further, in the MOS transistor 41, a configuration in which the conductive type of each semiconductor portion is inverted may be adopted. For example, in the MOS transistor 41, the p-type portion may be n-type and the n-type portion may be p-type.
Further, the ion implantation when forming the source layer 62 is not limited to diagonal implantation in which ions are implanted in a direction inclined with respect to the surface 49 of the epitaxial layer 48, and is, for example, perpendicular to the surface 49 of the epitaxial layer 48. Vertical implantation, in which ions are implanted in the direction, may be employed.

Further, for example, a SiC epitaxial layer can be used instead of the epitaxial layer 48.
(Characteristics to be grasped from the disclosure of the embodiment of the reference example)
For example, the following inventions (1) to (14) can be grasped from the disclosure of the embodiments of the reference example.
(1) A first conductive type semiconductor layer on which a gate trench is formed, and
An electrode facing the semiconductor layer with a gate insulating film interposed therebetween, along the surface of the semiconductor layer laterally from the trench portion filled in the gate trench and the end portion on the open end side of the trench portion. A gate electrode that integrally includes the pulled-out planar part,
A second conductive layer formed on the surface portion of the semiconductor layer so as to be exposed on both the surface of the semiconductor layer and the side surface of the gate trench and having a depth shallower than that of the gate trench. A channel layer including a surface portion of the gate electrode facing the planar portion and a side surface portion of the gate electrode facing the trench portion.
A semiconductor device including a first conductive type source layer formed in the channel layer so as to be exposed on the surface of the semiconductor layer and adjacent to the surface portion of the channel layer on the opposite side of the gate trench. ..
(2) The semiconductor device according to (1), wherein the source layer has an overlapping portion that enters below an end portion of the planar portion and overlaps a part of the planar portion.
(3) The semiconductor device according to (2), wherein the overlapping portion of the source layer is shallower than the remaining portion of the source layer.
(4) The semiconductor device according to any one of (1) to (3), wherein the depth of the source layer is three times or less the thickness of the gate insulating film.
(5) The gate trench is a deep trench in which a storage layer of a first conductive carrier contained in the semiconductor layer can be formed along a side surface thereof by an electric field from the gate electrode when the semiconductor device is turned on. The semiconductor device according to any one of (1) to (4), which includes.
(6) The semiconductor layer includes a first conductive type substrate and an epitaxial layer formed on the substrate and having a lower impurity concentration than the substrate.
The semiconductor device according to (5), wherein the deep trench includes a trench that penetrates the epitaxial layer and reaches the substrate.
(7) The semiconductor device according to any one of (1) to (6), wherein the thickness of the semiconductor layer is 70 μm to 300 μm.
(8) The semiconductor device according to any one of (1) to (7), wherein the depth of the gate trench is 30 μm to 50 μm.
(9) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed so as to partition unit cells arranged in a striped pattern.
(10) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed so as to partition unit cells arranged in a matrix.
(11) The semiconductor device according to any one of (1) to (8), wherein the gate trench is formed so as to partition unit cells arranged in a staggered pattern.
(12) A step of forming a channel layer so as to be exposed on the surface of the semiconductor layer by injecting a second conductive ion into the first conductive type semiconductor layer.
A step of forming a gate trench deeper than the depth of the channel layer by etching the semiconductor layer from the surface so as to penetrate the channel layer.
A step of forming a gate insulating film on the inner surface of the gate trench and the surface of the semiconductor layer,
A step of depositing an electrode material on the gate insulating film until the gate trench is filled and the surface of the semiconductor layer is covered.
By patterning the portion of the electrode material outside the gate trench by etching, the trench portion filled in the gate trench and the end portion on the open end side of the trench portion are laterally along the surface of the semiconductor layer. And the process of forming a gate electrode that integrally includes the planar part drawn out from the
In a state where the lower portion of the planar portion of the channel layer is covered with the planar portion, the first conductive ion is injected into the channel layer through the surface of the semiconductor layer to the planar portion. On the other hand, a method for manufacturing a semiconductor device, which includes a step of forming a source layer in a self-aligned manner.
(13) In the step of forming the source layer, a part of the source layer enters below the end portion of the planar portion by a predetermined amount, so that an overlapping portion overlapping with the part of the planar portion is formed. The method for manufacturing a semiconductor device according to (12), comprising a step of obliquely injecting the first conductive type ion at an injection angle inclined with respect to the surface of the semiconductor layer.
(14) The step of forming the gate trench includes a step of forming a striped trench so that the unit cells are arranged in a stripe shape in the semiconductor layer.
The step of diagonally injecting the first conductive type ion is the first step of diagonally injecting the first conductive type ion into the stripe trench from one side in the width direction, and the first step of diagonally injecting the first conductive type ion into the stripe trench. 13. The semiconductor according to (13), which includes a second step of obliquely injecting the first conductive type ion in a direction intersecting the incident direction of the first conductive type ion in the first step from the opposite side of the injection position. Manufacturing method of the device.
(Effects of the above features to be grasped)
The semiconductor device of (1) can be manufactured by, for example, the method of manufacturing the semiconductor device of (12).

According to the inventions (1) and (12), a channel formed on the side surface portion of the channel layer by an electric field from the gate electrode and passing a current in a vertical direction along the side surface portion of the gate trench, and a surface portion of the channel layer. It is possible to form a bidirectional channel of a channel that is formed in the above direction and allows a current to flow laterally along the surface of the semiconductor layer.
The vertical channel length is determined by the depth of the side surface of the channel layer, and the lateral channel length is determined by the width of the surface of the channel layer.

In the invention of the reference example, if the channel layer is formed at the design depth based on the implantation conditions of the second conductive ion, then the channel is implanted during the first conductive ion implantation for forming the source layer. Since the side surface portion of the layer is covered with the planar portion (mask) of the gate electrode, it is not affected by the first conductive type ion. Therefore, since the depth of the side surface portion of the channel layer can be precisely maintained as designed, the channel length in the vertical direction can be precisely controlled as designed.

On the other hand, the width of the surface portion of the channel layer depends on the formation accuracy of the source layer formed next to the channel layer, but in the invention of the reference example, the planar portion of the gate electrode formed by the etching technique having excellent processing accuracy ( The source layer is self-aligned with respect to the mask). Since it is possible to prevent the source layer from excessively advancing to the surface portion of the channel layer covered with the planar portion, the width of the surface portion of the channel layer can be increased by etching the electrode material as designed to form the planar portion. It can be precisely controlled as designed. As a result, the lateral channel length can be precisely controlled as designed, as is the vertical channel length.

In the semiconductor device of the reference example, as described in (2), the source layer has an overlapping portion that enters below the end portion of the planar portion by a predetermined amount and overlaps with a part of the planar portion. Is preferable. In this case, as described in (3), the overlapping portion of the source layer may be shallower than the rest of the source layer.
According to this configuration, the surface portion of the channel layer is surely opposed to the planar portion of the gate electrode, so that highly reliable transistor operation can be performed.

Further, in the semiconductor device of the reference example, as described in (4), the depth of the source layer may be three times or less the thickness of the gate insulating film.
Further, in the semiconductor device of the reference example, as described in (5), the gate trench is a first conductive type carrier included in the semiconductor layer due to an electric field from the gate electrode when the semiconductor device is turned on. It is preferable to include a deep trench in which the accumulation layer can be formed along its side surface.

According to this configuration, a carrier storage layer having low resistance is formed in the semiconductor layer, and this carrier storage layer can be used as a current path when the semiconductor device is turned on. Therefore, the on-resistance of the semiconductor device can be lowered regardless of the inherent resistance value of the semiconductor layer. Therefore, it is possible to achieve high withstand voltage by thickening the semiconductor layer while maintaining low on-resistance.
Specifically, as described in (6), when the semiconductor layer includes a first conductive type substrate and an epitaxial layer formed on the substrate and having a lower impurity concentration than the substrate, the deep The trench preferably includes a trench that penetrates the epitaxial layer and reaches the substrate.

As a result, the carrier accumulation layer can be formed in the entire section of the epitaxial layer in the thickness direction, which has a low impurity concentration and hinders the reduction of the on-resistance, so that the effect of the reduction of the on-resistance is great.
Further, in the semiconductor device of the reference example, the thickness of the semiconductor layer may be 70 μm to 300 μm as described in (7), and the depth of the gate trench is set as described in (8). It may be 30 μm to 50 μm.

Further, the gate trench is a unit cell arranged in a stripe pattern as described in (9), a unit cell arranged in a matrix pattern as described in (10), and a unit cell arranged in a matrix pattern as described in (11). It may be formed so as to partition any form of unit cells represented by the unit cells arranged in a staggered pattern.
Further, in the method for manufacturing a semiconductor device of the reference example, as described in (13), in the step of forming the source layer, a part of the source layer enters below the end portion of the planar portion by a predetermined amount. It is preferable to include a step of obliquely injecting the first conductive ion at an injection angle inclined with respect to the surface of the semiconductor layer so that an overlapping portion overlapping with a part of the planar portion is formed.

By this method, since the first conductive type ion can be positively injected below the planar portion, the overlapping portion of the source layer can be easily formed.
Further, as described in (14), when the step of forming the gate trench includes a step of forming a striped trench so that the unit cells are arranged in a stripe shape in the semiconductor layer, the first conductive type ion The step of diagonally injecting the first conductive ion into the stripe trench from one side in the width direction is the first step, and the step of diagonally injecting the first conductive ion into the stripe trench is from the opposite side of the injection position of the first step. It is preferable to include a second step of obliquely injecting the first conductive type ion in a direction intersecting the incident direction of the first conductive type ion in the first step.

1 MOS transistor 2 Unit cell 3 Gate trench 4 Contact trench 5 Si substrate 6 (Si substrate) front surface 7 (Si substrate) back surface 8 Si epitaxial layer 9 (Si epitaxial layer) front surface 10 (Si epitaxial layer) back surface 11 Side surface (of gate trench) 12 Bottom surface (of gate trench) 13 Source area 14 Channel area 15 Drain area 16 Gate insulating film 17 Gate electrode 18 Side surface (of contact trench) 19 Bottom surface (of contact trench) 20 Channel contact area 21 Interlayer insulation Film 22 Contact hole 23 Channel part 24 Convex part 25 Top 26 SiO ₂ film 27 SiN film 28 Hardmask 29 Interface 30 Channel area 31 Convex part 32 Top 33 Top 41 MOS transistor 42 Unit cell 43 Gate trench 44 Contact trench 45 Substrate 46 ( Front surface (of substrate) 47 Back surface (of substrate) 48 epitaxial layer 49 Surface 50 (of epitaxial layer) Back surface 51 (of epitaxial layer) Side surface 52 (of gate trench) Bottom surface 53 Gate insulating film 54 Gate electrode 55 ( Trench part (of gate electrode) 56 Planer part (of gate electrode) 57 Channel layer 58 Drain layer 59 Trench corner part 60 Side part (of channel layer) 61 Surface part (of channel layer) 62 Source layer 63 Overlap part 64 Contact part 65 Side surface (of contact trench) 66 Bottom surface (of contact trench) 67 Channel contact area 68 Interlayer insulating film 69 Contact hole 70 SiO ₂ film 71 SiN film 72 Hard mask 73 Electrode material layer 74 Photoresist 75 Carrier storage layer

Claims (18)

A semiconductor layer having a first surface and a second surface,
A first trench formed on the first surface of the semiconductor layer,
A second trench formed on the first surface of the semiconductor layer,
A first region of the first conductive type, which is formed so as to be exposed on the first surface side of the semiconductor layer and forms a part of the side surface of the first trench.
A second conductive type second region formed so as to be in contact with the first region on the second surface side of the semiconductor layer with respect to the first region and forming a part of the side surface of the first trench. ,
A first conductive type third region formed so as to be in contact with the second region on the second surface side of the semiconductor layer with respect to the second region and forming the bottom surface of the first trench.
The insulating film formed on the inner surface of the first trench and
The first electrode embedded inside the insulating film in the first trench,
A third trench that is at least partially surrounded by the semiconductor layer and has a bottom surface between the first surface and the second surface of the semiconductor layer.
The second region is formed relative to the first portion formed on the first surface side of the semiconductor layer and the lower side of the first portion, and the semiconductor is formed with respect to the bottom surface of the first trench. It integrally includes a second portion protruding from the first portion to a depth located on the second surface side of the layer.
The second portion of the second region is a convex portion protruding from the vicinity of the bottom of the first trench as an end portion, and forms a curved surface between the second region and the third region.
The top of the second portion of the second region is located between the first trench and the second trench.
The distance from the top of the second portion to the first trench and the distance from the top of the second portion to the second trench are substantially the same.
The third trench is formed directly above the second portion of the second region.
The third trench includes a third portion consisting of an impurity region.
A semiconductor device, wherein the top of the second portion is formed just below the third portion and includes a top formed along a position below the widthwise end of the bottom surface of the third trench. A semiconductor layer having a first surface and a second surface,
A first trench formed on the first surface of the semiconductor layer,
A second trench formed on the first surface of the semiconductor layer,
A first region of the first conductive type, which is formed so as to be exposed on the first surface side of the semiconductor layer and forms a part of the side surface of the first trench.
A second conductive type second region formed so as to be in contact with the first region on the second surface side of the semiconductor layer with respect to the first region and forming a part of the side surface of the first trench. ,
A first conductive type third region formed so as to be in contact with the second region on the second surface side of the semiconductor layer with respect to the second region and forming the bottom surface of the first trench.
The insulating film formed on the inner surface of the first trench and
The first electrode embedded inside the insulating film in the first trench,
A third trench that is at least partially surrounded by the semiconductor layer and has a bottom surface between the first surface and the second surface of the semiconductor layer.
The second region is formed relative to the first portion formed on the first surface side of the semiconductor layer and the lower side of the first portion, and the semiconductor is formed with respect to the bottom surface of the first trench. It integrally includes a second portion protruding from the first portion to a depth located on the second surface side of the layer.
The second portion of the second region is a convex portion protruding from the vicinity of the bottom of the first trench as an end portion, and forms a curved surface between the second region and the third region.
The top of the second portion of the second region is located between the first trench and the second trench.
The distance from the top of the second portion to the first trench and the distance from the top of the second portion to the second trench are substantially the same.
The third trench is formed directly above the second portion of the second region.
The top of the second portion is a semiconductor device comprising a plurality of tops formed parallel to each other along the lower positions of the widthwise ends of the bottom surface of the third trench. A semiconductor layer having a first surface and a second surface,
A first trench formed on the first surface of the semiconductor layer,
A second trench formed on the first surface of the semiconductor layer,
A first region of the first conductive type, which is formed so as to be exposed on the first surface side of the semiconductor layer and forms a part of the side surface of the first trench.
A second conductive type second region formed so as to be in contact with the first region on the second surface side of the semiconductor layer with respect to the first region and forming a part of the side surface of the first trench. ,
A first conductive type third region formed so as to be in contact with the second region on the second surface side of the semiconductor layer with respect to the second region and forming the bottom surface of the first trench.
The insulating film formed on the inner surface of the first trench and
The first electrode embedded inside the insulating film in the first trench,
A third trench that is at least partially surrounded by the semiconductor layer and has a bottom surface between the first surface and the second surface of the semiconductor layer.
The second region is formed relative to the first portion formed on the first surface side of the semiconductor layer and the lower side of the first portion, and the semiconductor is formed with respect to the bottom surface of the first trench. It integrally includes a second portion protruding from the first portion to a depth located on the second surface side of the layer.
The second portion of the second region is a convex portion protruding from the vicinity of the bottom of the first trench as an end portion, and forms a curved surface between the second region and the third region.
The top of the second portion of the second region is located between the first trench and the second trench.
The distance from the top of the second portion to the first trench and the distance from the top of the second portion to the second trench are substantially the same.
The third trench is formed directly above the second portion of the second region.
The second portion of the second region protrudes in a plurality of parabolas.
The tops of the plurality of parabolic second portions are located below the first end in the width direction of the third trench and below the second end in the width direction of the third trench. A semiconductor device, including a second apex located. A semiconductor layer having a first surface and a second surface,
A first trench formed on the first surface of the semiconductor layer,
A second trench formed on the first surface of the semiconductor layer,
A first region of the first conductive type, which is formed so as to be exposed on the first surface side of the semiconductor layer and forms a part of the side surface of the first trench.
A second conductive type second region formed so as to be in contact with the first region on the second surface side of the semiconductor layer with respect to the first region and forming a part of the side surface of the first trench. ,
A first conductive type third region formed so as to be in contact with the second region on the second surface side of the semiconductor layer with respect to the second region and forming the bottom surface of the first trench.
The insulating film formed on the inner surface of the first trench and
The first electrode embedded inside the insulating film in the first trench,
A third trench that is at least partially surrounded by the semiconductor layer and has a bottom surface between the first surface and the second surface of the semiconductor layer.
The second region is formed relative to the first portion formed on the first surface side of the semiconductor layer and the lower side of the first portion, and the semiconductor is formed with respect to the bottom surface of the first trench. It integrally includes a second portion protruding from the first portion to a depth located on the second surface side of the layer.
The second portion of the second region is a convex portion protruding from the vicinity of the bottom of the first trench as an end portion, and forms a curved surface between the second region and the third region.
The top of the second portion of the second region is located between the first trench and the second trench.
The distance from the top of the second portion to the first trench and the distance from the top of the second portion to the second trench are substantially the same.
The third trench is formed directly above the second portion of the second region.
A semiconductor device, wherein the top of the second portion comprises a plurality of tops that are axisymmetric with respect to an axis of symmetry passing through the widthwise central portion of the bottom surface of the third trench. The semiconductor device according to any one of claims 1 to 4, further comprising an insulating layer formed so as to cover the first trench and the second trench. The semiconductor device according to claim 5, further comprising a source electrode formed so as to cover the insulating layer and the semiconductor layer. The semiconductor device according to any one of claims 2 to 4, further comprising a high-concentration impurity region formed below the third trench. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor layer includes a SiC layer. The semiconductor device according to claim 1, wherein the second portion of the second region has a width larger than the width of the third trench. The semiconductor device according to claim 1, wherein the impurity concentration of the second portion of the second region is 1/100 or less of the concentration of the third portion. The semiconductor device according to claim 3, wherein the first top and the second top are formed in parallel with each other along the third trench. The semiconductor layer includes a Si substrate and a Si epitaxial layer formed on the Si substrate and having a lower impurity concentration than the Si substrate.
The semiconductor device according to any one of claims 1 to 11, wherein the top of the second portion is not in contact with the Si substrate. The thickness of the first portion of the second region is 0.5 μm to 0.9 μm.
The semiconductor device according to any one of claims 1 to 12, wherein the thickness of the semiconductor layer from the first surface to the top of the second portion is 1.0 μm to 1.6 μm. The amount of protrusion of the first trench toward the second surface side of the semiconductor layer with respect to the interface between the first portion and the third region of the second region is 0.1 μm to 0.2 μm. The semiconductor device according to any one of claims 1 to 13. The third trench is formed in a striped shape.
The semiconductor device according to any one of claims 1 to 14, wherein the second portion of the second region is formed in a striped shape along the striped third trench. The semiconductor device according to any one of claims 1 to 15, wherein the third trench is formed shallower than the first trench. The semiconductor device according to any one of claims 1 to 16, wherein the insulating film includes a silicon oxide film. The semiconductor device according to any one of claims 1 to 17 , wherein the impurity concentration of the first portion of the second region is 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ^-3.

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