CN104425385A - Method for manufacturing embedded memory element - Google Patents
Method for manufacturing embedded memory element Download PDFInfo
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- CN104425385A CN104425385A CN201310365009.8A CN201310365009A CN104425385A CN 104425385 A CN104425385 A CN 104425385A CN 201310365009 A CN201310365009 A CN 201310365009A CN 104425385 A CN104425385 A CN 104425385A
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 239000000463 material Substances 0.000 claims description 78
- 230000001413 cellular effect Effects 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 20
- 239000011148 porous material Substances 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000004020 conductor Substances 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- -1 silica alkane Chemical class 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for manufacturing an embedded memory element. The method comprises the following steps: providing a substrate; forming a plurality of first gate structures in a unit area of the substrate; forming a second gate structure in a peripheral area of the substrate; forming a dielectric layer on the substrate in the peripheral area; forming a plurality of virtual self-aligned contact window plugs in the unit area and forming a plurality of openings around virtual self-aligned contact windows; forming a stop layer on the substrate and filling the openings with the stop layer, wherein the surface of the stop layer is provided with a plurality of depressions corresponding to the openings; forming a hard mask layer in each of the depressions; removing the hard mask layers and part of the stop layer; removing the virtual self-aligned contact window plugs to form a plurality of self-aligned contact window openings; and forming a plurality of self-aligned contact windows in the self-aligned contact window openings. By adopting the method of the invention, the problem that deep pores are formed in the position with the largest distance between two adjacent drain regions and a source region and subsequent metal fills the pores to cause short circuit of bit lines and word lines can be avoided.
Description
Technical field
The present invention relates to a kind of manufacture method of embedded memory element.
Background technology
Embedded memory element is reach to reduce costs and the demand of Simplified flowsheet step, the element of cellular zone and surrounding zone is integrated and becomes a kind of trend gradually on the same chip, such as flash memory and logic circuit component are integrated on the same chip, this kind of element is referred to as embedded flash memory (embedded flash memory).
But, existing embedded memory element is maximum distance apart between adjacent two drain regions and source area, deep pores is formed because of dielectric layer cannot be filled up, the metal level that follow-up formation is used as metal plug may fill in these some deep pores, thus the problem of derivative bit line and wordline electrical short.
Summary of the invention
The embodiment of the present invention proposes a kind of manufacture method of embedded memory element, can avoid maximum distance apart between adjacent two drain regions and source area, because cannot fill up dielectric layer and form deep pores.
The embodiment of the present invention proposes a kind of manufacture method of embedded memory element, and comprise and provide substrate, substrate comprises cellular zone and surrounding zone.The cellular zone of substrate is formed multiple first grid structure.The surrounding zone of substrate is formed second grid structure.The substrate of surrounding zone forms dielectric layer.Form multiple virtual self-aligned contacts window connector in cellular zone, and form multiple opening around virtual self-aligned contacts window.On substrate, form the first stop-layer, the first stop-layer fills in opening, wherein on the surface of above-mentioned first stop-layer of corresponding opening, has multiple depression.Hard mask layer is formed respectively in each depression.Remove hard mask layer and part first stop-layer.Remove above-mentioned virtual self-aligned contacts window connector, to form multiple self-aligned contacts window opening.Multiple self-aligned contacts window is formed in self-aligned contacts window opening.
Described in the embodiment of the present invention, the method forming described hard mask layer in above-mentioned depression comprises: on described substrate, form layer of hard mask material; And with described first stop-layer for stop layer, carry out flatening process, remove the described layer of hard mask material beyond described depression, leave the described hard mask layer in described depression.
Described in the embodiment of the present invention, the material of above-mentioned first stop-layer is different from the material of described hard mask layer.
Described in the embodiment of the present invention, above-mentioned when removing described hard mask layer and described first stop-layer of part, use for described hard mask layer: the etching selectivity of described first stop-layer is the etchant of 1:1.
Described in the embodiment of the present invention, above-mentioned virtual self-aligned contacts window comprises cap layer respectively, the material of described cap layer is identical with the material of described first stop-layer, and after described method is more included in and removes described hard mask layer and described first stop-layer of part, remove described first stop-layer of described cap layer and another part.
Described in the embodiment of the present invention, the manufacture method of above-mentioned embedded memory element more comprises the following steps: before the virtual self-aligned contacts window connector of formation and described dielectric layer, form the second stop-layer over the substrate, and after removing virtual self-aligned contacts window connector, remove described second stop-layer, to form described self-aligned contacts window opening.
Described in the embodiment of the present invention, above-mentioned when removing described first stop-layer of described cap layer and described another part, use for described cap layer: the etching selectivity of described second stop-layer is the etchant of 100:1.
Described in the embodiment of the present invention, the manufacture method of above-mentioned embedded memory element, the sidewall being more included in described virtual self-aligned contacts window connector forms clearance wall respectively.
Described in the embodiment of the present invention, the manufacture method of above-mentioned embedded memory element, the material of wherein said clearance wall is identical with the material of described first stop-layer.
Described in the embodiment of the present invention, the manufacture method of above-mentioned embedded memory element, wherein t1>a/2, t1 are the thickness of described first stop-layer; A is the distance between adjacent two drain regions.
Described in the embodiment of the present invention, said units district comprises the firstth district and the secondth district, between described first grid structure in described firstth district, there is the first gap, between described first grid structure in described secondth district, there is the second gap, described first gap is less than described second gap, the height of described first stop-layer in described second gap is lower than the height of described first stop-layer in described first gap, after described first stop-layer of formation and form described hard mask layer respectively in each described depression before, described method more comprises: the first stop-layer described in anisotropic etching, the first connected clearance wall is formed in described first gap, and the second clearance wall separated from one another is formed among described second gap, and the second stop-layer is formed in described firstth district and described secondth district, fill up described first gap and the second gap.
Described in the embodiment of the present invention, above-mentioned second stop-layer is identical with the material of described first stop-layer.
Described in the embodiment of the present invention, above-mentioned t1>a/2 and t2> (c-a)/2, wherein, t1 is the thickness of described first stop-layer; T2 is the thickness of described second stop-layer; A is the distance between adjacent two drain regions; And c is described adjacent two ultimate ranges between drain region and source area.
The embodiment of the present invention also proposes a kind of manufacture method of embedded memory element, and comprise and provide substrate, substrate comprises cellular zone, and cellular zone comprises the firstth district and the secondth district.Substrate is formed multiple first grid structure, has the first gap between the first grid structure in the firstth district, have the second gap between the first grid structure in the secondth district, the first gap is less than the second gap.Firstth district and the secondth district are formed multiple virtual self-aligned contacts window connector.On substrate, form the first stop-layer, the height of the first stop-layer wherein in the second gap is lower than the height of the first stop-layer in the first gap.Anisotropic etching first stop-layer, forms the first connected clearance wall in the first gap, and among the second gap, form the second clearance wall separated from one another.Firstth district and the secondth district form the second stop-layer, fills up the first gap and the second gap.
Described in the embodiment of the present invention, above-mentioned second stop-layer is identical with the material of described first stop-layer.
Described in the embodiment of the present invention, above-mentioned t1>a/2; And t2> (c-a)/2, wherein t1 is the thickness of described first stop-layer; T2 is the thickness of described second stop-layer; A is the distance between adjacent two drain regions; And c is described adjacent two ultimate ranges between drain region and source area.
The manufacture method of the embedded memory element of the embodiment of the present invention can avoid maximum distance apart between adjacent two drain regions and source area to form deep pores.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to 1I is the generalized section of the manufacturing process of a kind of embedded memory element illustrated according to a first embodiment of the present invention.
Fig. 2 is the source area of a kind of embedded memory element that illustrates according to the embodiment of the present invention and the vertical view of drain region.
Fig. 3 A to 3C is the generalized section of the part manufacturing process of a kind of embedded memory element illustrated according to a second embodiment of the present invention.
Fig. 4 is the image of the sweep electron microscope of existing a kind of embedded memory element.
Fig. 5 is the image of the sweep electron microscope of the embedded memory element of second embodiment of the invention.
Description of reference numerals
10: the first districts of district 20: the second
100: substrate 100a: cellular zone
100b: surrounding zone 102,110: grid structure
103: tunnel oxide 104,106,112: conductor layer
105: gate dielectric layer 107,113: metal silicide layer
108,114: lower mask layer 109: upper mask layer
111: grid oxic horizon 115: mask layer
116,120,132,133: stop-layer
117: lining 118,119,132a, 132b: clearance wall
122: dielectric layer 124: conductor layer
125: mask layer 126: cap layer
127: virtual self-aligned contacts window connector
128: opening 130: clearance wall
133: stop-layer 134: depression
136: layer of hard mask material 136a: hard mask layer
140: opening 142: self-aligned contacts window opening
144: barrier layer metal level 146: conductor metal layer
148: self-aligned contacts window 150: drain region
160: source area 162,164: gap
166: hole a, c: distance
Embodiment
Figure 1A to 1I is the generalized section of the manufacturing process of embedded memory element illustrated according to a first embodiment of the present invention.Fig. 2 is the source area of embedded memory element that illustrates according to one embodiment of the invention and the vertical view of drain region.
Please refer to Figure 1A, substrate 100 is provided.Substrate 100 can be semiconductor or semiconducting compound, such as, be silicon or germanium silicide.Substrate 10 also can be silicon on insulating barrier (SOI).Substrate 100 has cellular zone 100a and surrounding zone 100b.On the substrate 100 of cellular zone 100a, form multiple grid structure 102, and on the substrate 100 of surrounding zone 100b, form at least one grid structure 110.
Grid structure 102 can be the grid structure of non-volatile memory device, such as, be the grid structure of flash memory devices, is such as to comprise sequentially stacking tunnel oxide 103, conductor layer 104, gate dielectric layer 105 and conductor layer 106 on the substrate 100.The material of tunnel oxide 103 is such as silica.Conductor layer 104 is as floating grid, and its material is such as doped polycrystalline silicon.Gate dielectric layer 105 is such as silica, silicon nitride and silica (ONO) composite bed.Conductor layer 106 is as control gate, and its material is such as doped polycrystalline silicon.In addition, grid structure 110 comprises sequentially stacking gate dielectric 111 on the substrate 100 and conductor layer 112.Conductor layer 112 is as the grid of logic element, and its material is such as doped polycrystalline silicon.
Form grid structure 102 to comprise the following steps with the method for grid structure 110.First, the substrate 100 respectively at cellular zone 100a and surrounding zone 100b is formed different stacked material layers (not illustrating).In specific words, sequentially stacking tunnel oxide material layer, the first conductor material layer, inter-gate dielectric material layer and the second conductor material layer on the cellular zone 100a of substrate 100, and on the surrounding zone 100b of substrate 100 sequentially piled grids layer of oxidized material and the second conductor material layer, the second conductor material layer wherein on cellular zone 100a and surrounding zone 100b is formed simultaneously.Then, ion implantation technology is carried out to the second conductor material layer on the 100a of cellular zone.Afterwards, at least one patterning step is carried out to above-mentioned material layer, to form grid structure 102 and form grid structure 110 on the substrate 100 of cellular zone 100a on the substrate 100 of surrounding zone 100b.
In one embodiment, grid structure 102 more can comprise the metal silicide layer 107 be sequentially stacked on conductor layer 106, lower mask layer 108 and upper mask layer 109.Grid structure 110 more can comprise the metal silicide layer 113 be sequentially stacked on conductor layer 112, lower mask layer 114 and upper mask layer 115.Formation metal silicide layer 107 and metal silicide layer 113 are the resistances in order to reduce conductor layer 106 and conductor layer 112 respectively.Metal silicide layer 107 is identical with the material of metal silicide layer 113, such as, be tungsten silicide.
In addition, formed lower mask layer 108 and upper mask layer 109 be in order to pull open wordline (by conductor layer 106 and on metal silicide layer 107 form) and the follow-up bit line formed between beeline.Lower mask layer 108 is identical with the material of lower mask layer 114, such as, be silicon nitride.Upper mask layer 109 is identical with the material of upper mask layer 115, such as, be the silicon dioxide (TEOS-SiO2) that tetraethoxy silica alkane is formed.In this embodiment, be described for bilayer mask Rotating fields, but the present invention is not as limit.In other embodiments, also can use individual layer or be greater than two-layer mask layer structure.
Be noted that especially and be illustrated for the grid structure 110 of formation on the 100b of surrounding zone in figure ia, but the present invention is not as limit.In other embodiments, surrounding zone 100b can be formed multiple grid structure 110, surrounding zone 100b can have high voltage device district and low voltage component district (not illustrating), and the gate dielectric be formed in high voltage device district and low voltage component district has different thickness.
In addition, in figure ia, cellular zone 100a illustrates with the grid structure 102 of flash memory, but, the present invention is not as limit, grid structure 102 on the 100a of cellular zone also can be the grid structure of other nonvolatile memory, and such as conductor layer 104 can be replaced by the electric charge storage layer made with dielectric layer.
Then, continue referring to Figure 1A, on substrate 100, form lining 117 to compliance, with overlies gate structure 102 and grid structure 110.The material of lining 117 is such as high-temperature oxide (high-temperature oxide, HTO), and its formation method is such as carry out chemical vapor deposition method.In one embodiment, after the step forming grid structure 102 and grid structure 110 and before the step forming lining 117, also at least one ion implantation step can be carried out, to form multiple light doping section (not illustrating) in the substrate 100 of cellular zone 100a, and form multiple light doping section (not illustrating) in the substrate 100 in the high voltage device district of surrounding zone 100b.
Then, on each grid structure 102 with the sidewall of grid structure 110, clearance wall 118 is formed.The material of clearance wall 118 is such as silicon nitride.The method forming clearance wall 118 is included on substrate 100 and deposits spacer material layer (not illustrating).Then, carry out anisotropic etching process, to remove portion gap wall material layer.(do not illustrate) in one embodiment, the above-mentioned step removing portion gap wall material layer also can remove the part lining 117 between grid structure simultaneously.
Afterwards, please refer to Figure 1A, on substrate 100, form stop-layer 116 to compliance, with overlies gate structure 102 and grid structure 110.The material of stop-layer 116 is such as the silicon dioxide (TEOS-SiO that tetraethoxy silica alkane is formed
2), and its formation method is such as carry out chemical vapor deposition method.In one embodiment, after the step forming clearance wall 118 and before the step forming stop-layer 116, also at least one ion implantation step can be carried out, in the substrate 100 of cellular zone 100a, form multiple heavily doped region (not illustrating), and form multiple light doping section (not illustrating) in the substrate 100 in the low voltage component district of surrounding zone 100b.
Thereafter, please refer to Figure 1B, the sidewall of stop-layer 116 on grid structure 110 sidewall can form clearance wall 119.The material of clearance wall 119 is such as silicon nitride, and the method for formation is such as chemical vapour deposition technique, and thickness is such as 20nm to 200nm.The method forming clearance wall 119 is included on substrate 100 and deposits spacer material layer (not illustrating).Then, carry out anisotropic etching process, to remove portion gap wall material layer.Afterwards, on substrate 100, form conductor layer 124, also at least fill up the gap between grid structure 102 with overlies gate structure 110.The material of conductor layer 124 is such as polysilicon, and its method formed is such as carry out chemical vapor deposition method, and thickness is such as about 60 nanometers.Afterwards, selectivity can carry out flatening process to conductor layer 124, make conductor layer 124 have smooth surface.Afterwards, cellular zone 100a forms mask layer 125, expose the conductor layer 124 on the 100b of surrounding zone.Mask layer 125 is such as photoresist oxidant layer.
Please refer to Fig. 1 C, with mask layer 125 for etching mask, patterning conductor layer 124, removes the conductor layer 124 on the 100b of surrounding zone, exposes stop-layer 116.Afterwards, mask layer 125 is removed.Then, stop-layer 120, the conductor layer 124 of capping unit district 100a and first stop-layer 116 of surrounding zone 100b is formed on the substrate 100.The material of stop-layer 120 is such as silicon nitride, and the method for formation is such as chemical vapour deposition technique, and thickness is such as 20nm to 200nm.Afterwards, the stop-layer 120 of surrounding zone 100b forms dielectric layer 122.The material of dielectric layer 122 is such as spin-on glasses, its formation method profit spin-coating method in this way.The material of dielectric layer 122 can be such as silica, and its formation method is such as chemical vapour deposition technique.Afterwards, with the stop-layer 120 on the 100a of cellular zone for polishing stop layer, CMP (Chemical Mechanical Polishing) process is utilized to carry out flatening process to the dielectric layer 122 on the 100b of surrounding zone.
Afterwards, please refer to Fig. 1 D, remove the stop-layer 120 on the 100a of cellular zone.Then, cap layer 126, the conductor layer 124 on capping unit district 100a and the dielectric layer 122 on the 100b of surrounding zone is formed on the substrate 100.The material of cap layer 126 is such as silicon nitride, and the method for formation is such as plasma enhanced chemical vapor deposition method, and thickness can be 100nm to 300nm.
Afterwards, please refer to Fig. 1 E, utilize photoetching and etch process, with stop-layer 116 for stop layer, patterning cap layer 126 and conductor layer 124, to form virtual self-aligned contacts window connector 127 at cellular zone 100a, and form opening 128 around virtual self-aligned contacts window connector 127.Afterwards, selectivity clearance wall 130 can be formed at the sidewall of virtual self-aligned contacts window connector 127.The material of clearance wall 130 is such as silicon nitride, and thickness is such as 5nm to 20nm.The method forming clearance wall 130 is included on substrate 100 and deposits spacer material layer (not illustrating).Then, carry out anisotropic etching process, to remove portion gap wall material layer.
Afterwards, please refer to Fig. 1 F, form stop-layer 132 on the substrate 100.The material of stop-layer 132 can adopt the material identical with cap layer 126, such as, be silicon nitride, and the method for formation is such as chemical vapour deposition technique.Stop-layer 132 covers cap layer 126 and fills in opening 128.Please refer to Fig. 2, the distance between adjacent two drain regions 150 is a, and between adjacent two drain regions 150 and source area 160, ultimate range is c, and c>a.In the present embodiment, the thickness t1 of the stop-layer 132 of Fig. 1 F is greater than 1/2 of the distance a between adjacent two drain regions 150, such as, be 30nm to 100nm.Because the thickness t1 of stop-layer 132 is greater than 1/2 of the distance a between adjacent two drain regions 150, therefore, the gap between adjacent two drain regions 150 can be filled up, if but thickness does not reach 1/2 of ultimate range c between adjacent two drain regions 150 and source area 160, adjacent two drain regions 150 and gap each other, source area 160 cannot be stopped layer 132 and fill up, and the diameter leaving hole is less than c-a, namely radius is less than (c-a)/2.And this hole can be filled up by the layer of hard mask material 136 of follow-up formation.
In addition, please refer to Fig. 1 F, the surface of stop-layer 132 has height to rise and fall because of the structure on substrate 100 or material layer, have multiple depression 134 in corresponding opening 128 part.In one embodiment, the degree of depth of depression 134 is such as 600 dusts.
Then, continue referring to Fig. 1 F, layer of hard mask material 136 is formed on the substrate 100.The material of layer of hard mask material 136 is different from stop-layer 132, such as, be the silicon dioxide (TEOS-SiO2) that tetraethoxy silica alkane is formed, and its formation method is such as carry out chemical vapor deposition method.
Please refer to Fig. 2, more particularly, layer of hard mask material 136 can fill up depression 134 (Fig. 1 F), and its thickness t2 is greater than the half (a/2) of the distance (a) between adjacent two drain regions 150, and be greater than the half ((c-a)/2) that ultimate range (c) between adjacent two drain regions 150 and source area 160 deducts the distance (a) between adjacent two drain regions 150, be such as 100nm to 200nm.In one embodiment, the degree of depth of depression 134 is such as 600 dusts, and the thickness of layer of hard mask material 136 is such as 1000 dusts.The thickness t1 of stop-layer 132 is greater than a/2, and adjacent two drain regions 150 and source area 160 are each other because cannot be stopped that layer 132 fills up and the radius of hole that stays is less than (c-a)/2, because the thickness t2 of layer of hard mask material 136 is greater than (c-a)/2, the hole that therefore radius can be less than (c-a)/2 fills up.
Thereafter, please refer to Fig. 1 G, with stop-layer 132 for stop layer, carry out flatening process, remove the layer of hard mask material 136 beyond depression 134, leave the hard mask layer 136a among depression 134, the hard mask layer 136a stayed and stop-layer 132 have smooth surface.Flatening process can adopt CMP (Chemical Mechanical Polishing) process to implement.
Afterwards, please refer to Fig. 1 H, remove hard mask layer 136a, the stop-layer 132 of part and the cap layer 126 of virtual self-aligned contacts window connector 127, remove the conductor layer 124 of virtual self-aligned contacts window connector 127 afterwards again, to form opening 140.In one embodiment, the material of hard mask layer 136a is different from the material of stop-layer 132, and the material of cap layer 126 is identical with the material of stop-layer 132, therefore etchant hard mask layer 136a/ stop-layer 132 to roughly the same rate of etch can be selected, it is such as hard mask layer 136a: the etchant of stop-layer 132=1:1, etch hard mask layer 136a and stop-layer 132, then etch cap layer 126 and stop-layer 132 around thereof downwards with identical etchant.In one embodiment, the degree of depth that the surface of self-stopping technology layer 132 etches downwards is such as that 1000 Izods are right.Thereafter, select again for stop-layer 132/ stop-layer 116, to there is high etching selectivity and cap layer 126/ stop-layer 116 is had to the etchant of high etching selectivity, such as stop-layer 132: stop-layer 116=100:1 and for cap layer 126: the etchant of stop-layer 116=100:1 etches, and leaves the stop-layer 132a above grid structure 102 and clearance wall 130.Then, then change etchant, with stop-layer 116 for stop layer, down etching removes conductor layer 124, to form opening 140, exposes stop-layer 116.
Afterwards, please refer to Fig. 1 I, remove the lining 117 of the exposed stop-layer of opening 140 116 and below thereof, to form self-aligned contacts window opening 142, barrier layer metal level 144 and conductor metal layer 146 is inserted, to form self-aligned contacts window 148 etc. technique again in self-aligned contacts window opening 142.The material of barrier layer metal level 144 is such as titanium or titanium nitride, and the method profit chemical vapour deposition technique in this way of formation, thickness is such as 5nm to 30nm.The material of conductor metal layer 146 is such as tungsten, and the method profit chemical vapour deposition technique in this way of formation, thickness is such as 100nm to 300nm.These some follow-up steps are well known to the skilled person, and repeat no more in this.
In the above-described embodiment, please refer to Fig. 1 F, after forming stop-layer 132 on the substrate 100, namely form layer of hard mask material 136.But the present invention is not as limit.After formation stop-layer 132, during the height big rise and fall on stop-layer 132 surface, other step can also be comprised between the step forming stop-layer 132 and layer of hard mask material 136, rise and fall to reduce height, avoid hole to be formed.
Fig. 3 A to 3C is the generalized section of the part manufacturing process of embedded memory element illustrated according to a second embodiment of the present invention.
Please refer to Fig. 3 A, the method according to above-described embodiment proceeds to the stop-layer 132 forming Fig. 1 F.For simplifying accompanying drawing, at Fig. 3 A to Fig. 3 C, only showing another direction of the cellular zone 100a of substrate 100, and not showing the surrounding zone 100b of dummy contact window connector 27 and Fig. 1 F.Substrate 100 comprises the first district 10 and the second district 20.Distance in first district 10 between two adjacent grid structures 102 to be less than in the second district 20 distance between two adjacent grid structures 102.The thickness t1 of stop-layer 132 is greater than the half (a/2) of the distance (a) in Fig. 2 between adjacent two drain regions 150, such as, be 30nm to 100nm.Because the gap 162 between the grid structure 102 that two in the first district 10 are adjacent is less than the gap 164 between two of the second district 20 adjacent grid structures 102, and the thickness of stop-layer 132 is not enough to fill up the gap 164 between the adjacent grid structure 102 of two of the second district 20, therefore, the height of the stop-layer 132 inserted in gap 164 can lower than the height of the stop-layer 132 inserted in gap 162.
Afterwards, please refer to Fig. 3 B, anisotropy etch-back stop-layer 132.In the second district 20, the thinner thickness of the stop-layer 132 bottom the gap 164 between distant two adjacent grid structures 102, is thus removed, and in the second gap 164, form two clearance wall 132b be separated.And in the first district 10, then because the thickness of stop-layer 132 is thicker, therefore, after anisotropy etch-back in gap 162 between the grid structure 102 that two of close together are adjacent, form two connected clearance wall 132a, and do not expose the bottom in gap 162.
Thereafter please refer to Fig. 3 C, form stop-layer 133 on the substrate 100, cover on the stop-layer 116 above grid structure 102 and on clearance wall 132a and clearance wall 132b, and fill up gap 162 and 164.The material of stop-layer 133 can be identical with the material of stop-layer 132 or different.In the present embodiment, the material of stop-layer 133 and the material of stop-layer 132 can be all silicon nitride, and the method for formation is such as chemical vapour deposition technique.The thickness of stop-layer 133 is greater than ultimate range c between adjacent two drain regions 150 in Fig. 2 and source area 160 and deducts the half ((c-a)/2) of the distance a between adjacent two drain regions 150, such as, be 30nm to 100nm.Stop-layer 133 can fill up gap 162 and 164, avoids hole to be formed, and can reduce the high low head on substrate 100 surface.
Follow-up step such as Fig. 1 F forms the step of layer of hard mask material 136, more then completes the making of in-line memory according to the step of Fig. 1 G to 1I.
Fig. 4 is the image of the sweep electron microscope of existing a kind of embedded memory element.Fig. 5 is the image of the sweep electron microscope of the embedded memory element of second embodiment of the invention.
Please refer to Fig. 4, existing embedded memory element is maximum distance apart between adjacent two drain regions and source area, because cannot dielectric layer be filled up, and cause the surface of dielectric layer to form hole 166, the metal level causing follow-up formation to be used as metal plug may fill in this some holes gap, causes the problem of bit line and wordline electrical short.
Please refer to Fig. 5, according to embedded memory element maximum distance apart between adjacent two drain regions and source area of above-mentioned second embodiment of the present invention, because utilize the mode of repeated deposition and etch-back, gap between grid structure is filled because forming clearance wall and stop-layer, hole therefore can not be had to be formed the problem that derives.
Described in the embodiment of the present invention, the present invention can avoid maximum distance apart between adjacent two drain regions and source area to form hole, avoids follow-up metal to insert among hole, and causes the problem of bit line and wordline short circuit.
Although the present invention with embodiment openly as above; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore being as the criterion of defining with claims of protection scope of the present invention.
Claims (16)
1. a manufacture method for embedded memory element, is characterized in that comprising:
There is provided substrate, described substrate comprises cellular zone and surrounding zone;
The described cellular zone of described substrate forms multiple first grid structure;
The surrounding zone of described substrate is formed second grid structure;
The described substrate of described surrounding zone forms dielectric layer;
Form multiple virtual self-aligned contacts window connector in described cellular zone, and form multiple opening around described virtual self-aligned contacts window;
On described substrate, form the first stop-layer, described first stop-layer fills in described opening, wherein on the surface of described first stop-layer of the described opening of correspondence, has multiple depression;
Hard mask layer is formed respectively in each described depression;
Remove described hard mask layer and described first stop-layer of part;
Remove described virtual self-aligned contacts window connector, to form multiple self-aligned contacts window opening; And
Multiple self-aligned contacts window is formed in described self-aligned contacts window opening.
2. the manufacture method of embedded memory element as claimed in claim 1, the method wherein forming described hard mask layer in described depression comprises:
Layer of hard mask material is formed on described substrate; And
With described first stop-layer for stop layer, carry out flatening process, remove the described layer of hard mask material beyond described depression, leave the described hard mask layer in described depression.
3. the manufacture method of embedded memory element as claimed in claim 1, the material of wherein said first stop-layer is different from the material of described hard mask layer.
4. the manufacture method of embedded memory element as claimed in claim 2, wherein when removing described hard mask layer and described first stop-layer of part, uses for described hard mask layer: the etching selectivity of described first stop-layer is the etchant of 1:1.
5. the manufacture method of embedded memory element as claimed in claim 4, wherein said virtual self-aligned contacts window comprises cap layer respectively, the material of described cap layer is identical with the material of described first stop-layer, and after described method is more included in and removes described hard mask layer and described first stop-layer of part, remove described first stop-layer of described cap layer and another part.
6. the manufacture method of embedded memory element as claimed in claim 5, more comprises the following steps:
Before the virtual self-aligned contacts window connector of formation and described dielectric layer, form the second stop-layer over the substrate, and after removing virtual self-aligned contacts window connector, remove described second stop-layer, to form described self-aligned contacts window opening.
7. the manufacture method of embedded memory element as claimed in claim 6, wherein when removing described first stop-layer of described cap layer and described another part, use for described cap layer: the etching selectivity of described second stop-layer is the etchant of 100:1.
8. the manufacture method of embedded memory element as claimed in claim 1, the sidewall being more included in described virtual self-aligned contacts window connector forms clearance wall respectively.
9. the manufacture method of embedded memory element as claimed in claim 8, the material of wherein said clearance wall is identical with the material of described first stop-layer.
10. the manufacture method of embedded memory element as claimed in claim 1, wherein t1>a/2, t1 are the thickness of described first stop-layer; A is the distance between adjacent two drain regions.
The manufacture method of 11. embedded memory elements as claimed in claim 1, wherein said cellular zone comprises the firstth district and the secondth district, between described first grid structure in described firstth district, there is the first gap, between described first grid structure in described secondth district, there is the second gap, described first gap is less than described second gap, the height of described first stop-layer in described second gap is lower than the height of described first stop-layer in described first gap, after described first stop-layer of formation and form described hard mask layer respectively in each described depression before, described method more comprises:
First stop-layer described in anisotropic etching, forms the first connected clearance wall in described first gap, and forms the second clearance wall separated from one another among described second gap; And
Described firstth district and described secondth district form the second stop-layer, fills up described first gap and the second gap.
The manufacture method of 12. embedded memory elements as claimed in claim 11, wherein said second stop-layer is identical with the material of described first stop-layer.
The manufacture method of 13. embedded memory elements as claimed in claim 11, wherein t1>a/2 and t2> (c-a)/2,
Wherein,
T1 is the thickness of described first stop-layer;
T2 is the thickness of described second stop-layer;
A is the distance between adjacent two drain regions; And
C is described adjacent two ultimate ranges between drain region and source area.
The manufacture method of 14. 1 kinds of embedded memory elements, is characterized in that comprising:
There is provided substrate, described substrate comprises cellular zone, and described cellular zone comprises the firstth district and the secondth district;
Form multiple first grid structure over the substrate, have the first gap between the described first grid structure in described firstth district, have the second gap between the described first grid structure in described secondth district, described first gap is less than described second gap;
Described firstth district and described secondth district are formed multiple virtual self-aligned contacts window connector;
On described substrate, form the first stop-layer, the height of described first stop-layer wherein in described second gap is lower than the height of described first stop-layer in described first gap;
First stop-layer described in anisotropic etching, forms the first connected clearance wall in described first gap, and forms the second clearance wall separated from one another among described second gap; And
Described firstth district and described secondth district form the second stop-layer, fills up described first gap and described second gap.
The manufacture method of 15. embedded memory elements as claimed in claim 14, wherein said second stop-layer is identical with the material of described first stop-layer.
The manufacture method of 16. embedded memory elements as claimed in claim 14, wherein t1>a/2; And t2> (c-a)/2,
Wherein t1 is the thickness of described first stop-layer;
T2 is the thickness of described second stop-layer;
A is the distance between adjacent two drain regions; And
C is described adjacent two ultimate ranges between drain region and source area.
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