CN110875314A - Bit line structure, preparation method thereof and memory - Google Patents
Bit line structure, preparation method thereof and memory Download PDFInfo
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- CN110875314A CN110875314A CN201811003601.2A CN201811003601A CN110875314A CN 110875314 A CN110875314 A CN 110875314A CN 201811003601 A CN201811003601 A CN 201811003601A CN 110875314 A CN110875314 A CN 110875314A
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- 238000002360 preparation method Methods 0.000 title description 5
- 239000000463 material Substances 0.000 claims abstract description 168
- 238000002955 isolation Methods 0.000 claims abstract description 113
- 239000011810 insulating material Substances 0.000 claims abstract description 87
- 239000002861 polymer material Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000011148 porous material Substances 0.000 claims abstract description 23
- 238000000137 annealing Methods 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 50
- 239000007789 gas Substances 0.000 claims description 38
- 125000006850 spacer group Chemical group 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000354 decomposition reaction Methods 0.000 claims description 4
- 239000004793 Polystyrene Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 3
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 3
- 229920005553 polystyrene-acrylate Polymers 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 12
- 239000012774 insulation material Substances 0.000 description 9
- 238000003860 storage Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a bit line structure, a forming method thereof and a memory, wherein the method comprises the following steps: the method comprises the steps of forming a plurality of bit lines which are arranged at intervals on a substrate, forming isolation material layers on the tops and the side walls of the bit lines, forming a high polymer material layer on the portions, corresponding to the side walls of the bit lines, of the isolation material layers, then forming a porous insulating material layer on the high polymer material layer and the isolation material layers, finally performing a high-temperature annealing process to decompose the high polymer material layer into gas, isolating the gas by the isolation material layers to protect the bit lines and the substrate, and enabling the gas to escape through a plurality of pores in the porous insulating material layer, so that air gaps are formed on the portions, corresponding to the side walls of the bit lines, of the isolation material layers, and the air gaps can.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a bit line structure, a preparation method of the bit line structure and a memory.
Background
A memory typically includes a storage capacitor for storing charge representative of stored information, and a storage transistor connected to the storage capacitor. The memory transistor has formed therein a source region, a drain region, and a gate electrode for controlling a current flow between the source region and the drain region and connected to a word line, the source region for constituting a bit line contact region to be connected to a bit line, and the drain region for constituting a storage node contact region to be connected to a storage capacitor.
With the increasing integration of semiconductor fabrication processes, the integration density of memory devices has been increased, and the integration density of bit lines has also been increased. However, as the pitch between bit lines becomes smaller, the parasitic capacitance between bit lines has a greater and greater influence on device performance.
Disclosure of Invention
The invention aims to provide a bit line structure, a preparation method thereof and a memory, which can reduce parasitic capacitance between bit lines and improve the performance of a device.
To solve the above technical problem, the present invention provides a method for forming a bit line structure, including:
providing a substrate, wherein a plurality of bit lines are formed on the substrate and are arranged at intervals;
forming a layer of isolation material on the substrate and the bit lines, the layer of isolation material covering the tops and sidewalls of the bit lines;
forming a high molecular polymer material layer on the isolation material layer, wherein the high molecular polymer material layer covers the part, corresponding to the side wall of the bit line, of the isolation material layer, so that the high molecular polymer material layer covers the side wall of the bit line at intervals of the isolation material layer;
forming a porous insulating material layer on the isolation material layer and the high molecular polymer material layer, wherein the porous insulating material layer covers the high molecular polymer material layer and the isolation material layer;
and performing a high-temperature annealing process to decompose the high-molecular polymer material layer into gas, wherein the isolating material layer isolates the gas and allows the gas to escape from the porous insulating material layer to define air gaps on the parts, corresponding to the side walls of the bit line, of the isolating material layer, wherein the air gaps are positioned on two sides of the bit line and between the isolating material layer and the porous insulating material layer.
Optionally, the material of the polymer material layer includes polystyrene or polymethyl methacrylate, and the gas generated by decomposition of the polymer material layer includes CO2、H2O、NH3。
Optionally, the material of the isolation material layer includes silicon nitride, silicon oxynitride, or silicon dioxide, and the material of the porous insulation material layer includes mesoporous silicon dioxide.
Optionally, the method for forming the isolation material layer includes an atomic layer deposition method; the method of forming the porous insulating material layer includes a chemical vapor deposition method or an atomic layer deposition method.
Optionally, the step of forming the polymer material layer includes:
forming a high molecular polymer material layer on the isolation material layer, wherein the high molecular polymer material layer covers the isolation material layer;
etching the high molecular polymer material layer, only reserving a part of the high molecular polymer material layer on the side wall of the bit line, and exposing a first part of the isolation material layer on the bit line and a second part on the substrate; when the porous insulating material layer is formed, the porous insulating material layer covers the first portion and the second portion of the spacer material layer, and the portion of the high molecular polymer material layer remaining on the bit line sidewall.
Optionally, the method for forming the high molecular polymer material layer comprises a spin coating method; the method for etching the high polymer material layer comprises plasma etching.
Optionally, the temperature of the high temperature annealing process is greater than 350 ℃, and oxygen is introduced during the high temperature annealing process.
Optionally, after forming the air gap, the method further includes: and forming a bit line isolation layer on the porous insulating material layer, wherein the bit line isolation layer covers the porous insulating material layer and fills gaps between adjacent bit lines, and the bit line isolation layer is made of silicon dioxide.
Optionally, the bit line includes a first conductive material layer, a second conductive material layer and a protective material layer sequentially formed on the substrate, the first conductive material layer includes doped polysilicon, the second conductive material layer includes titanium or titanium nitride or tungsten, and the protective material layer includes silicon nitride or silicon oxynitride or silicon dioxide.
Based on the above memory manufacturing method, the present invention further provides a bit line structure, including:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals;
the isolation material layer is positioned on the substrate and the bit line, and covers the top and the side wall of the bit line;
a layer of porous insulating material on the layer of separator material, the layer of porous insulating material covering the layer of separator material and having a plurality of pores therein;
air gaps on both sides of the bit lines between the layer of spacer material and the layer of porous insulating material, the air gaps in communication with the plurality of pores in the layer of porous insulating material.
Optionally, the memory cell further comprises a bit line isolation layer, wherein the bit line isolation layer covers the porous insulating material layer and fills gaps between adjacent bit lines.
Optionally, the isolation material layer is made of silicon nitride or silicon oxynitride or silicon dioxide, the porous insulation material layer is made of mesoporous silicon dioxide, and the bit line isolation layer is made of silicon dioxide.
Optionally, the bit line includes a first conductive material layer, a second conductive material layer and a protective material layer sequentially located on the substrate, the first conductive material layer includes doped polysilicon, the second conductive material layer includes titanium or titanium nitride or tungsten, and the protective material layer includes silicon nitride or silicon oxynitride or silicon dioxide.
Optionally, the spacer material layer has a first portion on the bit line and a second portion on the substrate, and the porous insulating material layer covers the first portion and the second portion of the spacer material layer to cover the air gaps.
The present invention also provides a memory comprising:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals;
the isolation material layer is positioned on the substrate and the bit line, and covers the top and the side wall of the bit line;
a layer of porous insulating material on the layer of separator material, the layer of porous insulating material covering the layer of separator material and having a plurality of pores therein;
air gaps on both sides of the bit lines between the layer of spacer material and the layer of porous insulating material, the air gaps in communication with the plurality of pores in the layer of porous insulating material.
In the bit line structure, the manufacturing method thereof and the memory provided by the invention, a plurality of bit lines arranged at intervals are formed on a substrate, isolation material layers are formed on the top and the side walls of the bit lines, a high molecular polymer material layer is formed on the isolation material layer corresponding to the side walls of the bit lines, then a porous insulating material layer is formed on the high molecular polymer material layer and the isolation material layer, finally a high temperature annealing process is carried out to decompose the high molecular polymer material layer into gas, the isolation material layer isolates the gas to protect the bit lines and the substrate, and the gas is enabled to escape through a plurality of pores in the porous insulating material layer, so that air gaps are formed on the isolation material layer corresponding to the side walls of the bit lines, the air gaps are positioned at two sides of the bit lines and between the isolation material layer and the porous insulating material layer, the air gap can reduce the parasitic capacitance between bit lines and improve the performance of the device.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for fabricating a bit line structure according to an embodiment of the invention;
FIG. 2 is a cross-sectional view of an embodiment of the present invention during steps S100 and S200;
FIGS. 3 and 4 are cross-sectional views illustrating the process of performing step S300 according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of an embodiment of the present invention during the execution of step S400;
FIG. 6 is a cross-sectional view of an embodiment of the present invention during the step S500;
FIG. 7 is a cross-sectional view illustrating the formation of a bit line insulating layer according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
20-a substrate;
21-bit line; 211-a first layer of conductive material; 212-a second layer of conductive material; 213-a layer of protective material;
22-a layer of isolating material; 22 a-first site; 22 b-a second site;
23-a layer of high molecular polymer material; 23' -an air gap;
24-a layer of porous insulating material;
25-bit line spacers.
Detailed Description
The core idea of the invention is to provide a bit line structure, a manufacturing method thereof and a memory, so as to reduce parasitic capacitance between bit lines and improve performance of a device.
Referring to fig. 1, the method for manufacturing the bit line structure mainly includes the following steps:
step S100, providing a substrate, wherein a plurality of bit lines are formed on the substrate and are arranged at intervals;
step S200, forming an isolation material layer on the substrate and the bit line, wherein the isolation material layer covers the top and the side wall of the bit line;
step S300, forming a high molecular polymer material layer on the isolation material layer, where the high molecular polymer material layer covers a portion of the isolation material layer corresponding to the sidewall of the bit line, so that the high molecular polymer material layer covers the sidewall of the bit line at an interval from the isolation material layer;
step S400, forming a porous insulating material layer on the isolation material layer and the high molecular polymer material layer, wherein the porous insulating material layer covers the high molecular polymer material layer and the isolation material layer;
step S500, performing a high temperature annealing process to decompose the polymer material layer into a gas, wherein the spacer material layer isolates the gas and allows the gas to escape from the porous insulating material layer, so as to define air gaps on portions of the spacer material layer corresponding to sidewalls of the bit line, wherein the air gaps are located on both sides of the bit line and between the spacer material layer and the porous insulating material layer.
Referring to fig. 7, the bit line structure includes:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals;
the isolation material layer is positioned on the substrate and the bit line, and covers the top and the side wall of the bit line;
a layer of porous insulating material on the layer of separator material, the layer of porous insulating material covering the layer of separator material and having a plurality of pores therein;
air gaps on both sides of the bit lines between the layer of spacer material and the layer of porous insulating material, the air gaps in communication with the plurality of pores in the layer of porous insulating material.
In addition, the invention also provides a memory comprising the bit line structure.
In the bit line structure, the preparation method thereof and the memory provided by the invention, a plurality of bit lines arranged at intervals are formed on a substrate, isolation material layers are formed on the top and the side walls of the bit lines, high molecular polymer material layers are formed on the portions, corresponding to the side walls of the bit lines, of the isolation material layers, then porous insulation material layers are formed on the high molecular polymer material layers and the isolation material layers, finally, a high-temperature annealing process is carried out to decompose the high molecular polymer material layers into gas, the isolation material layers isolate the gas to protect the bit lines and the substrate, and the gas is enabled to escape through a plurality of pores in the porous insulation material layers, so that air gaps are formed on the portions, corresponding to the side walls of the bit lines, of the isolation material layers, the air gaps are positioned at two sides of the bit lines and between the isolation, the air gap can reduce the parasitic capacitance between bit lines and improve the performance of the device.
The bit line structure, the fabrication thereof, and the memory method according to the present invention are further described in detail with reference to the accompanying drawings and the embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a cross-sectional view illustrating the process of performing steps S100 and S200 according to an embodiment of the present invention. Referring to fig. 2, in step S100, a substrate 20 is provided, a plurality of bit lines 21 are formed on the substrate 20, and the bit lines 21 are arranged at intervals.
The substrate 20 may be single crystal silicon, polysilicon, amorphous silicon, silicon germanium compound, silicon-on-insulator (SOI), or the like, or other materials known to those skilled in the art. Active regions, isolation structures, word lines, bit line contacts and the like can be formed in the substrate 20, the active regions are arranged in an array, the isolation structures are located on the periphery of the active regions and used for isolating the adjacent active regions, the word lines are buried word lines and intersect with the active regions, and the surfaces of the word lines are not higher than the surface of the substrate 20. Since the structure before forming the bit lines is well known to those skilled in the art, it will not be described in detail herein.
The bit line 21 includes a first conductive material layer 211, a second conductive material layer 212 and a protection material layer 213 sequentially formed on the substrate 20, wherein the first conductive material layer 211 includes but is not limited to doped polysilicon, the second conductive material layer 212 includes but is not limited to titanium or titanium nitride or tungsten, and the protection material layer 213 includes but is not limited to silicon nitride or silicon oxynitride or silicon dioxide. The bit line 21 is also formed in the same manner as in the related art.
In step S200, please continue to refer to fig. 2, a layer of isolation material 22 is formed on the substrate 20 and the bit lines 21, wherein the layer of isolation material 22 covers the top and sidewalls of the bit lines 21.
Specifically, an isolation material layer 22 is formed on the substrate 20 and the upper surface of the bit line 21 by using an atomic layer deposition technique, and the isolation material layer 22 covers the exposed surface of the bit line 21, that is, the isolation material layer 22 covers the top and the sidewall of the bit line 21, and meanwhile, the isolation material layer 22 also covers the upper surface of the substrate 20 that is not covered by the bit line 21. I.e., the layer of isolation material 22 includes a first site 22a on the bit line 21, a second site 22b on the substrate 20, and a third site (not shown) on the sidewalls of the bit line 21.
The isolation material layer 22 includes, but is not limited to, silicon nitride (SiN) or silicon oxynitride (SiON) or silicon dioxide (SiO2), and the isolation material layer 22 must have an isolation effect on the gas generated by the decomposition of the subsequent high molecular polymer material layer to prevent the gas from affecting the bit line 21 and the substrate 20.
Fig. 3 and 4 are cross-sectional views illustrating the process of performing step S300 according to an embodiment of the present invention. In step S300, please refer to fig. 3 and 4, a polymer material layer 23 is formed on the isolation material layer 22, and the polymer material layer 23 covers a portion of the isolation material layer 22 corresponding to the sidewall of the bit line 21, so that the polymer material layer 23 covers the sidewall of the bit line 21 with the isolation material layer 22 therebetween.
First, referring to fig. 3, a polymer material layer 23 is formed on the isolation material layer 22, and the polymer material layer 23 covers the isolation material layer 22. The material of the polymer material layer 23 includes, but is not limited to, polystyrene or polymethyl methacrylate, and may be deposited on the surface of the isolation material layer 22 by a selective coating method or the like. The layer 23 of high molecular polymer material is capable of decomposing at high temperature into a gas, including but not limited to CO2、H2O、NH3The isolation material layer 22 is required to isolate the gas, so as to prevent the gas from affecting the bit line 21 and the substrate 20.
Then, referring to fig. 4, the polymer material layer 23 is etched, only the portion of the polymer material layer 23 on the sidewall of the bit line 21 is remained, and the first portion 22a of the isolation material layer 22 on the bit line 21 and the second portion 22b on the substrate 20 are exposed; when the porous insulating material layer is formed, the porous insulating material layer is attached to the first portion 22a and the second portion 22b of the separator material layer 22 so as to cover the high molecular polymer material layer 23.
In this embodiment, a plasma etching technique may be adopted to remove the redundant polymer material layer 23, and only the polymer material layer 23 on the sidewall of the bit line 21 is remained.
Fig. 5 is a cross-sectional view illustrating the process of performing step S400 according to an embodiment of the present invention. In step S400, please refer to fig. 5, a porous insulating material layer 24 is formed on the isolation material layer 22 and the polymer material layer 24, and the porous insulating material layer 24 covers the polymer material layer 23 and the isolation material layer 22. The porous insulating material layer 24 is attached to the first portion 22a and the second portion 22b of the insulating material layer 22 to cover the high molecular polymer material layer 23.
The plurality of pores in the porous insulating material layer 24 allow the gas generated by the decomposition of the high molecular polymer material layer 23 to pass through, i.e., the gas can pass through the plurality of pores in the porous insulating material layer 24, so as to escape from the semiconductor device, and the gas cannot pass through the isolation material layer 22, so that the bit line 21 and the substrate 20 are not damaged.
The porous insulating material layer 24 may be formed by using a chemical vapor deposition, an atomic layer deposition, or the like, and the porous insulating material layer 24 covers the high molecular polymer material layer 23 and the exposed isolating material layer 22. The material of the porous insulating material layer 24 includes, but is not limited to, mesoporous silica, and the porous characteristic of the porous insulating material layer allows the gas decomposed by the high molecular polymer material layer 23 to pass through.
Fig. 6 is a cross-sectional view illustrating the process of performing step S500 according to an embodiment of the present invention. In step S500, a high temperature annealing process is performed to decompose the polymer material layer 23 into a gas, and the isolation material layer 22 isolates the gas and allows the gas to escape from the porous insulating material layer 24 to define air gaps 23 'on portions of the isolation material layer 22 corresponding to sidewalls of the bit line 21, the air gaps 23' being located on both sides of the bit line 21 and between the isolation material layer 22 and the porous insulating material layer 24.
In this embodiment, preferably, the temperature of the high temperature annealing process is greater than 350 ℃, and oxygen is introduced during the high temperature annealing process, so that the polymer material layer 23 is decomposed when subjected to the high temperature annealing process and is completely converted into CO2、H2O、NH3The gas is blocked by the isolation material layer 22 and does not damage the bit line 21 and the substrate 20, the gas can pass through the pores in the porous insulation material layer 24, and the gas escapes from the pores in the porous insulation material layer 24, so that an air gap 23 'is formed at the part of the isolation material layer 22 corresponding to the side wall of the bit line 21 (where the high molecular polymer material layer 23 is located after etching), and the air gap 23' is located between the isolation material layer 22 and the porous insulation material layer 24.
The magnitude of the parasitic capacitance is proportional to the magnitude of the dielectric constant of the isolation material, and in order to reduce the parasitic capacitance between the bit lines 21, a material having a small dielectric constant needs to be selected as the isolation material between the bit lines, and the dielectric constant of air is 1, which is an excellent choice for reducing the parasitic capacitance. The air gaps 23 'are located on the portions of the isolation material layer 22 corresponding to the sidewalls of the bit lines 21, that is, two air gaps 23' are provided between adjacent bit lines 21, so that the parasitic capacitance between the bit lines 21 can be reduced, and the improvement of the device performance can be facilitated.
FIG. 7 is a cross-sectional view illustrating the formation of a bit line insulating layer according to an embodiment of the present invention. Referring to fig. 7, after forming the air gap 23', the method further includes: a bit line isolation layer 25 is formed on the porous insulating material layer 24, and the bit line isolation layer 25 covers the porous insulating material layer 24 and fills a gap between adjacent bit lines 21. The bit line isolation layer 25 is made of a material including, but not limited to, silicon dioxide to isolate the bit line 21 from a subsequently formed device structure.
In the method for manufacturing a bit line structure provided by the present invention, a plurality of bit lines 21 arranged at intervals are formed on a substrate 20, a spacer material layer 22 is formed on the top and the sidewall of the bit line 21, a polymer material layer 23 is formed on the spacer material layer 22, then a porous insulating material layer 24 is formed on the polymer material layer 23 and the spacer material layer 22, finally a high temperature annealing process is performed to decompose the polymer material layer 23 into a gas, the spacer material layer 22 separates the gas to protect the bit line 21 and the substrate 20, and the gas escapes through a plurality of pores in the porous insulating material layer 24, so that air gaps 23 'are formed on the portions of the spacer material layer 22 corresponding to the sidewall of the bit line 21, the air gaps 23' are located on both sides of the bit line 21 and between the spacer material layer 22 and the porous insulating material layer 24, the air gaps 23' can reduce the parasitic capacitance between the bit lines 21 and improve the performance of the device.
Accordingly, the present invention further provides a bit line structure manufactured by the method for forming a bit line structure as described above, with reference to fig. 7, the bit line structure includes: a substrate 10, a plurality of bitlines 21 located on the substrate 10, a layer of spacer material 22, a layer of porous insulating material 24, and air gaps 23'.
Specifically, the bit lines 21 are disposed on the substrate, and a plurality of the bit lines 21 are arranged at intervals. The layer of spacer material 22 covers the top and sidewalls of the bit line 21, the layer of porous insulating material 24 covers the layer of spacer material 22, and the layer of porous insulating material 24 has a plurality of pores therein, the air gaps 23 'are located on both sides of the bit line 21 between the layer of spacer material 22 and the layer of porous insulating material 24, and the air gaps 23' are in communication with the plurality of pores in the layer of porous insulating material 24.
Preferably, the memory further comprises a bit line isolation layer 25, wherein the bit line isolation layer 25 covers the porous insulating material layer 24 and fills gaps between adjacent bit lines 21. The material of the isolation material layer 22 includes, but is not limited to, silicon nitride or silicon oxynitride or silicon dioxide, the material of the porous insulating material layer 24 includes, but is not limited to, mesoporous silicon dioxide, and the material of the bit line isolation layer 25 includes, but is not limited to, silicon dioxide.
The bit line 21 includes a first conductive material layer 211, a second conductive material layer 212 and a protection material layer 213 sequentially disposed on the substrate 20, wherein the first conductive material layer 211 includes but is not limited to doped polysilicon, the second conductive material layer 212 includes but is not limited to titanium or titanium nitride or tungsten, and the protection material layer 213 includes but is not limited to silicon nitride or silicon oxynitride or silicon dioxide.
The layer of spacer material 22 has a first portion 22a on the bit line 21 and a second portion 22b on the substrate 20, and the layer of porous insulating material 24 is attached to the first portion 22a and the second portion 22b of the layer of spacer material 22 to encapsulate the air gaps 23'.
The air gap 23' is located on the portion, corresponding to the side wall of the bit line 21, of the isolation material layer 22, the dielectric constant of air is 1, parasitic capacitance between the bit lines 21 can be well reduced, and performance of the device is improved.
Correspondingly, the invention also provides a memory, comprising: the device comprises a substrate, a plurality of bit lines, an isolation material layer, a porous insulation material layer and air gaps, wherein the bit lines, the isolation material layer, the porous insulation material layer and the air gaps are located on the substrate.
Specifically, the bit lines are disposed on the substrate, and the plurality of bit lines are arranged at intervals. The layer of spacer material covers the top and sidewalls of the bit line, the layer of porous insulating material covers the layer of spacer material, and the layer of porous insulating material 24 has a plurality of pores therein, and the air gaps 23' are located on either side of the bit line 21 between the layer of spacer material 22 and the layer of porous insulating material 24, the air gaps being in communication with the plurality of pores in the layer of porous insulating material.
Active regions, isolation structures, word lines, bit line contacts and other parts are further formed in the substrate, and the bit lines are electrically connected with the bit line contacts.
In summary, in the bit line structure, the method for manufacturing the bit line structure, and the memory provided by the present invention, a plurality of bit lines arranged at intervals are formed on a substrate, isolation material layers are formed on the top and the sidewalls of the bit lines, a high molecular polymer material layer is formed on the isolation material layer corresponding to the sidewalls of the bit lines, then a porous insulating material layer is formed on the high molecular polymer material layer and the isolation material layer, and finally a high temperature annealing process is performed to decompose the high molecular polymer material layer into a gas, the isolation material layer isolates the gas to protect the bit lines and the substrate, and the gas is allowed to escape through a plurality of pores in the porous insulating material layer, so that air gaps are formed on the isolation material layer corresponding to the sidewalls of the bit lines, the air gaps are located at two sides of the bit lines and between the isolation material layer and the porous, the air gap can reduce the parasitic capacitance between the bit lines and improve the performance of the device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (15)
1. A method for fabricating a bitline structure, comprising:
providing a substrate, wherein a plurality of bit lines are formed on the substrate and are arranged at intervals;
forming a layer of isolation material on the substrate and the bit lines, the layer of isolation material covering the tops and sidewalls of the bit lines;
forming a high molecular polymer material layer on the isolation material layer, wherein the high molecular polymer material layer covers the part, corresponding to the side wall of the bit line, of the isolation material layer, so that the high molecular polymer material layer covers the side wall of the bit line at intervals of the isolation material layer;
forming a porous insulating material layer on the isolation material layer and the high molecular polymer material layer, wherein the porous insulating material layer covers the high molecular polymer material layer and the isolation material layer;
and performing a high-temperature annealing process to decompose the high-molecular polymer material layer into gas, wherein the isolating material layer isolates the gas and allows the gas to escape from the porous insulating material layer so as to define air gaps on the parts, corresponding to the side walls of the bit line, of the isolating material layer, wherein the air gaps are positioned on two sides of the bit line and between the isolating material layer and the porous insulating material layer.
2. The method of claim 1, wherein the polymer material layer comprises polystyrene or polymethyl methacrylate, and the gas generated by decomposition of the polymer material layer comprises CO2、H2O、NH3。
3. The method of claim 1, wherein the spacer material layer comprises silicon nitride, silicon oxynitride, or silicon dioxide, and the porous insulating material layer comprises mesoporous silicon dioxide.
4. The method of fabricating a bitline structure of claim 1, wherein the method of forming the spacer material layer comprises an atomic layer deposition method; the method of forming the porous insulating material layer includes a chemical vapor deposition method or an atomic layer deposition method.
5. The method of claim 1, wherein the step of forming the polymer material layer comprises:
forming a high molecular polymer material layer on the isolation material layer, wherein the high molecular polymer material layer covers the isolation material layer;
etching the high molecular polymer material layer, only reserving a part of the high molecular polymer material layer on the side wall of the bit line, and exposing a first part of the isolation material layer on the bit line and a second part on the substrate; when the porous insulating material layer is formed, the porous insulating material layer covers the first portion and the second portion of the spacer material layer, and the portion of the high molecular polymer material layer remaining on the bit line sidewall.
6. The method of claim 5, wherein the forming the polymer material layer comprises spin coating; the method for etching the high polymer material layer comprises plasma etching.
7. The method of claim 1, wherein the temperature of the high temperature annealing process is greater than 350 ℃, and oxygen is introduced during the high temperature annealing process.
8. The method of fabricating a bitline structure of claim 1, further comprising, after forming the air gap: and forming a bit line isolation layer on the porous insulating material layer, wherein the bit line isolation layer covers the porous insulating material layer and fills gaps between adjacent bit lines, and the bit line isolation layer is made of silicon dioxide.
9. The method of claim 1, wherein the bit line comprises a first conductive material layer, a second conductive material layer and a protective material layer sequentially formed on the substrate, the first conductive material layer comprises doped polysilicon, the second conductive material layer comprises titanium or titanium nitride or tungsten, and the protective material layer comprises silicon nitride or silicon oxynitride or silicon dioxide.
10. A bit line structure, comprising:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals;
the isolation material layer is positioned on the substrate and the bit line, and covers the top and the side wall of the bit line;
a layer of porous insulating material on the layer of separator material, the layer of porous insulating material covering the layer of separator material and having a plurality of pores therein;
air gaps on both sides of the bit lines between the layer of spacer material and the layer of porous insulating material, the air gaps in communication with the plurality of pores in the layer of porous insulating material.
11. The bit line structure of claim 10, further comprising a bit line isolation layer covering the layer of porous insulating material and filling gaps between adjacent bit lines.
12. The bit line structure of claim 11, wherein the material of the isolation material layer comprises silicon nitride, silicon oxynitride, or silicon dioxide, the material of the porous insulating material layer comprises mesoporous silicon dioxide, and the material of the bit line isolation layer comprises silicon dioxide.
13. The bit line structure of claim 10, wherein the bit line comprises a first conductive material layer, a second conductive material layer and a protective material layer sequentially disposed on the substrate, the first conductive material layer comprises doped polysilicon, the second conductive material layer comprises titanium or titanium nitride or tungsten, and the protective material layer comprises silicon nitride or silicon oxynitride or silicon dioxide.
14. The bitline structure of claim 10, wherein the layer of spacer material has a first location on the bitline and a second location on the substrate, the layer of porous insulating material covering the first and second locations of the layer of spacer material and encapsulating the air gaps.
15. A memory, comprising:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals;
the isolation material layer is positioned on the substrate and the bit line, and covers the top and the side wall of the bit line;
a layer of porous insulating material on the layer of separator material, the layer of porous insulating material covering the layer of separator material and having a plurality of pores therein;
air gaps on both sides of the bit lines between the layer of spacer material and the layer of porous insulating material, the air gaps in communication with the plurality of pores in the layer of porous insulating material.
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