CN108074866A - The preparation method and structure of a kind of semiconductor transistor - Google Patents
The preparation method and structure of a kind of semiconductor transistor Download PDFInfo
- Publication number
- CN108074866A CN108074866A CN201711226548.8A CN201711226548A CN108074866A CN 108074866 A CN108074866 A CN 108074866A CN 201711226548 A CN201711226548 A CN 201711226548A CN 108074866 A CN108074866 A CN 108074866A
- Authority
- CN
- China
- Prior art keywords
- bolt
- insulation
- side wall
- layer
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 238000009413 insulation Methods 0.000 claims abstract description 170
- 238000007789 sealing Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000012212 insulator Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 52
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 238000010276 construction Methods 0.000 claims description 41
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 239000010703 silicon Substances 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- 238000000231 atomic layer deposition Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 19
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000011049 filling Methods 0.000 claims description 16
- 229910021529 ammonia Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910000077 silane Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- WGYKZJWCGVVSQN-UHFFFAOYSA-N propylamine Chemical compound CCCN WGYKZJWCGVVSQN-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 238000007664 blowing Methods 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 5
- 238000004062 sedimentation Methods 0.000 claims description 5
- 241000278713 Theora Species 0.000 claims description 3
- 235000008429 bread Nutrition 0.000 claims description 3
- 230000001351 cycling effect Effects 0.000 claims description 3
- RFBSXFWTSAJAEJ-UHFFFAOYSA-N silane dihydrochloride Chemical compound [SiH4].Cl.Cl RFBSXFWTSAJAEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 238000010926 purge Methods 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 19
- 238000010586 diagram Methods 0.000 description 30
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 230000001934 delay Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 239000012774 insulation material Substances 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- DUFGEJIQSSMEIU-UHFFFAOYSA-N [N].[Si]=O Chemical compound [N].[Si]=O DUFGEJIQSSMEIU-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
Abstract
The preparation method and structure of a kind of semiconductor transistor of teachings of this disclosure, including Semiconductor substrate；Gate structure, positioned at the upper surface of Semiconductor substrate, the gate insulator including grid conducting layer and on grid conducting layer；Gate insulation side wall, positioned at the side wall of gate structure；Positioned at the both sides of gate structure, electric isolation is carried out between each bolt conductive structure by air insulation structure or insulating layer for bolt conductive structure；Airside wall, between bolt conductive layer and the gate insulation side wall, airside wall includes the air gap and insulation sealing layer, and the air gap is sealed by the insulation sealing layer.Compared with prior art, the introducing of the air gap and airspace room not only reduces the parasitic capacitance between grid and bolt conductive structure, and reduce the parasitic capacitance between bolt conductive structure and bolt conductive structure, the stability and reliability of transistor are improved, a kind of effective approach is provided for further reducing for transistor size.
Description
Technical field
The present invention relates to a kind of manufacturing process of semiconductor devices, more particularly to a kind of preparation side of semiconductor transistor
Method and structure.
Background technology
Metal-oxide semiconductor fieldeffect transistor (MOSFET, Metal-Oxide-Semiconductor
Field-Effect Transistor) it is that most common unit is used in integrated circuit.Since MOSFET is in normal operating conditions
Under, grid, source electrode and the voltage of drain electrode is all unequal so electric field between them is there is a coupling, this coupling is made
With the presence that will appear as having capacitance between them.With the development of integrated circuit, device miniaturization is inevitable trend, but work
Parasitic capacitance is not proportionally reduced with the reduction of device size in skill, and assertive evidence capacitance reducing with device size
The reduction of ratio, the ratio that accounts for of such parasitic capacitance in total capacitance just considerably increase, and have seriously affected the stabilization of device
Property and reliability, therefore to the research of small size device parasitic capacitance with regard to more meaningful.
As the process shrink of dynamic RAM (DRAM, Dynamic Random Access Memory) is to nanometer
Scale, under conditions of element significantly reduces, it is a major challenge to improve grid and the interelectrode parasitic capacitance of source-drain electrode, grid and
Source-drain electrode is equivalent to two pole plates of a plane-parallel capacitor, in plane-parallel capacitor, capacitance C, plane-parallel capacitor
The dielectric coefficient k of dielectric layer, polar plate area A, pole plate spacing d, plate charge amount Q, charging and discharging currents I, charge-discharge electric power P fill
Discharge energy W, charge and discharge time t, there are following relations between voltage V between pole plate：C=kA/d, Q=It, C=Q/V, P=W/t
=IV, for a specific device, it will be assumed that polar plate voltage, charging and discharging currents, polar plate area and distance between polar plate are constant
In the case of, it is possible thereby to derive RC delays t ∝ C ∝ k, switch energy W ∝ C ∝ k, it can be seen that selecting one
The low wall of kind dielectric coefficient can effectively reduce the parasitic capacitance between grid and hourglass source electrode, and then reduce capacitance resistance
Delay and reduction switch energy consumption.Fig. 1 is the structure diagram of the MOSFET of a prior art, including Semiconductor substrate 11 ', grid
Conductive layer 121 ', gate insulator 122 ', gate insulation side wall 13 ', stud structure, the gate insulation side wall 13 ' is successively by silicon nitride
Layer 131 ', silicon oxide layer 132 ' and silicon nitride layer 131 ' form, and the stud structure is by bolt conductive structure 15 ' and bolt insulation system
16 ' along the gate insulation side wall 13 ' length direction repeated arrangement form, the bolt insulation system 16 ' be insulating layer 162 ', institute
State 131 ' dielectric constant (k of silicon nitride layer:And 132 ' dielectric constant (the k of silicon oxide layer 7.8):3.9) higher, this will be unfavorable for
The parasitic capacitance in semiconductor transistor is dropped, influences the reliability and stability of device.
Therefore, the parasitic capacitance between grid and bolt conductive structure and bolt conductive structure how to be reduced and bolt conduction is tied
Parasitic capacitance between structure improves the reliability of semiconductor devices, it has also become those skilled in the art's weight urgently to be resolved hurrily
Want problem.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of preparations of semiconductor transistor
Method and structure, for solving in the prior art between grid and bolt conductive structure and bolt conductive structure and bolt conductive structure
Between parasitic capacitance it is big the problem of, improve device stability and reliability.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation side of semiconductor transistor construction
Method, which is characterized in that the preparation method of the semiconductor transistor construction includes at least following steps：
Step S1, semi-conductive substrate is provided, sequentially form grid conducting layer on the semiconductor substrate and grid is exhausted
Edge layer forms gate structure by etching；
Step S2, the side wall in the gate structure sequentially forms gate insulation side wall and sacrifices side wall, described in adjacent two
It sacrifices side wall and surrounds the first groove；
Step S3, form bolt conductive layer in first groove that surrounds of sacrifice side wall, by etch formed by
Several bolt conductive structures of several second groove isolation；
Step S4, bolt insulation system is formed in second groove between the bolt conductive structure；
Step S5, the sacrifice side wall is removed, it is empty to be formed between the gate insulation side wall and the bolt conductive structure
Gas gap；
Step S6, in forming insulation sealing layer in the air gap, the air gap is closed into airside wall.
Preferably, the method for the bolt insulation system is formed between the bolt conductive structure to be included：
In step s 4, in the sacrifice side wall, the side wall of the bolt conductive structure and the upper table of the Semiconductor substrate
Face forms bolt insulative sidewall, and the bolt insulative sidewall surrounds to form airspace room；And form the insulation sealing in step S6
While layer, the airspace room is closed into air insulation structure.
Preferably, the method for the bolt insulation system is formed between each bolt conductive structure to be included：
In step s 4, in the sacrifice side wall, the side wall of the bolt conductive structure and the upper table of the Semiconductor substrate
Filling forms insulating layer in second groove that bread encloses.
Preferably, forming the method for the insulation sealing layer includes atomic layer deposition, passes through the cycling of multiple deposition process
Realize atomic layer deposition, the wherein deposition process of single loop includes sidewall surfaces of first presoma in the air gap
Learn absorption and form monoatomic layer, washed away by inert blowing gas except extra first presoma, the second presoma with it is described
Monoatomic layer reacts to form insulation sealed membrane layer, is washed away by inert blowing gas except extra second presoma and pair
Product.
Preferably, first presoma is in a pulsed fashion into reaction chamber, and be chemisorbed on the air gap
Sidewall surfaces, board rear end main valve open ratio is between 60% to 100% at this time.
Preferably, first presoma is in a pulsed fashion into reaction chamber, the sidewall surfaces in the air gap
The time of Chemisorption is between 1 second to 3 seconds.
Preferably, the insulation sealing layer is formed using atomic layer deposition method deposited silicon nitride, the first presoma includes two
Chlorinated silane, the second presoma include ammonia, the sedimentation time of single loop between 20 seconds to 60 seconds, process temperature between
Between 400 degree to 700 degree.Preferably, the insulation sealing layer is formed using atomic layer deposition method deposition silica, before first
Driving body includes single propyl amine silicon, and the second presoma includes oxygen, and the sedimentation time of single loop is between 20 seconds to 60 seconds, mistake
Cheng Wendu is room temperature.
The present invention also provides a kind of semiconductor transistor construction, the semiconductor transistor construction includes at least：
Semiconductor substrate；
Gate structure, positioned at the upper surface of the Semiconductor substrate, including grid conducting layer and positioned at the Gate Electrode Conductive
Gate insulator on layer；
Gate insulation side wall, positioned at the side wall of the gate structure；
Bolt conductive structure positioned at the both sides of the gate structure, is insulated between the adjacent bolt conductive structure by bolt
Structure carries out electric isolation；Wherein, the gap between the bolt conductive structure and the gate structure is more than the gate insulation side
The deposition thickness of wall, to form the air gap between the gate insulation side wall and the bolt conductive structure；And
First insulation sealing layer, is formed on the air gap, and the air gap is closed into airside wall, by
Small in dielectric constant of air, the airside wall can effectively reduce the parasitic capacitance between grid and bolt conductive structure, reduce electricity
Capacitance delays are hindered, and then increase switching speed, reduce switch energy.
Preferably, the first insulation sealing layer is locally filled between the gate insulation side wall and the bolt conductive structure
The air gap opening, it is described first insulation sealing layer insert inside depth be no more than level in the grid conducting layer top surface
Level.
Preferably, the first insulation first top surface of sealing layer, the second top surface of the gate insulation side wall, the bolt are led
4th top surface of the 3rd top surface of electric structure and the gate insulator of the gate structure is formed at same ground flat, uses
To ensure that the semiconductor transistor construction also keeps the airside wall to be still hermetically closed under an opposite low clearance.
Preferably, the bolt insulation system has the 5th top surface, is also formed in same ground flat.
Preferably, the 5th top surface of the bolt insulation system includes the solid object surface of insulating layer, and the insulating layer fills shape
Cheng Yu is by the adjacent bolt conductive structure and the second groove of the adjacent airside wall encirclement.
Preferably, the 5th top surface of the bolt insulation system includes the annular surface of bolt insulative sidewall and in the annular table
Bread encloses the surface of the second interior insulation sealing layer, and the bolt insulative sidewall connects the ora terminalis and shape of the adjacent bolt conductive structure
The upper surface of the side wall of bolt conductive structure and the Semiconductor substrate described in Cheng Yu forms airspace room to surround；Described
Two insulation sealing layers close the airspace room into air insulation structure, and since dielectric constant of air is small, the air is exhausted
Edge structure can effectively reduce the parasitic capacitance between grid and bolt conductive structure, reduce RC delays, and then increase switch
Speed reduces switch energy.
Preferably, the second insulation sealing layer, which locally inserts the bolt insulative sidewall and surrounds the airspace room to be formed, opens
Mouthful, the second insulation sealing layer insert inside depth be no more than it is horizontal in the level of the grid conducting layer top surface,
The material of the second insulation sealing layer is selected from forms one of group by silicon nitride, silica and silicon oxynitride.
Preferably, the material of the gate insulation side wall is selected from forms group by silicon nitride, silica and silicon oxynitride
One of, the thickness of the gate insulation side wall is between 2 nanometers to 15 nanometers；The material of the bolt conductive structure includes
Polysilicon；It is described first insulation sealing layer material be selected from by silicon nitride, silica and silicon oxynitride form group its
One of.
Preferably, the height of the air gap is more than the height of the grid conducting layer, and less than the gate structure
Height；The width of the air gap is between 2 nanometers to 20 nanometers；Dichlorosilane, ammonia are included in the air gap
One or several kinds in gas, silane, tetrachloro silicane and nitrogen；Gas pressure in the air gap between 200 millitorrs extremely
Between one standard atmospheric pressure.
Preferably, the material of the insulating layer is selected from forms group by silicon nitride, silica and silicon oxynitride
One of them.
Preferably, the material of the bolt insulative sidewall is selected from and is made of silicon nitride, silica and silicon oxynitride
One of group, the thickness of the bolt insulative sidewall is between 2 nanometers to 15 nanometers.
Preferably, the height of the airspace room is more than the height of the grid conducting layer, and less than the grid knot
The height of structure；The width of the airspace room is between 2 nanometers to 20 nanometers；Dichloro silicon is included in the airspace room
One or several kinds in alkane, ammonia, silane, tetrachloro silicane and nitrogen；The indoor gas pressure in airspace is between 200
Millitorr is between a standard atmospheric pressure.
Preferably, there is the occluded air compartment of a pointed structures in the air insulation structure.
Preferably, there is the occluded air gap of a pointed structures in the airside wall.
As described above, the preparation method and structure of a kind of semiconductor transistor of the present invention, have the advantages that：
1. the present invention uses the dissymmetrical structure of silicon nitride-airside wall, with silicon-nitride and silicon oxide-nitrogen in the prior art
The symmetrical gate insulation side wall construction of SiClx is compared, and since dielectric constant of air is small, can effectively be reduced between grid and bolt conductive structure
Parasitic capacitance, reduce RC delays, and then increase switching speed, reduce switch energy；And reduce one layer of nitridation
Silicon layer, can increase Semiconductor substrate efficiently uses area.
2. the present invention uses the air insulation structure containing airspace room, compared with insulating layer in the prior art, due to
Dielectric constant of air is small, can effectively reduce between grid and bolt conductive structure and between bolt conductive structure and bolt conductive structure
Parasitic capacitance, reduce RC delays, and then increase switching speed, reduce switch energy.
3. the present invention is during bolt conductive structure is prepared, first deposit polycrystalline silicon simultaneously forms bolt conductive structure, after each bolt
Bolt insulation system is formed between conductive structure, when can be to avoid due to being initially formed deposit polycrystalline silicon after bolt insulation system, polysilicon
Cause in the defects of depositing to bolt insulation system and turn between bolt conductive structure, improve the stability and reliability of device.
4. the present invention uses airside wall and air insulation structure can effectively reduce between grid and bolt conductive structure with
And the parasitic capacitance between each bolt conductive structure, in the case where ensureing semiconductor transistor normal work, provide it is a kind of into
One step reduces semiconductor crystal pipe size, improves the effective way of integrated circuit integrated level.
Description of the drawings
Fig. 1 is shown as the schematic diagram of semiconductor transistor construction of the prior art.
Fig. 2 is shown as the flow diagram of the preparation method of semiconductor transistor of the present invention.
Fig. 3 is shown as the present invention in formation grid conducting material layer, gate insulating material layer and grid in Semiconductor substrate
The structure diagram of pattern layer.
Fig. 4 is shown as the present invention in the structure diagram that grid conducting layer, gate insulator are formed in Semiconductor substrate.
Fig. 5 is shown as the present invention in the structure diagram that gate insulation side-wall material layer is formed on gate structure sidewall.
Fig. 6 is shown as the present invention in the structure diagram that gate insulation side wall is formed on gate structure sidewall.
Fig. 7 is shown as the present invention in the structure diagram that sacrifice side-wall material layer is formed on gate insulation side wall.
Fig. 8 is shown as the present invention in the structure diagram that sacrifice side wall is formed on gate insulation side wall.
Fig. 9 is shown as the structure diagram that the present invention forms bolt conductive material layer in Semiconductor substrate exposed locations.
Figure 10 is shown as the structure diagram that the present invention forms bolt conductive layer in Semiconductor substrate exposed locations.
Figure 11 is shown as the present invention in the structure diagram that bolt pattern layer is formed on bolt conductive layer.
Figure 12 is shown as the present invention in the structure diagram that bolt conductive structure is formed on bolt conductive layer.
Figure 13 is shown as being formed in the side wall of bolt conductive structure and the upper surface of Semiconductor substrate in the embodiment of the present invention one
The structure diagram of bolt insulative sidewall material layer.
Figure 14 is shown as being formed in the side wall of bolt conductive structure and the upper surface of Semiconductor substrate in the embodiment of the present invention one
The structure diagram of bolt insulative sidewall.
Figure 15 is shown as in the embodiment of the present invention one in the structure diagram for sacrificing sidewall locations formation the air gap.
Figure 16 is shown as in the embodiment of the present invention one in formation insulation joint filling material floor in the air gap and airspace room
Structure diagram.
Figure 17 is shown as the structure diagram of the semiconductor transistor in the embodiment of the present invention one.
Figure 18 is shown as being formed the structure diagram of insulation material layer between bolt conductive structure in the embodiment of the present invention two.
Figure 19 is shown as being formed the structure diagram of insulating layer between bolt conductive structure in the embodiment of the present invention two.
Figure 20 is shown as in the embodiment of the present invention two in the structure diagram for sacrificing sidewall locations formation the air gap.
Figure 21 is shown as in the embodiment of the present invention two in the structure diagram that insulation joint filling material layer is formed in the air gap.
Figure 22 is shown as the schematic diagram of the structure of the semiconductor transistor in the embodiment of the present invention two
Figure 23 is shown as in Fig. 3 and Figure 18 of the present invention along the structure diagram in dotted line X sections.
Figure 24 is shown as in Fig. 3 of the present invention along the structure diagram in dotted line Y sections.
Figure 25 is shown as the structure diagram that the present invention prepares the atomic deposition device of insulation sealing.
Figure 26 is shown as the schematic diagram that atomic layer deposition method of the present invention prepares insulation sealing response procedures.
Figure 27 is shown as the schematic diagram that atomic layer deposition method of the present invention prepares insulation sealing coverage rate.
Figure 28 is shown as the structure diagram that atomic layer deposition method of the present invention prepares insulation sealing.
Component label instructions
11,11 ' Semiconductor substrates
121,121 ' grid conducting layers
1210 grid conducting material layers
122,122 ' gate insulators
1220 gate insulating material layers
13,13 ' gate insulation side walls
130 gate insulation side-wall material layers
131 ' silicon nitride layers
132 ' silicon dioxide layers
14 airside walls
140 sacrifice side wall
1400 sacrifice side-wall material layer
141 the air gaps
15,15 ' bolt conductive structures
150 bolt conductive layers
1500 bolt conductive material layers
151 first grooves
16,16 ' bolt insulation systems
161 second grooves
162,162 ' insulating layers
1620 insulation material layers
17 air insulation structures
171 airspaces room
172 bolt insulative sidewalls
1720 bolt insulative sidewall material layers
18 insulation sealing layers
180 insulation joint filling material layers
181 first insulation sealing layers
182 second insulation sealing layers
191 gate pattern layers
192 bolt pattern layers
21 substrates
22 storage boxes
23 first presomas
24 reaction chambers
25 nozzles
S1~S6 steps
A~d steps
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 2 is referred to Figure 28.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then only the display component related with the present invention rather than package count during according to actual implementation in schema
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in Fig. 2~Figure 17, in order to effectively reduce the parasitic capacitance between grid and bolt conductive structure, resistance electricity is reduced
Hold delay, and then increase switching speed, reduce switch energy, the present embodiment provides a kind of preparation sides of semiconductor transistor construction
Method, the preparation method of the semiconductor transistor construction include at least following steps：
Step S1 is performed, semi-conductive substrate 11 is provided, grid conducting layer is sequentially formed in the Semiconductor substrate 11
121 and gate insulator 122, gate structure is formed by etching.
Specifically, as shown in figure 3, in the present embodiment, the Semiconductor substrate 11 uses silicon substrate；In the silicon substrate
Upper oxidation layer of oxide layer (not shown), as the dielectric layer of gate structure, thickness is between 1 nanometer to 10 nanometers；
Using physical vaporous deposition or chemical vapour deposition technique one layer of Gate Electrode Conductive material is formed in the surface of the Semiconductor substrate 11
Tungsten can be used in the bed of material 1210 and one layer of gate insulating material layer 1220, the material of the grid conducting material layer 1210, thick
Degree is between 15 nanometers to 90 nanometers, and silicon nitride can be used in the material of the gate insulating material layer 1220, and thickness is between 50
Nanometer is to 300 nanometers；Using exposure imaging technology, in formation gate pattern layer 191 on the gate insulating material layer 1220.
Specifically, as described in Figure 4, in the present embodiment, using etch process in the upper surface of the Semiconductor substrate 11
Gate structure is formed, grid of the gate structure including grid conducting layer 121 and on the grid conducting layer 121 is exhausted
Edge layer 122, the etch process include but not limited to dry etching or wet etching, can be selected according to actual demand and experiment condition
With specific etching technics, it is not limited to this embodiment.
Step S2 is performed, gate insulation side wall 13 is sequentially formed in the side wall of the gate structure and sacrifices side wall 140, it is adjacent
Two it is described sacrifice side walls 140 surround the first groove 151.
Specifically, in the present embodiment, first, as shown in figure 5, in the upper surface of step S1 resulting structures using chemical gas
Mutually the method for deposition forms one layer of gate insulation side-wall material layer 130, then, as shown in fig. 6, it is preferred that will using dry etching
The gate insulation side-wall material layer 130 in the Semiconductor substrate 11 and the gate insulator 122 removes, and forms the grid
Silicon nitride can be used in insulative sidewall 13, the material of the gate insulation side wall 13, and thickness is between 2 nanometers to 15 nanometers；
It should be noted that the process gas that chemical vapour deposition technique forms the nitride gate insulative sidewall 13 include but
It is not limited to the mixed gas of monosilane and ammonia, the mixed gas or tetrachloro silicane of dichlorosilane and ammonia and the gaseous mixture of ammonia
Body can select specific mixed gas according to experiment condition, be not limited to this embodiment, and process pressure includes 0.25 support to 500
Support, process temperatures are between 600 degree to 800 degree；Wherein, in mixed gas monosilane, dichlorosilane or tetrachloro silicane body
Product and the volume ratio of ammonia are between 1:3 to 1:Between 10.
Specifically, in the present embodiment, first, as shown in fig. 7, on the gate insulation side wall 13 use chemical vapor deposition
Long-pending method forms one layer and sacrifices side-wall material layer 1400, then, as shown in figure 8, being served as a contrast the semiconductor using dry etching
The sacrifice side-wall material layer 1400 on bottom 11 and the gate insulator 122 removes, and forms the sacrifice side wall 140, institute
Silica can be used in the material for stating sacrifice side wall 140, and thickness is between 2 nanometers to 15 nanometers.
It sacrifices the process gas of side wall 140 it should be noted that vapour deposition process forms the silica and includes but not
It is limited to the mixed gas of the mixed gas of ethyl orthosilicate and nitrous oxide, monosilane and nitrous oxide, ethyl orthosilicate
With the mixed gas of oxygen, the mixed gas of monosilane and oxygen can select specific mixed gas according to experiment condition, not with
The present embodiment is limited, and process pressure includes 400 millitorrs to 1 standard atmospheric pressure, and process temperatures are between 200 degree to 800 degree.
Step S3 is performed, is formed in first groove 151 surrounded in the sacrifice side wall 140 and Semiconductor substrate 11
Several bolt conductive structures 15 that etching technics formation is isolated by several second grooves 161 can be used in bolt conductive layer 150.
Specifically, in the present embodiment, as shown in figure 9, first, in the present embodiment, using chemical vapour deposition technique in
The upper surface of step S2 resulting structures deposits one layer of bolt conductive material layer 1500, and the material of the bolt conductive material layer 1500 can be adopted
With polysilicon, thickness is between 100 nanometers to 500 nanometers；Secondly, as shown in Figure 10, it is preferred that using chemical grinding technology
The extra bolt conductive material layer 1500 is got rid of, forms the bolt conductive layer 150, it is exhausted that this technique stops at the grid
The upper surface of edge layer 122；Then, as shown in figure 11, using exposure imaging technology, in formation bolt figure on the bolt conductive layer 150
Pattern layer 192；Finally, as shown in figure 12, it is preferred that being performed etching using dry etching technology to the bolt conductive layer 150, formed
The bolt conductive structure 15 and second groove 161 between the bolt conductive structure 15.
Step S4 is performed, second groove 161 between the bolt conductive structure 15 forms bolt insulation system 16.
Specifically, in the present embodiment, first, as shown in figure 13, in the sacrifice side wall 140, the bolt conductive structure
The upper surface of 15 side wall and the Semiconductor substrate 11 forms bolt insulative sidewall material layer 1720, the bolt insulative sidewall material
Silicon nitride can be used in the material of layer 1720, and thickness is between 2 nanometers to 15 nanometers；The preparation of the bolt insulative sidewall material layer 1720
Method includes but not limited to chemical and physical vapor deposition, is not limited to this embodiment.Then, as shown in figure 14,
It is preferred that removing extra bolt insulative sidewall material layer 1720 using chemical grinding technology, the bolt insulative sidewall is formed
172, this technique stops at 122 upper surface of gate insulator；The encirclement of bolt insulative sidewall 172 forms airspace room
171。
Perform step S5, remove the sacrifice side wall 140, in the gate insulation side wall 13 and the bolt conductive structure 15 it
Between formed the air gap 141.
Specifically, as shown in figure 15, in the present embodiment, the sacrifice side wall 140 is removed using wet etching technique
Fall, form the air gap 141.
Perform step S6, on the air gap 141 and the airspace room 171 formed insulation sealing layer 18, with
Airside wall 14 and air insulation structure 17, the insulation are closed into the air gap 141 and the airspace room 171
Sealing layer 18 includes the be located in the air gap 141 first insulation sealing layer 181 and in the airspace room 171
Second insulation sealing layer 182.
Specifically, in the present embodiment, first, as shown in figure 16, in one layer of insulator seal of formation on step S5 resulting structures
Gate material layer 180, the material of the insulation joint filling material layer 180 can be used silicon nitride or silica, form the insulator seal
The method of gate material layer 180 includes atomic layer deposition；It finally, as shown in figure 17, preferably will be extra using chemical grinding technology
The insulation joint filling material layer 180 get rid of, formed it is described insulation sealing layer 18.
It should be strongly noted that as shown in Figure 25~Figure 27, in the present embodiment, atomic layer deposition can be used and form institute
Insulation sealing layer 18 is stated, atomic layer deposition includes multiple reaction cycles, wherein single reaction cycle process includes：
A. the first presoma 23 for being stored in storage box 22 enters reaction chamber 24 by nozzle 25 in a pulsed fashion,
The side wall of the air gap 141 and the sidewall surfaces chemisorbed of the airspace room 171, gradually cover entire crystallizing field
Field surface eventually forms a monoatomic layer；
B. washed away using inert blowing gas except first presoma 23 extra in the reaction chamber 24, in the process
The monoatomic layer remains unchanged；
C. the second presoma being stored in the storage box 22 enters institute by the nozzle 25 in a pulsed fashion
Reaction chamber 24 is stated, is reacted with the monoatomic layer, the complete nitrogen-atoms layer is gradually used up, and ultimately forms an insulation
Film layer is sealed, the second presoma can apply radio-frequency power supply and be ionized, and shorten the reaction time, reduce depositing temperature；
D. washed away using inert blowing gas except second presoma and by-product extra in the reaction chamber 24, herein
The insulation sealed membrane layer remains unchanged in the process.
As shown in Figure 28 a to Figure 28 c, sequentially form multilayer insulation by multiple reaction cycles and seal film layer, and then formed
The airspace room 171 of pointed structures, in practical applications, the number of reaction cycle can be according to material, gap width
Etc. parameters specifically set, be not limited to this embodiment.It is divided into three steps in the present embodiment, as shown in figure 28 a, uses
The reaction cycle in deposition insulation joint filling material floor 180 on the side wall (bolt insulative sidewall 172) of the airspace room 171,
The parameter of atomic layer deposition is controlled, the insulation joint filling material floor 180 is made mainly to be deposited on the side wall of the airspace room 171
The one end of (bolt insulative sidewall 172) away from Semiconductor substrate 11 increases the reaction cycle number, the insulation joint filling material layer
180 thickness is continuously increased, and the side wall (bolt insulative sidewall 172) of the airspace room 171 is away from the Semiconductor substrate 11
One end between spacing taper into, form structure as depicted in fig. 28b, continue to increase the reaction cycle number, it is described absolutely
Edge joint filling material floor 180 is by the side wall (bolt insulative sidewall 172) of the airspace room 171 away from the Semiconductor substrate 11
One end completely encloses, and eventually forms the airspace room 171 with pointed structures as shown in Figure 28 c；Forming pen
During the airspace room 171 of pointed structures, while the air gap 141 of a pointed structures can be also formed,
The forming process of the air gap 141 and the forming process of the airspace room 171 are essentially identical, therefore do not repeat herein.
Specifically, condition 1 as shown in figure 25, the parameter of the control atomic layer deposition include first presoma 23
In a pulsed fashion into the reaction chamber 24, and 21 surface of substrate is chemisorbed on, at this time board rear end main valve open ratio
Between 60% to 100%, rear end main valve open ratio is bigger, and 23 preferential chemical of the first presoma described in the reaction chamber 24 is inhaled
The one end of side wall and the side wall of the airspace room 171 away from the Semiconductor substrate 11 of the air gap 141 is attached to,
And the side wall of the air gap 141 and the side wall of the airspace room 171 are close to one end of the Semiconductor substrate 11
A small amount of first presoma 23 of chemisorbed.
Specifically, condition 2 as shown in figure 25, in one embodiment of the invention, the control atomic layer deposition
Parameter includes first presoma 23 in a pulsed fashion into reaction chamber 24, when 21 chemical absorption of surface of substrate reacts
Between include 1 to 3s, reduce the Chemisorption time, since first presoma 23 first contacts the air gap 141
The one end of side wall and the side wall of the airspace room 171 away from the Semiconductor substrate 11, described in the reaction chamber 24
The absorption of one presoma, 23 preferential chemical is in the side wall of the air gap 141 and the side wall of the airspace room 171 away from institute
One end of Semiconductor substrate 11 is stated, and the side wall of the air gap 141 and the side wall of the airspace room 171 are close to described
A small amount of first presoma 23 of one end chemisorbed of Semiconductor substrate 11.
It should be noted that in the present embodiment, atomic layer deposition method deposited silicon nitride is used to form the insulator seal
Mouth layer 18, the first presoma 23 include dichloride silane, and the second presoma includes ammonia, and the sedimentation time of single loop is between 20
Between second to 60 seconds, process temperature is between 400 degree to 700 degree.
It should be noted that in one embodiment of the invention, atomic layer deposition method is used to deposit silica with shape
Into the insulation sealing layer 18, the first presoma 23 includes single propyl amine silicon, and the second presoma includes oxygen, and single loop is sunk
The product time, process temperature was room temperature between 20 seconds to 60 seconds.
As shown in figure 17, the present embodiment also provides a kind of semiconductor transistor construction, and the semiconductor transistor construction is extremely
Include less：Semiconductor substrate 11；Gate structure, positioned at the upper surface of the Semiconductor substrate 11, including grid conducting layer 121,
And the gate insulator 122 on the grid conducting layer 121；Gate insulation side wall 13, positioned at the side wall of the gate structure；
Bolt conductive structure 15 positioned at the both sides of the gate structure, passes through air insulation knot between the adjacent bolt conductive structure 15
Structure 17 carries out electric isolation；Wherein, the gap between the bolt conductive structure 15 and the gate structure is more than the gate insulation
The deposition thickness of side wall 13, to form the air gap 141 between the gate insulation side wall 13 and the bolt conductive structure 15；
And first insulation sealing layer 181, be formed in the air gap 141, air side closed into the air gap 141
Wall 14, since dielectric constant of air is small, the airside wall 14 can effectively reduce the parasitism between grid and bolt conductive structure 15
Capacitance reduces RC delays, and then increases switching speed, reduces switch energy.
Specifically, the Semiconductor substrate 11 is located at the bottom of the semiconductor transistor construction, the Semiconductor substrate
11 material includes but not limited to silicon.In the present embodiment, the upper surface of the Semiconductor substrate 11 is formed with oxide layer (in figure
It does not show).
Specifically, the material of the grid conducting layer 121 includes but not limited to tungsten, is not limited to this embodiment, the grid
The thickness of pole conductive layer 121 is between 15 nanometers to 90 nanometers.The material of the gate insulator 122 includes but not limited to nitrogen
One kind in SiClx, silica and silicon oxynitride, is not limited to this embodiment, the thickness of the gate insulator 122 between
50 nanometers between 300nm.The material of the gate insulation side wall 13 includes but not limited to silicon nitride, silica and silicon oxynitride
In one kind, be not limited to this embodiment, the thickness of the gate insulation side wall 13 is between 2 nanometers to 15 nanometers；The bolt
The material of conductive structure 15 includes but not limited to polysilicon, is not limited to this embodiment.
Specifically, as shown in figure 17, the first insulation first top surface of sealing layer 181, the gate insulation side wall 13
Second top surface, the 3rd top surface of the bolt conductive structure 15, the gate structure the gate insulator 122 the 4th top surface
And the 5th top surface of the bolt insulation system 16 is formed at same ground flat.
Specifically, as shown in figure 17, the 5th top surface of the bolt insulation system 16 includes the annular table of bolt insulative sidewall 172
Face and the top surface of the second insulation sealing layer 182 in annular surface encirclement, the bolt insulative sidewall 172 connect adjacent institute
It states the ora terminalis of bolt conductive structure 15 and is formed at the side wall of the bolt conductive structure 15 and the upper surface of the Semiconductor substrate 11,
Airspace room 171 is formed to surround；It is exhausted that air is closed into the airspace room 171 by the second insulation sealing layer 182
Edge structure 17, since dielectric constant of air is small, the air insulation structure 17 can effectively reduce grid and bolt conductive structure 15 it
Between parasitic capacitance, reduce RC delays, and then increase switching speed, reduce switch energy.
Specifically, the material of the bolt insulative sidewall 172 includes but not limited in silicon nitride, silica and silicon oxynitride
One kind, be not limited to this embodiment, the thickness of the bolt insulative sidewall 172 is between 2 nanometers to 15 nanometers.
The material of the first insulation sealing layer 181 and the second insulation sealing layer 182 includes silicon nitride, silica
And one kind of silicon oxynitride, it is not limited to this embodiment；The first insulation sealing layer 181 and the second insulation sealing layer
182 material includes but not limited to silicon nitride, silica or silicon oxynitride, is not limited to this embodiment, first insulation
Sealing layer 181 and the second insulation sealing layer 182 insert depth between 2 nanometers to 15 nanometers.
Specifically, the height of the air gap is more than the height of the grid conducting layer 121, and less than the grid knot
The height of structure；The width of the air gap is between 2 nanometers to 20 nanometers；In the air gap comprising dichlorosilane,
One or several kinds in ammonia, silane, tetrachloro silicane and nitrogen；Gas pressure in the air gap is between 200 millitorrs
To between a standard atmospheric pressure.
Specifically, as shown in figure 23, the first insulation sealing layer 181 is local is filled in the gate insulation side wall 13 and institute
The air gap opening between bolt conductive structure 15 is stated, the first insulation sealing layer 181 inserts depth no more than water inside
It puts down in the level of 121 top surface of grid conducting layer, the first insulation sealing layer 181 permeates the airside wall 14
Internal chamber wall, the interior occluded air gap with pointed structures of the airside wall 14；The height of the air gap 141 is more than
The height of the grid conducting layer 121, and less than the height of the gate structure, in the present embodiment, the air gap 141
Width between 2 nanometers to 20 nanometers；Dichlorosilane, ammonia, silane, tetrachloro silicane are included in the air gap 141
And the one or several kinds in nitrogen；Gas pressure in the air gap 141 between 200 millitorrs a to standard atmospheric pressure it
Between.
Specifically, as shown in figure 24,182 part of the second insulation sealing layer is inserted the bolt insulative sidewall 172 and is surrounded
The airspace room 171 of formation is open, and the depth of inserting inside of the second insulation sealing layer 182 is no more than level in the grid
The level of 121 top surface of pole conductive layer, the second insulation sealing layer 182 permeate the inner cavity of the air insulation structure 17
Wall, the interior occluded air compartment 171 with pointed structures of the air insulation structure 17；The airspace room 171
Highly it is more than the height of the grid conducting layer 121, and less than the height of the gate structure；The airspace room 171
Width is between 2 nanometers to 20 nanometers；Dichlorosilane, ammonia, silane, tetrachloro silicane are included in the airspace room 171
And the one or several kinds in nitrogen；Gas pressure in the airspace room 171 is between 200 millitorrs a to standard atmospheric pressure
Between.
Embodiment two
As shown in Fig. 2~Figure 13 and Figure 18~Figure 22, the present embodiment provides a kind of preparation sides of semiconductor transistor construction
Method, the preparation method of the semiconductor transistor construction include at least following steps：
Step S1 is performed, semi-conductive substrate 11 is provided, grid conducting layer is sequentially formed in the Semiconductor substrate 11
121 and gate insulator 122, gate structure is formed by etching.
Step S2 is performed, gate insulation side wall 13 is sequentially formed in the side wall of the gate structure and sacrifices side wall 140, it is adjacent
Two it is described sacrifice side walls 140 surround the first groove 151.
Step S3 is performed, bolt conductive layer 150 is formed in first groove 151 surrounded in the sacrifice side wall 140, leads to
Several bolt conductive structures 15 that over etching formation is isolated by several second grooves 161.
Above-mentioned steps S1~step S3 and the specific implementation of step S1~step S3 of embodiment one are essentially identical, therefore
This will not be repeated here.
Step S4 is performed, insulating layer 162 is formed in second groove 161 between each bolt conductive structure 15,
The insulating layer 162 is used as bolt insulation system 16.
Specifically, first, as shown in figure 18, in the sacrifice side wall 140, the side wall of the bolt conductive structure 15 and described
Full insulation material layer 1620, the insulating materials are filled in second groove 161 that the upper surface of Semiconductor substrate 11 surrounds
Silicon nitride can be used in the material of layer 1620, and thickness is between 50 nanometers to 200 nanometers.The preparation of the insulation material layer 1620
Method includes but not limited to chemical and physical vapor deposition, is not limited to this embodiment；Then, as shown in figure 19,
Chemical grinding technology can be used to remove extra insulation material layer 1620, form the insulating layer 162, this technique stops at institute
State 122 upper surface of gate insulator.
Step S5 is performed, the sacrifice side wall 140 is removed, in the gate insulation side wall 13 and the bolt conductive structure 15
Between formed the air gap 141.
Specifically, it as shown in figure 20, it is preferred that being got rid of the sacrifice side wall 140 using wet etching technique, is formed
The air gap 141.
Perform step S6, on the air gap 141 formed insulation sealing layer 18, by the air gap closing into
Airside wall 14.
Specifically, first, as shown in figure 21, in one layer of insulation joint filling material layer 180 of formation on step S5 resulting structures, institute
Silicon nitride or silica can be used in the material for stating insulation joint filling material layer 180.Finally, as shown in figure 22, chemistry can be used to grind
Mill technology gets rid of the extra insulation joint filling material layer 180, forms the insulation sealing layer 18, forms the insulator seal
The method of mouth layer 18 includes atomic layer deposition, and the insulation sealing layer 18 includes the first insulation sealing layer 181.
It should be noted that as shown in Figure 25 to 27, in the present embodiment, atomic layer deposition can be used and form the insulation
Sealing layer 18, Atomic layer deposition method and embodiment one are essentially identical, therefore this will not be repeated here.
As shown in figure 22, the present embodiment also provides a kind of semiconductor transistor construction, the semiconductor transistor of the present embodiment
Semiconductor structure in structure and embodiment one is essentially identical, the difference is that each in the semiconductor transistor construction in the present embodiment
Electric isolation is carried out by insulating layer 162 between bolt conductive structure 15, the filling of insulating layer 162 is formed at by the adjacent bolt
In the groove that conductive structure and the adjacent airside wall are surrounded, therefore this will not be repeated here.
In conclusion the present invention replaces silicon nitride-oxygen in the prior art using the dissymmetrical structure of silicon nitride-airside wall
The symmetrical gate insulation side wall construction of SiClx-silicon nitride is replaced in the prior art using the air insulation structure containing airspace room
Insulating layer since dielectric constant of air is small, can be reduced effectively between grid and bolt conductive structure and bolt conductive structure is led with bolt
Parasitic capacitance between electric structure reduces RC delays, and then increases switching speed, reduces switch energy；The present invention exists
During preparing stud structure, first deposit polycrystalline silicon simultaneously forms conductive structure, is tied after forming bolt insulation between each bolt conductive structure
Structure, when can be to avoid due to being initially formed deposit polycrystalline silicon after bolt insulation system, polysilicon deposition be into the defects of bolt insulation system
Cause and turn between bolt conductive structure, improve the stability and reliability of device；The present invention uses airside wall and air insulation
Structure can effectively reduce between reduction grid and bolt conductive structure and the parasitism between bolt conductive structure and bolt conductive structure
Capacitance in the case where ensureing semiconductor transistor normal work, provides one kind and further reduces semiconductor crystal pipe size,
Improve the effective way of integrated circuit integrated level.So the present invention effectively overcomes various shortcoming of the prior art and has height
Spend industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (22)
- A kind of 1. preparation method of semiconductor transistor construction, which is characterized in that the preparation side of the semiconductor transistor construction Method includes at least following steps：Step S1, semi-conductive substrate is provided, sequentially form grid conducting layer and gate insulator on the semiconductor substrate, Gate structure is formed by etching；Step S2, the side wall in the gate structure sequentially forms gate insulation side wall and sacrifices side wall, adjacent two sacrifices Side wall surrounds the first groove；Step S3, bolt conductive layer is formed in first groove surrounded in the sacrifice side wall, is formed by etching by several Several bolt conductive structures of second groove isolation；Step S4, bolt insulation system is formed in second groove between the bolt conductive structure；Step S5, the sacrifice side wall is removed, to be formed between the gate insulation side wall and the bolt conductive structure between air Gap；Step S6, in forming insulation sealing layer on the air gap, the air gap is closed into airside wall.
- 2. the preparation method of semiconductor transistor construction as described in claim 1, which is characterized in that in the bolt conductive structure Between form the method for the bolt insulation system and include：In step s 4, in the sacrifice side wall, the side wall of the bolt conductive structure and the upper surface shape of the Semiconductor substrate Into bolt insulative sidewall, the bolt insulative sidewall surrounds to form airspace room；And form the insulation sealing layer in step S6 Meanwhile the airspace room is closed into air insulation structure.
- 3. the preparation method of semiconductor transistor construction as described in claim 1, which is characterized in that in each bolt conductive structure it Between form the method for the bolt insulation system and include：In step s 4, in the sacrifice side wall, the side wall of the bolt conductive structure and the upper table bread of the Semiconductor substrate Filling forms insulating layer in second groove enclosed.
- 4. the preparation method of the semiconductor transistor construction as described in claim 1,2 or 3, which is characterized in that formed described exhausted The method of edge sealing layer includes atomic layer deposition, atomic layer deposition is realized by the cycling of multiple deposition process, wherein single follow The deposition process of ring includes sidewall surfaces chemisorbed of first presoma in the air gap and forms monoatomic layer, by lazy Property gas purging remove extra first presoma, the second presoma reacts to form insulator seal with the monoatomic layer Membrana oralis layer is washed away by inert blowing gas except extra second presoma.
- 5. the preparation method of semiconductor transistor construction as claimed in claim 4, which is characterized in that first presoma with The mode of pulse enters reaction chamber, and is chemisorbed on the sidewall surfaces of the air gap, at this time board rear end main valve open Ratio is between 60% to 100%.
- 6. the preparation method of semiconductor transistor construction as claimed in claim 4, which is characterized in that first presoma with The mode of pulse enters reaction chamber, the air gap sidewall surfaces Chemisorption time between 1 second to 3 seconds it Between.
- 7. the preparation method of semiconductor transistor construction as claimed in claim 4, which is characterized in that using atomic layer deposition method Deposited silicon nitride forms the insulation sealing layer, and the first presoma includes dichloride silane, and the second presoma includes ammonia, single The sedimentation time for cycling is between 20 seconds to 60 seconds, and process temperature is between 400 degree to 700 degree.
- 8. the preparation method of semiconductor transistor construction as claimed in claim 4, which is characterized in that using atomic layer deposition method Deposition silica is to form the insulation sealing layer, and the first presoma includes single propyl amine silicon, and the second presoma includes oxygen, For the sedimentation time of single loop between 20 seconds to 60 seconds, process temperature includes 25 degree.
- 9. a kind of semiconductor transistor construction, which is characterized in that the semiconductor transistor construction includes at least：Semiconductor substrate；Gate structure, positioned at the upper surface of the Semiconductor substrate, including grid conducting layer and on the grid conducting layer Gate insulator；Gate insulation side wall, positioned at the side wall of the gate structure；Bolt conductive structure positioned at the both sides of the gate structure, passes through bolt insulation system between the adjacent bolt conductive structure Carry out electric isolation；Wherein, the gap between the bolt conductive structure and the gate structure is more than the gate insulation side wall Deposition thickness, to form the air gap between the gate insulation side wall and the bolt conductive structure；AndFirst insulation sealing layer, is formed on the air gap, the air gap is closed into airside wall.
- 10. semiconductor transistor construction as claimed in claim 9, which is characterized in that the first insulation sealing layer is locally filled out Enter the air gap opening between the gate insulation side wall and the bolt conductive structure, the first insulation sealing layer is inside It inserts depth and is no more than level in the level of the grid conducting layer top surface.
- 11. semiconductor transistor construction as claimed in claim 10, which is characterized in that the first of the first insulation sealing layer Top surface, the second top surface of the gate insulation side wall, the 3rd top surface of the bolt conductive structure and the grid of the gate structure 4th top surface of pole insulating layer is formed at same ground flat.
- 12. semiconductor transistor construction as claimed in claim 11, which is characterized in that the bolt insulation system has the 5th top Face is also formed in same ground flat.
- 13. semiconductor transistor construction as claimed in claim 12, which is characterized in that the 5th top surface of the bolt insulation system Solid object surface comprising insulating layer, the insulating layer filling are formed at by the adjacent bolt conductive structure and the adjacent air side In the groove that wall surrounds.
- 14. semiconductor transistor construction as claimed in claim 13, which is characterized in that the material of the insulating layer be selected from by Silicon nitride, silica and silicon oxynitride form one of group.
- 15. semiconductor transistor construction as claimed in claim 12, which is characterized in that the 5th top surface of the bolt insulation system The surface of annular surface comprising bolt insulative sidewall and the second insulation sealing layer in annular surface encirclement, the bolt are exhausted Edge side wall connects the ora terminalis of the adjacent bolt conductive structure and is formed at the side wall of the bolt conductive structure and semiconductor lining The upper surface at bottom forms airspace room to surround；The second insulation sealing layer closes the airspace room into air Insulation system.
- 16. semiconductor transistor construction as claimed in claim 15, which is characterized in that the second insulation sealing layer is locally filled out Enter the bolt insulative sidewall and surround the airspace room opening to be formed, the depth of inserting inside of the second insulation sealing layer does not surpass Cross it is horizontal in the level of the grid conducting layer top surface, the material of the second insulation sealing layer be selected from by silicon nitride, Silica and silicon oxynitride form one of group.
- 17. semiconductor transistor construction as claimed in claim 15, which is characterized in that the material of the bolt insulative sidewall is selected from In forming one of group by silicon nitride, silica and silicon oxynitride, the thickness of the bolt insulative sidewall is between 2 Nanometer is between 15 nanometers.
- 18. semiconductor transistor construction as claimed in claim 15, which is characterized in that the height of the airspace room is more than The height of the grid conducting layer, and less than the height of the gate structure；The width of the airspace room between 2 nanometers extremely Between 20 nanometers；In the airspace room comprising one kind in dichlorosilane, ammonia, silane, tetrachloro silicane and nitrogen or It is several；The indoor gas pressure in airspace is between 200 millitorrs between a standard atmospheric pressure.
- 19. semiconductor transistor construction as claimed in claim 15, which is characterized in that there is pen in the air insulation structure The occluded air compartment of pointed structures.
- 20. semiconductor transistor construction as claimed in claim 9, which is characterized in that the material of the gate insulation side wall is selected from In forming one of group by silicon nitride, silica and silicon oxynitride, the thickness of the gate insulation side wall is between 2 nanometers To between 15 nanometers；The material of the bolt conductive structure includes polysilicon；It is described first insulation sealing layer material be selected from by Silicon nitride, silica and silicon oxynitride form one of group.
- 21. semiconductor transistor construction as claimed in claim 9, which is characterized in that the height of the air gap is more than institute The height of grid conducting layer is stated, and less than the height of the gate structure；The width of the air gap is received between 2 nanometers to 20 Between rice；The one or several kinds in dichlorosilane, ammonia, silane, tetrachloro silicane and nitrogen are included in the air gap；Institute The gas pressure in the air gap is stated between 200 millitorrs between a standard atmospheric pressure.
- 22. the semiconductor transistor construction as any one of claim 9 to 21, which is characterized in that the airside wall The interior occluded air gap with pointed structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711226548.8A CN108074866B (en) | 2017-11-29 | 2017-11-29 | Preparation method and structure of semiconductor transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711226548.8A CN108074866B (en) | 2017-11-29 | 2017-11-29 | Preparation method and structure of semiconductor transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108074866A true CN108074866A (en) | 2018-05-25 |
| CN108074866B CN108074866B (en) | 2023-12-01 |
Family
ID=62157952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711226548.8A Active CN108074866B (en) | 2017-11-29 | 2017-11-29 | Preparation method and structure of semiconductor transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108074866B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022061738A1 (en) * | 2020-09-25 | 2022-03-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method therefor |
| WO2022166117A1 (en) * | 2021-02-03 | 2022-08-11 | 长鑫存储技术有限公司 | Interconnection structure and preparation method therefor, and semiconductor structure |
| WO2022198877A1 (en) * | 2021-03-25 | 2022-09-29 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure, and semiconductor structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6090698A (en) * | 1999-07-23 | 2000-07-18 | United Microelectronics Corp | Fabrication method for an insulation structure having a low dielectric constant |
| CN102760687A (en) * | 2011-04-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device with air space and manufacture method thereof |
| CN104299911A (en) * | 2013-07-16 | 2015-01-21 | 格罗方德半导体公司 | Gate encapsulation achieved by single-step deposition |
| US20150287676A1 (en) * | 2014-04-07 | 2015-10-08 | Sangho Rha | Semiconductor devices having staggered air gaps |
| US20160181143A1 (en) * | 2014-12-18 | 2016-06-23 | SK Hynix Inc. | Semiconductor device with air gap and method for fabricating the same |
| CN107195550A (en) * | 2017-06-30 | 2017-09-22 | 睿力集成电路有限公司 | A kind of semiconductor device structure and preparation method thereof |
| CN207852645U (en) * | 2017-11-29 | 2018-09-11 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction |
-
2017
- 2017-11-29 CN CN201711226548.8A patent/CN108074866B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6090698A (en) * | 1999-07-23 | 2000-07-18 | United Microelectronics Corp | Fabrication method for an insulation structure having a low dielectric constant |
| CN102760687A (en) * | 2011-04-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device with air space and manufacture method thereof |
| CN104299911A (en) * | 2013-07-16 | 2015-01-21 | 格罗方德半导体公司 | Gate encapsulation achieved by single-step deposition |
| US20150287676A1 (en) * | 2014-04-07 | 2015-10-08 | Sangho Rha | Semiconductor devices having staggered air gaps |
| US20160181143A1 (en) * | 2014-12-18 | 2016-06-23 | SK Hynix Inc. | Semiconductor device with air gap and method for fabricating the same |
| CN107195550A (en) * | 2017-06-30 | 2017-09-22 | 睿力集成电路有限公司 | A kind of semiconductor device structure and preparation method thereof |
| CN207852645U (en) * | 2017-11-29 | 2018-09-11 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022061738A1 (en) * | 2020-09-25 | 2022-03-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method therefor |
| WO2022166117A1 (en) * | 2021-02-03 | 2022-08-11 | 长鑫存储技术有限公司 | Interconnection structure and preparation method therefor, and semiconductor structure |
| WO2022198877A1 (en) * | 2021-03-25 | 2022-09-29 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure, and semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108074866B (en) | 2023-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207852645U (en) | A kind of semiconductor transistor construction | |
| US10879248B2 (en) | Semiconductor devices including capacitors and methods of manufacturing the same | |
| CN103050376B (en) | Deposition materials and formation method | |
| CN108074866A (en) | The preparation method and structure of a kind of semiconductor transistor | |
| CN107968044A (en) | Array of capacitors structure, semiconductor memory and preparation method | |
| CN108063140A (en) | Transistor arrangement, memory cell array and preparation method thereof | |
| CN103050407B (en) | Embedded Transistor | |
| CN101330014A (en) | Method for depositing atomic layer and semiconductor device formed by the same | |
| CN108470686B (en) | A kind of semiconductor device structure and preparation method thereof | |
| CN104347417B (en) | The forming method of MOS transistor | |
| CN109390402A (en) | A kind of semiconductor transistor construction and preparation method thereof | |
| US7531422B2 (en) | Method for fabricating capacitor in semiconductor device using hafnium terbium oxide dielectric layer | |
| CN115244713A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US20170309491A1 (en) | Method of forming tungsten film and method of fabricating semiconductor device using the same | |
| CN103839806B (en) | Semiconductor devices and its manufacture method | |
| CN103204461A (en) | Semiconductor structure and forming method thereof | |
| CN105244265B (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| CN107799531B (en) | A kind of 3D nand memory grade layer stack manufacturing method | |
| JP2004311782A (en) | Method and device for forming film | |
| CN107437529A (en) | A kind of semiconductor structure and its manufacture method | |
| CN112992774B (en) | Method for forming gap | |
| CN105529328B (en) | DRAM device and forming method thereof | |
| TWI821218B (en) | Layer stack | |
| KR20220020829A (en) | Metal Oxide, and Transistors Having Metal Oxide | |
| CN100590848C (en) | Method for forming capacitor and random access memory unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20181008 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: CHANGXIN MEMORY TECHNOLOGIES, Inc. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant before: INNOTRON MEMORY CO.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |