CN107437529A - A kind of semiconductor structure and its manufacture method - Google Patents
A kind of semiconductor structure and its manufacture method Download PDFInfo
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- CN107437529A CN107437529A CN201710791238.4A CN201710791238A CN107437529A CN 107437529 A CN107437529 A CN 107437529A CN 201710791238 A CN201710791238 A CN 201710791238A CN 107437529 A CN107437529 A CN 107437529A
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- air bag
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
Abstract
The present invention, which provides a kind of semiconductor structure and its manufacture method, methods described, includes step：S1：The substrate that a surface is provided with conductive interconnecting structure is provided, the conductive interconnecting structure includes the first conductive layer, and first conductive layer includes the line construction of some discrete settings；S2：Insulation-coated layer is formed on the surface of line construction exposure, the insulation-coated layer is between the line construction formed with groove；S3：Insulation sealing gland layer is formed on the insulation-coated layer using high density plasma CVD method, and the insulation sealing gland layer closes the opening of the groove, so that the air bag that insulate is formed between the circuit between the line construction.The present invention is by adjusting the process conditions in high-density plasma chemical deposition process, position and the size for the air bag that insulate between control circuit can be facilitated, on the premise of conductive structure isolation effect is not influenceed, be effectively improved device RC delay, reduce conducting wire between parasitic capacitance, improve electron transfer rate.
Description
Technical field
The invention belongs to IC manufacturing field, is related to a kind of semiconductor structure and its manufacture method.
Background technology
United States Patent (USP) US6653223B1 discloses a kind of method that dual damascene vias is formed in micro-electronic manufacturing, and it is used
First dielectric layer of patterning carrys out at least a portion of limited hole.Covered with the second dielectric on first dielectric layer of patterning
Layer, and the second dielectric layer at lead to the hole site formed with space, so as to form the through hole of endless full packing.Therefore, when described
When the groove with through hole adjoining is formed in the second dielectric layer, in the through hole reopened that the through hole by endless full packing is formed
During, space provides the size Control of enhancing.That is, in integrated circuit fabrication, space can be utilized to strengthen
To the size Control of dual damascene vias.
Space in dielectric layer can also have other purposes.For example, because the dielectric constant of air only has 1.005, it is remote low
In the dielectric constant 3.9 of silica, according to formulaWherein C is electric capacity, and ε is dielectric constant, and A is metal polar plate
Relative area, d is the distance between metal polar plate (or thickness of dielectric layer), relative to the electricity using silicon dioxide dielectric layers
Container, when capacitor uses air dielectric layer, its electric capacity will substantially reduce.And in integrated circuit (such as dynamic randon access
Memory, abbreviation DRAM) rear road (BEOL) technique in can form metal interconnection structure, it includes multiple layer metal circuit, adjacent
Conductive posts connect between metallic circuit layer, and are isolated by dielectric layer, if making empty structure in the dielectric layer, will obtain more
Low parasitic capacitance, appearance resistance (RC) delay of reduction and faster electron transfer rate, so as to lift device performance.
Therefore, how a kind of semiconductor structure and its manufacture method are provided, it is controllable with forming position in the dielectric layer, size
Circuit between insulate air bag, while ensure that there is good isolation between metal wire, it is urgently to be resolved hurrily to turn into those skilled in the art
An important technological problems.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of semiconductor structure and its manufacture
Method, for solving the problems, such as that RC retardation ratio is serious, parasitic capacitance is big, electron transfer rate is low between metal wire in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacture method of semiconductor structure, including
Following steps：
S1：The substrate that a surface is provided with conductive interconnecting structure is provided, the conductive interconnecting structure includes the first conductive layer, institute
Stating the first conductive layer includes the line construction of some discrete settings；
S2：Insulation-coated layer is formed on the surface of line construction exposure, the insulation-coated layer is in the circuit knot
Formed with groove between structure；
S3：Insulation sealing gland layer is formed on the insulation-coated layer using high density plasma CVD method,
Wherein, the insulation sealing gland layer closes the opening of the groove, to form between the circuit between the line construction gas that insulate
Capsule (Air insulation Between Circuits, ABC), the air bag that insulate between the circuit is in the insulation-coated layer
The line construction is not appeared under limitation, and the air bag that insulated between the circuit has height under the limitation of the insulation sealing gland layer
Upper surface of the degree no more than the line construction.
Alternatively, the line construction includes circuit bottom, circuit main stor(e)y and the circuit top layer being sequentially connected from bottom to top,
The bottom surface of the circuit bottom is formed at the first plane, and the top surface of the circuit top layer is formed at the second plane, between the circuit
The top of insulation air bag is not higher than second plane, and the bottom for the air bag that insulated between the circuit is not less than first plane.
Alternatively, the cross sectional dimensions of the circuit top layer is more than the cross sectional dimensions of the circuit main stor(e)y.
Alternatively, the width range of insulation air bag is 64.5-74.5nm between the circuit, and altitude range is 91-111nm.
Alternatively, the gas between the circuit in insulation air bag includes one kind in oxygen, hydrogen, helium, silane, oxygen
It is or a variety of；Pressure range between the circuit in insulation air bag is 5-30mTorr.
Alternatively, the formation of the insulation-coated layer is to use chemical vapour deposition technique to make with tetraethyl orthosilicate (TEOS)
Deposit to obtain for silicon source, the material of the insulation-coated layer includes silica.
Alternatively, the thickness range of the insulation-coated layer is 68-72nm.
Alternatively, the formation of the insulation sealing gland layer is as oxygen source, using helium using silane as silicon source, using oxygen
As sputter gas to deposit to obtain, the material of the insulation sealing gland layer includes silica for gas or argon gas.
Alternatively, in the formation of the insulation sealing gland layer, the substrate is positioned in reative cell interior base, described
Apply high frequency RF power source on base, apply low frequency radio frequency power supply at the top of reative cell, carry out high-density plasma chemical gas
Mutually deposition obtains the insulation sealing gland layer；The frequency range that the high frequency RF power source uses is 13-14MHz, and the low frequency is penetrated
The frequency range that frequency power uses is 200-400kHz, and the power bracket that the high frequency RF power source uses is 7000-9000W,
By sedimentation rate/sputter rate Ratio control of the insulation sealing gland layer in 2-4.
Alternatively, the insulation-coated layer forms evagination neck in the opening both sides of the groove, with the profit groove
It is hermetic closed.
The present invention also provides a kind of semiconductor structure, including：
Substrate；
Conductive interconnecting structure, it is arranged on a surface of the substrate；The conductive interconnecting structure includes the first conductive layer,
First conductive layer includes the line construction of some discrete settings；
Insulation-coated layer, the surface of the line construction exposure is formed at, the insulation-coated layer is in the line construction
Between formed with groove；
Insulate sealing gland layer, is formed on the insulation-coated layer, wherein, the insulation sealing gland layer closes opening for the groove
Mouthful, to form between the circuit between the line construction air bag that insulate, the air bag that insulated between the circuit is described insulation-coated
The line construction is not appeared under the limitation of layer, and the air bag that insulated between the circuit has under the limitation of the insulation sealing gland layer
There is the upper surface that height is no more than the line construction.
Alternatively, the line construction includes circuit bottom, circuit main stor(e)y and the circuit top layer being sequentially connected from bottom to top,
The bottom surface of the circuit bottom is formed at the first plane, and the top surface of the circuit top layer is formed at the second plane, between the circuit
The top of insulation air bag is not higher than second plane, and the bottom for the air bag that insulated between the circuit is not less than first plane.
Alternatively, the conductive interconnecting structure includes rear cable architecture, and the material of the circuit main stor(e)y is included in copper, aluminium extremely
Few one kind, the metal that the circuit bottom is used to limit the circuit main stor(e)y with the circuit top layer spread.
Alternatively, the cross sectional dimensions of the circuit top layer is more than the cross sectional dimensions of the circuit main stor(e)y.
Alternatively, the width range of insulation air bag is 64.5-74.5nm between the circuit, and altitude range is 91-111nm.
Alternatively, the gas between the circuit in insulation air bag includes one kind in oxygen, hydrogen, helium, silane, oxygen
It is or a variety of；Pressure range between the circuit in insulation air bag is 5-30mTorr.
Alternatively, the bottom width scope of the groove is 118-138nm, and altitude range is 500-540nm.
Alternatively, the thickness range of the insulation-coated layer is 68-72nm.
Alternatively, the hardness of the insulation sealing gland layer is more than the hardness of the insulation-coated layer.
Alternatively, the material of the insulation-coated layer and the insulation sealing gland layer all includes silica, the insulation gas
The crystallinity of sealing is more than the crystallinity of the insulation-coated layer.
Alternatively, the insulation-coated layer forms evagination neck in the opening both sides of the groove, with the profit groove
It is hermetic closed.
As described above, the semiconductor structure and its manufacture method of the present invention, have the advantages that：The present invention's partly leads
Body structure and its manufacture method pass through tune by introducing between circuit the air bag that insulate between the line construction of conductive interconnecting structure
The process conditions during high density plasma CVD are saved, the position of insulation air bag between control circuit can be facilitated
And size, and so that insulation air bag is uniformly distributed among wafer to crystal round fringes between circuit, reaching is not influenceing conductive structure
On the premise of isolation effect, parasitic capacitance, the raising electric transmission for be effectively improved device R C delays, reducing between conducting wire are fast
The technique effect of rate.
Brief description of the drawings
Fig. 1 is shown as the process chart of the manufacture method of the semiconductor structure of the present invention.
Fig. 2 is shown as DRAM basic structure schematic diagram.
Fig. 3 is shown as including schematic diagram during three-layer metal layer in rear line layer.
The surface that Fig. 4 is shown as providing in the manufacture method of the semiconductor structure of the present invention is provided with the lining of conductive interconnecting structure
The structural representation at bottom.
Fig. 5 is shown as being formed absolutely on the surface of line construction exposure in the manufacture method of the semiconductor structure of the present invention
The schematic diagram of edge coating.
Fig. 6 is shown as in the manufacture method of the semiconductor structure of the present invention deposition and the insulation-coated layer in a control wafer
The schematic diagram of the film of identical material.
Fig. 7 a are shown as in the manufacture method of the semiconductor structure of the present invention forming insulation gas on the insulation-coated layer
The schematic diagram of sealing.
Fig. 7 b are shown as the top view of the plane where circuit main stor(e)y described in the line construction.
Fig. 8 is shown as equipment construction block diagram and crystalline substance employed in the manufacture method step S3 of the semiconductor structure of the present invention
The schematic diagram that circle circulates wherein.
Fig. 9 is shown as using high density plasma CVD in the manufacture method of the semiconductor structure of the present invention
Method (HDPCVD) deposits the schematic diagram of the insulation sealing gland layer in the reaction chamber.
Figure 10 is shown as high frequency RF power source described in the manufacture method of the semiconductor structure of the present invention using being more than 9000W
Power when, it is described insulation the sealing gland layer schematic diagram that most groove fills up at last.
Figure 11 is shown as high frequency RF power source described in the manufacture method of the semiconductor structure of the present invention and uses 7000-
During 9000W power, the schematic diagram formed with insulation air bag in the insulation sealing gland layer.
Figure 12 is shown as high frequency RF power source described in the manufacture method of the semiconductor structure of the present invention and uses 1000-
During 3000W power, balloon size is excessive or even is difficult to the schematic diagram closed.
Component label instructions
S1~S3 steps
101 front structure sheafs
102 centerline construction layers
Cable architecture layer after 103
104 cellular construction layers
1031 the first metal layers
1032 second metal layers
1033 the 3rd metal levels
1034 metallic circuits
Dielectric between 1035 circuits
1036 metal interlevel dielectrics
1037 embolisms
2 first conductive layers
21 first line structures
22 second line constructions
201 circuit bottoms
202 circuit main stor(e)ies
203 circuit top layers
204 grooves
3 insulation-coated layers
301 evagination necks
4 control wafers
401 middle parts
402 edges
5 insulation sealing gland layers
Insulate air bag between 6 circuits
7 wafers
8 reative cells
9 bases
10 high frequency RF power sources
11 low frequency radio frequency power supplys
12 plasmas
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of manufacture method of semiconductor structure, referring to Fig. 1, being shown as the technological process of this method
Figure, comprises the following steps：
Step S1 is first carried out：The substrate that one surface is provided with conductive interconnecting structure is provided；The conductive interconnecting structure includes
First conductive layer, first conductive layer include the line construction of some discrete settings.
It is pointed out that the manufacture method of the semiconductor structure of the present invention is applied to a variety of semiconductor devices, including but
It is not limited to semiconductor storage unit.As an example, Fig. 2 shows DRAM (Dynamic Random Access Memory, dynamic
Random access memory) basic structure, from bottom to top successively include front structure sheaf 101 (FEOL), centerline construction layer 102
(MOL), cellular construction layer 104 (Cell) and rear cable architecture layer 103 (BEOL), wherein, half is provided with the cellular construction layer 104
Conductor device unit.Include at least one layer of metal level in cable architecture layer 103 after described, as an example, after Fig. 3 is shown as described
Cable architecture layer 103 includes situation during three-layer metal layer, wherein, the first metal layer 1031, the gold medal of second metal layer 1032 and the 3rd
Category layer 1033 is set gradually from bottom to top, and dielectric 1035, phase between metallic circuit 1034 and circuit are included in every layer of metal level
Metal interlevel dielectric 1036 is provided between adjacent two metal layers, and the metallic circuit 1034 in adjacent two layers metal level passes through bolt
Plug 1037, which is realized, to be electrically connected with.
As shown in figure 4, in the present embodiment, first conductive layer 2 using the metallic circuit in cable architecture layer 103 after described as
Example, the substrate include the front structure sheaf 101, centerline construction layer 102 and cellular construction layer 104 successively from bottom to top.
As an example, two groups of line constructions in first conductive layer 2 are shown in Fig. 4：First line structure 21 and
Second line construction 22.
Specifically, the line construction includes circuit bottom 201, circuit main stor(e)y 202 and the line being sequentially connected from bottom to top
Road top layer 203, the bottom surface of the circuit bottom 201 are formed at the first plane, and the top surface of the circuit top layer 203 is formed at second
Plane.
Specifically, the cross sectional dimensions of the circuit top layer 201 is more than the cross sectional dimensions of the circuit main stor(e)y 202.Change
Sentence is talked about, and two side peripheries of the circuit top layer 201 are suspended on the circuit main stor(e)y 202, using the mistake of the circuit main stor(e)y
Degree etching is reached.In effect, the insulation-coated layer for helping to be subsequently formed forms evagination in the shoulder opening both sides of groove 204
Neck.
Specifically, the circuit bottom 201 and the circuit top layer 203 are used for the metal for limiting the circuit main stor(e)y 202
Diffusion.As an example, the material of the circuit bottom 201 and the circuit top layer 203 includes but is not limited to titanium nitride (TiN),
The material of the circuit main stor(e)y 202 includes but is not limited to copper (Cu) or aluminium (Al).In the present embodiment, the circuit bottom 201 and
The circuit top layer 203 is both preferably Ti/TiN laminated construction, and the circuit main stor(e)y 202 preferably uses Cu materials.
Then step S2 is performed：As shown in figure 5, insulation-coated layer 3 is formed on the surface of line construction exposure, it is described
Insulation-coated layer 3 is between the line construction formed with groove.
Specifically, the insulation-coated layer 3 is used to protect the line construction in follow-up high-density plasma chemical gas
It is not damaged in phase deposition process.As an example, the insulation-coated layer 3 is formed using chemical vapour deposition technique.The present embodiment
In, it is preferred to use plasma reinforced chemical vapour deposition method, and silicon source is used as using tetraethyl orthosilicate (TEOS), deposition obtains
The insulation-coated layer 3, the material of the insulation-coated layer 3 include silica.
As an example, the scope of the wet etching rate (Wet Etch Rate, abbreviation WER) of the insulation-coated layer 3 is 2-
2.5nm/min.Wherein, wet etching rate is to characterize and the degree of closeness of stoichiometric, the integrated degree of lattice structure
One important parameter.The detection method of wet etching rate is to immerse the silicon chip for having deposited film in hydrofluoric acid (HF) decoction, warp
After corrosion after a while, the ratio of the variable quantity and etching time that calculate film thickness is worth to.
As shown in figure 5, in the present embodiment, the insulation-coated layer 3 forms evagination neck in the opening both sides of the groove 204
Portion 301 (overhang).The presence of the evagination neck 301 causes the top width of groove 204 to become narrower than bottom width, has
Beneficial to subsequently in the groove 204, during deposition insulation sealing gland layer, it is filled up in groove top in lower trench by insulation sealing gland layer
It is preceding to be just completely covered by insulation sealing gland layer, so as to the air bag that insulated between generation circuit in insulation-coated layer in the trench.Namely
Say, the evagination neck 301 is advantageous to the hermetic closed of the follow-up groove 204.
Although it is pointed out that the thickness of the insulation-coated layer 3 is thicker, protecting effect is better, blocked up is exhausted
Edge coating is by the control for the air bag that is unfavorable for insulating between follow-up gas circuit.In the present embodiment, the thickness model of the insulation-coated layer 3
It is 68-72nm to enclose, and the insulating protective layer is located at the thickness at the edges of substrate position preferably than in the substrate
Between position the small 1-2nm of thickness.
Specifically, can change edge and middle thickness by the adjustment of spacing (Spacing), the spacing refers to shower nozzle
(showerhead) distance of base (pedestal) is arrived, space therein influences whether air current flow.
Surface and on-plane surface due to line construction exposure, in the present embodiment, monitored using a control wafer it is described absolutely
The thickness of edge coating 3.Specifically, as shown in fig. 6, using with the insulation-coated identical sedimentary condition of layer 3 in a control wafer 4
The upper film deposited with the insulation-coated 3 identical material of layer.As an example, under the sedimentary condition, the pars intermedia of control wafer 4
The thickness range of the film of position 401 is 69-70nm, and the thickness range of the film of edge 402 is 68-69nm,
And the flatness of film is less than 2.6%.Herein, the calculation formula of flatness is (range/ (2*mean)) * 100%, wherein
Vertical ranges (unit nm) of the range between insulation protection layer surface peak and minimum point, mean are all measuring points
The average value (unit nm) of position.
As an example, if control wafer is circle, and a diameter of d, then middle part refers to in control wafer described in the present embodiment
The heart is origin, and the scope of a quarter control wafer diameter (d/4), remainder are edge outward.
Step S3 is performed again：As shown in Figure 7a, using high density plasma CVD method in the insulation quilt
Insulation sealing gland layer 5 is formed on coating 3, wherein, the insulation sealing gland layer 5 closes the opening of the groove 204, to be formed described
Insulate air bag 6 between circuit between line construction, insulate between the circuit air bag 6 under the limitation of the insulation-coated layer 3 not
Appear the line construction, and the air bag 6 that insulated between the circuit under the limitation of the insulation sealing gland layer 5 there is height not surpass
Cross the upper surface of the line construction.The height h and width w for the air bag 6 that insulate between the circuit are also show in Fig. 7 a.Fig. 7 b show
It is shown as the top view of a plane at the place of circuit main stor(e)y 202 described in the line construction.The circuit main stor(e)y 202 is strip
Shape, there is the air bag 6 that insulate between the circuit between adjacent lines.
Specifically, the bottom surface of the circuit bottom 201 is formed at the first plane, the top surface of the circuit top layer 203 is formed
The top of insulation air bag 6 is not higher than second plane between the second plane, the circuit, the bottom for the air bag that insulated between the circuit
End is not less than first plane.
As an example, as shown in figure 8, it is shown as what equipment construction block diagram and wafer used by this step circulated wherein
Schematic diagram, the equipment include factory interface (FI), load lock chamber A (Load lock A), load lock chamber B (Load lock
A), transfering state room (Transfer station), processing chamber A (Process chamber A), processing chamber B
(Process chamber B), processing chamber B (Process chamber B) and clean room (PEC station).
Wherein, arrow and circulation direction and the order of wafer in this step (substrate) are indicated with bracket numeral in Fig. 8,
That is：(1) wafer 7 initially enters factory interface, wherein, factory interface is an area of isolation (isolated area), is led to
Cross air inlet (gas-inlet) displaced air；(2) and then wafer enters load lock chamber A, wherein, by being evacuated vacuum
Sample introduction room pressure is consistent with transfering state room pressure；(3) then wafer enters transfering state room, wherein, by being arranged into
Spend table so that wafer is waited in transfering state room into idle processing chamber, and transfering state room can be used for preventing wafer
By dust pollution in waiting process；(4) wafer enters processing chamber A, and the insulation sealing gland is completed in the processing chamber A
The deposition of layer 5；(5) wafer is again introduced into the transfering state room, wherein, by arranging program, wafer is in transfering state room
Interior wait enters idle load lock chamber；(6) wafer enters load lock chamber, wherein, pass through air inlet load lock chamber
Interior air pressure is consistent with air pressure in factory interface, and cools；(7) wafer is sent out by factory interface, so far, wafer, which leaves, to be set
It is standby, into next state of the art.
As an example, as shown in figure 9, high density plasma CVD method (HDPCVD) is shown with anti-
Answer the schematic diagram that the insulation sealing gland floor 5 is deposited in room 8.Wherein, the substrate is positioned in the interior base 9 of reative cell 8, in institute
State on base 9 application high frequency RF power source 10, apply low frequency radio frequency power supply 11 at the top of reative cell, formed in reative cell etc. from
Daughter 12, carry out high density plasma CVD and obtain the insulation sealing gland layer 5；The high frequency RF power source uses
Frequency range be 13-14MHz, the frequency range that the low frequency radio frequency power supply uses is 200-400kHz.
As an example, using silane as silicon source, using oxygen as oxygen source, using helium or argon gas as sputtering gas
Body, deposition obtain the insulation sealing gland layer 5, and the material of the insulation sealing gland layer 5 includes silica.It is described in the present embodiment
The wet etching rate WER of the sealing gland that insulate layer 5 scope is 1.5-1.9nm/min.
As an example, the hardness of the insulation sealing gland layer 5 is more than the hardness of the insulation-coated layer 3, the insulation sealing gland
The crystallinity of layer 5 is more than the crystallinity of the insulation-coated layer 3, can increase the airtight effect of the air bag that insulate between the circuit with
And avoid the upper table facial disfigurement of the formation of the common upper layer circuit structure of insulation sealing gland layer.
Specifically, the high frequency RF power source 10 being carried on the base 9 is mainly used in controlling sputter rate, it is carried in anti-
The low frequency radio frequency power supply 11 at the top of room 8 is answered to be mainly used in controlling the sedimentation rate of silica.In the present embodiment, by adjusting
The power of high frequency RF power source 10 is stated, to control sedimentation rate/sputter rate ratio of the insulation sealing gland layer 5 (hereinafter referred to as
DS ratios), so as to reach the position of insulation air bag 6 and the purpose of size between the control circuit.
As shown in figs. 10-12, it is respectively indicated as the high frequency RF power source and uses the structure finally obtained during different capacity
Schematic diagram, wherein, when Figure 10 is shown as the high frequency RF power source using the power for being more than 9000W, the insulation sealing gland layer 5 is most
The schematic diagram that the groove fills up at last.It is described when Figure 11 is shown as the high frequency RF power source and uses 7000-9000W power
Schematic diagram formed with the air bag 6 that insulated between circuit in the sealing gland that insulate layer 5.Figure 12 is shown as the high frequency RF power source and used
The air bag 6 that insulated during 1000-3000W power, between circuit is oversized or even is difficult to the schematic diagram closed.In processing procedure of the present invention most
Good structure is Figure 11.
The reason for being distinguished more than occurring is：(1) when the high frequency RF power source uses the power more than 9000W, by
It is too high in power, cause DS than too low, that is to say, that sedimentation rate is relatively low with respect to sputter rate, therefore the insulation sealing gland layer
Hole will not occur soon very much because depositing, preferable filling effect is realized so as to cross；(2) when the high frequency RF power source uses
During 1000-3000W power, because power is too low, causing DS than too high, that is to say, that sedimentation rate is too high with respect to sputter rate,
Insulation bag width is excessive between circuit will so be caused, excessive height, or even is difficult to close；(3) when the high frequency RF power source
During using 7000-9000W power, DS is than moderate, between 2~4, can be of moderate size, between completely enclosed circuit absolutely
Edge air bag.
Therefore, in the present invention, the power bracket that the high frequency RF power source 10 should use is 7000-9000W, by described in
Insulate sealing gland layer DS than control in 2-4, it is hereby achieved that the air bag that insulated between position and the controllable circuit of size.The present embodiment
In, the power of the high frequency RF power source 10 is preferably adjusted, DS ratios are controlled in 2.8-3.2.
As an example, it is 4 for depth-to-width ratio:1 or so groove, such as the bottom width scope of groove is 118-138nm,
When altitude range is 500-540nm, the width range of insulation air bag more closes in 64.5-74.5nm between the circuit obtained in groove
Suitable, altitude range is more suitable in 91-111nm.
In the present embodiment, further such that the insulation sealing gland layer is located at the sedimentation rate of the substrate middle part/splash
Firing rate rate odds ratio is located at the sedimentation rate/high 0.1-0.3 of sputter rate ratio at the edges of substrate position, can obtain more equal
The air bag that insulated between even circuit is distributed.
Specifically, sedimentation rate/sputter rate ratio of edge and middle part can be changed by EFRC adjustment, its
In, EFRC refers to electronic flow than controller, for controlling electronic flow ratio (electric flow ratio), especially by control
The ratio among predecessor processed and edge controls.
Specifically, the process gas in part insulation sealing gland layer deposition process can be wrapped up in the air bag that insulated between the circuit
One or more in body, including oxygen, hydrogen, helium, silane, oxygen.Between the circuit insulate air bag in be negative pressure, its pressure
Strong scope is 5-30mTorr.
The manufacture method of the semiconductor structure of the present invention passes through exhausted between the middle introducing circuit between the circuit of conductive interconnecting structure
Edge air bag, and by adjusting the process conditions during high density plasma CVD, control circuit can be facilitated
Between insulate air bag position and size, and cause circuit between insulation air bag be uniformly distributed among wafer to crystal round fringes, reach
On the premise of conductive structure isolation effect is not influenceed, the parasitism for be effectively improved device R C delays, reducing between conducting wire is electric
Hold, improve the technique effect of electron transfer rate.And the presence for the air bag that insulated between circuit can also be reduced in insulation sealing gland layer
Stress, be advantageous to improve device stability.
Embodiment two
The present invention also provides a kind of semiconductor structure, as shown in Figure 7a, is shown as the schematic diagram of the semiconductor structure, wraps
Include：
Substrate；
Conductive interconnecting structure, it is arranged on a surface of the substrate；The conductive interconnecting structure includes the first conductive layer
2, first conductive layer 2 includes the line construction of some discrete settings；
Insulation-coated layer 3, the surface of the line construction exposure is formed at, the insulation-coated layer 3 is in the circuit knot
Formed with groove between structure；
The sealing gland that insulate layer 5, is formed on the insulation-coated layer 3, wherein, the insulation sealing gland layer 5 closes the groove
Opening, to form between circuit between the line construction air bag 6 that insulate, insulated between the circuit air bag 6 it is described absolutely
The line construction is not appeared under the limitation of edge coating 3, and the air bag 6 that insulated between the circuit is in the insulation sealing gland layer 5
Limitation under have height be no more than the line construction upper surface.
Specifically, the conductive interconnecting structure includes rear cable architecture.As an example, first conductive layer 2 is with DRAM
The first metal layer in the rear cable architecture layer of (Dynamic Random Access Memory, dynamic random access memory)
Exemplified by metallic circuit, the substrate includes front structure sheaf 101, centerline construction layer 102 and cellular construction layer successively from bottom to top
104。
Specifically, the line construction includes circuit bottom 201, circuit main stor(e)y 202 and the line being sequentially connected from bottom to top
Road top layer 203, the bottom surface of the circuit bottom 201 are formed at the first plane, and the top surface of the circuit top layer 203 is formed at second
Plane, the top of the air bag 6 that insulate between the circuit be not higher than second plane, and the bottom of insulation air bag 6 is not between the circuit
Less than first plane.
As an example, the material of the circuit main stor(e)y 202 includes copper, at least one of aluminium, the circuit bottom 201 with
The circuit top layer 203 is used for the metal diffusion for limiting the circuit main stor(e)y 202.The cross sectional dimensions of the circuit top layer 203
More than the cross sectional dimensions of the circuit main stor(e)y 202, formed outside in the opening both sides of the groove with the profit insulation-coated layer 3
Prominent neck 301.And the presence of the evagination neck 301 has beneficial to the hermetic closed of the groove.
As an example, it is 4 for depth-to-width ratio:1 or so groove, such as the bottom width scope of groove is 118-138nm,
Insulated when altitude range is 500-540nm, between the circuit obtained in groove air bag 6 width range in 64.5-74.5nm more
Properly, altitude range is more suitable in 91-111nm.
As an example, the gas in the air bag 6 that insulated between the circuit is included in oxygen, hydrogen, helium, silane, oxygen
It is one or more；Pressure range between the circuit in insulation air bag 6 is 5-30mTorr.
Specifically, the insulation-coated layer 3 is used to protect the line construction being subsequently formed the insulation sealing gland layer 5
During be not damaged.As an example, the material of the insulation-coated layer 3 includes silica, it is preferred to use plasma strengthens
Chemical vapour deposition technique is formed.In the present embodiment, the scope of the wet etching rate (WER) of the insulation-coated layer is 2-2.5nm/
min。
Specifically, the thickness range of the insulation-coated layer 3 is 68-72nm.In the present embodiment, the insulation-coated layer position
Thickness in the edges of substrate position is preferably smaller 1-2nm than the thickness positioned at the substrate middle part.
Specifically, the material of the insulation sealing gland layer 5 includes silica, it is preferred to use high-density plasma chemical gas
Phase sedimentation (HDPCVD) formation.In the present embodiment, the scope of the wet etching rate (WER) of the insulation sealing gland layer 5 is 1.5-
1.9nm/min。
As an example, the hardness of the insulation sealing gland layer 5 is more than the hardness of the insulation-coated layer 3, the insulation sealing gland
The crystallinity of layer 5 is more than the crystallinity of the insulation-coated layer 3, can increase the airtight effect of the air bag that insulate between the circuit with
And avoid the upper table facial disfigurement of the formation of the common upper layer circuit structure of insulation sealing gland layer.
The semiconductor structure of the present invention between the circuit in conductive interconnecting structure due to introducing between equally distributed circuit
Insulate air bag, can reach on the premise of conductive structure isolation effect is not influenceed, and is effectively improved device R C delays, reduces conduction
Parasitic capacitance, the technique effect of raising electron transfer rate between circuit.And the presence for the air bag that insulated between circuit can be with
The stress in insulation sealing gland layer is reduced, is advantageous to improve the stability of device.
In summary, semiconductor structure of the invention and its manufacture method between the circuit in conductive interconnecting structure by drawing
Enter the air bag that insulate between circuit, and by adjusting the process conditions during high density plasma CVD, Ke Yifang
Just the position of insulation air bag and size between control circuit, and so that the air bag that insulated between circuit is uniform to crystal round fringes among wafer
Distribution, reaches on the premise of conductive structure isolation effect is not influenceed, and is effectively improved between device R C delays, reduction conducting wire
Parasitic capacitance, improve electron transfer rate technique effect.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (21)
1. a kind of manufacture method of semiconductor structure, it is characterised in that comprise the following steps：
The substrate that one surface is provided with conductive interconnecting structure is provided, the conductive interconnecting structure includes the first conductive layer, and described first
Conductive layer includes the line construction of some discrete settings；
Insulation-coated layer, insulation-coated layer shape between the line construction are formed on the surface of line construction exposure
Into there is groove；
Insulation sealing gland layer is formed on the insulation-coated layer using high density plasma CVD method, wherein, institute
The opening that insulation sealing gland layer closes the groove is stated, it is described to form between the circuit between the line construction air bag that insulate
The air bag that insulated between circuit does not appear the line construction under the limitation of the insulation-coated layer, and the gas that insulated between the circuit
The upper surface that capsule under the limitation of the insulation sealing gland layer there is height to be no more than the line construction.
2. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：The line construction is included under
Circuit bottom, circuit main stor(e)y and the circuit top layer being sequentially connected on and, the bottom surface of the circuit bottom are formed at the first plane, institute
The top surface for stating circuit top layer is formed at the second plane, and the top for the air bag that insulated between the circuit is not higher than second plane, institute
The bottom for stating the air bag that insulate between circuit is not less than first plane.
3. the manufacture method of semiconductor structure according to claim 2, it is characterised in that：The cross section of the circuit top layer
Size is more than the cross sectional dimensions of the circuit main stor(e)y.
4. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：Insulate air bag between the circuit
Width range is 64.5-74.5nm, and altitude range is 91-111nm.
5. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：Between the circuit in insulation air bag
Gas include oxygen, hydrogen, helium, silane, the one or more in oxygen；Pressure model between the circuit in insulation air bag
It is 5-30mTorr to enclose.
6. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：The formation of the insulation-coated layer
It is to use chemical vapour deposition technique to deposit to obtain, the material of the insulation-coated layer using tetraethyl orthosilicate (TEOS) as silicon source
Material includes silica.
7. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：The thickness of the insulation-coated layer
Scope is 68-72nm.
8. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：The formation of the insulation sealing gland layer
It is to use silane as silicon source, use oxygen as oxygen source, use helium or argon gas as sputter gas to deposit to obtain, it is described
The material of insulation sealing gland layer includes silica.
9. the manufacture method of semiconductor structure according to claim 1, it is characterised in that：In the shape of the insulation sealing gland layer
Cheng Zhong, the substrate is positioned in reative cell interior base, applies high frequency RF power source on the base, at the top of reative cell
Apply low frequency radio frequency power supply, carry out high density plasma CVD and obtain the insulation sealing gland layer；The high frequency is penetrated
The frequency range that frequency power uses is 13-14MHz, and the frequency range that the low frequency radio frequency power supply uses is 200-400kHz, institute
The power bracket for stating high frequency RF power source use is 7000-9000W, by sedimentation rate/sputter rate of the insulation sealing gland layer
Ratio control is in 2-4.
10. the manufacture method of the semiconductor structure according to claim 1 to 9 any one, it is characterised in that：The insulation
Coating forms evagination neck in the opening both sides of the groove, with the hermetic closed of the profit groove.
A kind of 11. semiconductor structure, it is characterised in that including：
Substrate；
Conductive interconnecting structure, it is arranged on a surface of the substrate；The conductive interconnecting structure includes the first conductive layer, described
First conductive layer includes the line construction of some discrete settings；
Insulation-coated layer, the surface of the line construction exposure is formed at, the insulation-coated layer is between the line construction
Formed with groove；
Insulate sealing gland layer, is formed on the insulation-coated layer, wherein, the insulation sealing gland layer closes the opening of the groove,
To form between the circuit between the line construction air bag that insulate, the air bag that insulated between the circuit is in the insulation-coated layer
The line construction is not appeared under limitation, and the air bag that insulated between the circuit has height under the limitation of the insulation sealing gland layer
Upper surface of the degree no more than the line construction.
12. semiconductor structure according to claim 11, it is characterised in that：The line construction is included from bottom to top successively
Circuit bottom, circuit main stor(e)y and the circuit top layer of connection, the bottom surface of the circuit bottom are formed at the first plane, the circuit top
The top surface of layer is formed at the second plane, and the top of the air bag that insulated between the circuit is not higher than second plane, between the circuit
The bottom of insulation air bag is not less than first plane.
13. semiconductor structure according to claim 12, it is characterised in that：The conductive interconnecting structure includes rear knot
Structure,
The material of the circuit main stor(e)y includes at least one of copper, aluminium, and the circuit bottom is used to limit with the circuit top layer
Make the metal diffusion of the circuit main stor(e)y.
14. semiconductor structure according to claim 12, it is characterised in that：The cross sectional dimensions of the circuit top layer is more than
The cross sectional dimensions of the circuit main stor(e)y.
15. semiconductor structure according to claim 11, it is characterised in that：The width range of insulation air bag between the circuit
It is 64.5-74.5nm, altitude range is 91-111nm.
16. semiconductor structure according to claim 11, it is characterised in that：Gas bag between the circuit in insulation air bag
Include the one or more in oxygen, hydrogen, helium, silane, oxygen；Pressure range between the circuit in insulation air bag is 5-
30mTorr。
17. semiconductor structure according to claim 11, it is characterised in that：The bottom width scope of the groove is 118-
138nm, altitude range are 500-540nm.
18. semiconductor structure according to claim 11, it is characterised in that：The thickness range of the insulation-coated layer is
68-72nm。
19. semiconductor structure according to claim 11, it is characterised in that：The hardness of the insulation sealing gland layer is more than described
The hardness of insulation-coated layer.
20. semiconductor structure according to claim 11, it is characterised in that：The insulation-coated layer and the insulation sealing gland
The material of layer all includes silica, and the crystallinity of the insulation sealing gland layer is more than the crystallinity of the insulation-coated layer.
21. according to the semiconductor structure described in claim 11 to 20 any one, it is characterised in that：The insulation-coated layer exists
The opening both sides of the groove form evagination neck, with the hermetic closed of the profit groove.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110148584A (en) * | 2019-05-14 | 2019-08-20 | 上海华虹宏力半导体制造有限公司 | The method for forming the air gap |
| CN114040559A (en) * | 2021-11-09 | 2022-02-11 | 广东电网有限责任公司电力科学研究院 | GIL three-binding-point surface plasma processing device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW355813B (en) * | 1997-12-20 | 1999-04-11 | United Microelectronics Corp | Method for manufacturing semiconductor element |
| US6287979B1 (en) * | 2000-04-17 | 2001-09-11 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer |
| US6291030B1 (en) * | 1999-12-21 | 2001-09-18 | Promos Technologies, Inc. | Method for reducing capacitance in metal lines using air gaps |
| CN101197423A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Method for making a self-converged memory material element for memory cell |
| CN103871964A (en) * | 2014-03-11 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Interconnecting wire structure and forming method thereof |
-
2017
- 2017-09-05 CN CN201710791238.4A patent/CN107437529A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW355813B (en) * | 1997-12-20 | 1999-04-11 | United Microelectronics Corp | Method for manufacturing semiconductor element |
| US6291030B1 (en) * | 1999-12-21 | 2001-09-18 | Promos Technologies, Inc. | Method for reducing capacitance in metal lines using air gaps |
| US6287979B1 (en) * | 2000-04-17 | 2001-09-11 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer |
| CN101197423A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Method for making a self-converged memory material element for memory cell |
| CN103871964A (en) * | 2014-03-11 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Interconnecting wire structure and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110148584A (en) * | 2019-05-14 | 2019-08-20 | 上海华虹宏力半导体制造有限公司 | The method for forming the air gap |
| CN114040559A (en) * | 2021-11-09 | 2022-02-11 | 广东电网有限责任公司电力科学研究院 | GIL three-binding-point surface plasma processing device |
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