CN110148584A - The method for forming the air gap - Google Patents
The method for forming the air gap Download PDFInfo
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- CN110148584A CN110148584A CN201910399070.1A CN201910399070A CN110148584A CN 110148584 A CN110148584 A CN 110148584A CN 201910399070 A CN201910399070 A CN 201910399070A CN 110148584 A CN110148584 A CN 110148584A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention provides a kind of method for forming the air gap, method includes the following steps: providing a substrate, is formed with gate structure, functional layer and the first plug in the substrate；An interconnection line is formed in the functional layer；It is subsequently formed a mask layer；The functional layer of the mask layer and segment thickness is etched to form groove；Execute cineration technics；Dielectric layer, wherein form the air gap in dielectric layer in the groove.Cineration technics is executed to the groove and the interconnection line surface, remaining high polymer impurity when etching the mask layer and the functional layer can be effectively removed, the pattern of the air gap formed when avoiding high polymer impurity to subsequent dielectric layer in the trench has an impact, and balances the pressure between the dielectric layer and the interconnection line.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of method for forming the air gap.
Background technique
During the manufacturing of semiconductor structure, there is an important technique: being formed between air in the semiconductor structure
Gap.Gate structure, the functional layer of the covering gate structure are generally formed on substrate in semiconductor structure, positioned at the function
Interconnection line on ergosphere, the dielectric layer of the covering interconnection line, the first plug in the functional layer and it is located at dielectric layer
In the second plug (wherein, the first plug, interconnection line and the second plug are electrically connected.).The air gap is typically formed
In the dielectric layer and it is being formed between adjacent interconnection line.Why the air gap is needed to form, is because adjacent is mutual
There are a parasitic capacitances between line, and parasitic capacitance can generate interference electric current, so that electromagnetic interference is generated, especially in high frequency feelings
Very big influence is be easy to cause under condition to the overall performance of semiconductor devices.In dielectric layer between adjacent interconnection line
The air gap, which can reduce, even is eliminated parasitic capacitance, and the volume of the air gap is bigger, pattern is more complete, can more reduce interconnection
Parasitic capacitance between line plays the role of the electrical property for optimizing semiconductor devices to reduce the electromagnetic interference of circuit.
But the study found that the pattern of the air gap in existing semiconductor devices is imperfect, especially the air gap
Top is easy defect, and high polymer impurity is easy the partial air gap between blocking interconnection line and constitutes second plug of corrosion
Adhesion layer, influence the second plug electrical property, to influence the electrical property of semiconductor devices.In addition, the incomplete sky of pattern
The stress of the complete the air gap of gas gap-ratio pattern is big, this will cause the unequal power distribution between dielectric layer and interconnection line, is easy
Part interconnection line is caused to be squeezed and precipitate into the air gap, thus the electric leakage between causing interconnection line.
Summary of the invention
The purpose of the present invention is to provide a kind of methods for forming the air gap, to improve between the air in semiconductor devices
The pattern of gap.
In order to solve the above technical problems, the present invention provides a kind of method for forming the air gap, step includes:
One substrate is provided, gate structure, the functional layer of the covering gate structure are formed on the substrate and positioned at institute
State the first plug in functional layer；
Interconnection line is formed in the functional layer, the interconnection line and first plug are electrically connected；
A mask layer is formed, the mask layer covers the interconnection line and the functional layer；
The functional layer of mask layer and segment thickness described in dry etching is to form groove；
Execute cineration technics；And
Dielectric layer, the dielectric layer fill the groove and the covering mask layer, wherein are located in the groove
The dielectric layer in form the air gap.
Optionally, in the method for forming the air gap, Cl is utilized2And BCl3It etches the mask layer and part is thick
The functional layer of degree.
Optionally, in the method for forming the air gap, the thickness of the functional layer above the gate structure
BetweenBetween, the depth of the groove is greater thanThe depth-to-width ratio of the groove is greater than 2.
Optionally, in the method for forming the air gap, the duration of cineration technics is executed between 30s~600s.
Optionally, in the method for forming the air gap, cineration technics is executed using oxygen-containing gas.
Optionally, in the method for forming the air gap, after execution cineration technics, before dielectric layer, also
Include:
Execute wet clean process.
Optionally, in the method for forming the air gap, the duration of the wet clean process between 18min~
22min。
Optionally, in the method for forming the air gap, wet clean process is executed using alkali organic solvent.
Optionally, in the method for forming the air gap, after dielectric layer, further includes:
The second plug being electrically connected with the interconnection line is formed, second plug is located in the dielectric layer.
Optionally, in the method for forming the air gap, the material of the mask layer be silica, silicon nitride or
Silicon oxynitride.
Optionally, in the method for forming the air gap, the functional layer includes the silicon nitride layer sequentially formed, oxygen
SiClx layer and carbon doped silicon oxide layer.
To sum up, the present invention provides a kind of method for forming the air gap, the functional layer shape of etching mask layer and segment thickness
After groove, cineration technics is executed to the groove and the interconnection line surface, then dielectric layer, thus in the groove
The air gap is formed in interior dielectric layer.It, can be effective by executing cineration technics to the groove and the interconnection line surface
Removal etches the high polymer impurity formed when the mask layer and the functional layer, avoids high polymer impurity to subsequent described
The air gap pattern formed when dielectric layer in groove has an impact, and ensure that the top integrality of the air gap, improves
Product yield.Further, it forms the complete the air gap of pattern and also balances answering between the dielectric layer and interconnection line
Power precipitate into the risk that electric leakage is caused in the air gap so as to avoid the interconnection line stress imbalance.Further, to institute
It states groove and the interconnection line surface executes cineration technics and it is miscellaneous to avoid high polymer so that high polymer impurity is effectively removed
Texture at adhesion layer corrode the risk of second plug, optimize the electrical property of semiconductor devices.
Detailed description of the invention
Fig. 1 is the flow chart of the method for the formation the air gap of the embodiment of the present invention；
Fig. 2-Fig. 8 is the semiconductor structure signal in each step of the method for the formation the air gap of the embodiment of the present invention
Figure；
Wherein, description of symbols:
100- substrate, 110- gate structure, 120- functional layer, 121- silicon nitride layer, 122- silicon oxide layer, the doping of 123- carbon
Silicon oxide layer, the first plug of 130-, 140- conductive layer, 141- interconnection line, 150- mask layer, 160- dielectric layer, between 161- air
Gap, the second plug of 170-, 200- groove.
Specific embodiment
Inventor is the study found that the step of forming the air gap in the dielectric layer generally comprises: semiconductor substrate is provided,
Functional layer, interconnection line and mask layer are formed on the semiconductor base；The functional layer of etching mask layer and segment thickness is with shape
At groove；Dielectric layer, the dielectric layer cover the interconnection line and fill the groove, wherein because of the groove of formation
Depth-to-width ratio is bigger, so can to generate the air gap in dielectric layer when filling dielectric layer in the trench.Currently, etching is covered
During film layer and the functional layer of segment thickness, the part waste material of the mask layer being etched and functional layer become in groove with
And the high polymer impurity on interconnection line.But in prior art, the high polymer impurity formed before dielectric layer exists
It can not be completely removed clean situation, when leading to dielectric layer, the air gap is squeezed by remaining high polymer impurity
It presses and the case where the air gap is by Partial Blocking occurs, so as to cause the air gap formed in the dielectric layer in semiconductor devices
Pattern it is imperfect, especially be easy to cause the top pattern defect of the air gap, be blocked in the high polymer impurity of the air gap
Can constitute has certain corrosive adhesion layer to metal, easily corrodes the integrated circuit of semiconductor devices, product yield is caused to drop
It is low.In addition, high polymer impurity also exacerbates the unequal power distribution between the dielectric layer and interconnection line, it is easy to happen the interconnection
Line stress imbalance precipitate into the case where electric leakage is caused in the air gap.
Based on above-mentioned discovery, applicant provides a kind of method for forming the air gap, etching mask layer and segment thickness
After functional layer forms groove, cineration technics is executed to the groove and the interconnection line surface, can be effectively removed described in etching
The high polymer impurity formed when mask layer and the functional layer avoids high polymer impurity and is situated between to subsequent deposition in the trench
The pattern of the air gap formed when electric layer has an impact, and increases the volume of the air gap, and is conducive to avoid high polymer miscellaneous
Texture at adhesion layer corrode the second plug risk.
The method proposed by the present invention for forming the air gap is made below in conjunction with the drawings and specific embodiments further detailed
Explanation.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is adopted
With very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.In addition, the structure that attached drawing is shown is often a part of practical structures.Particularly, each attached drawing needs what is shown to stress
Point is different, uses different ratios sometimes.
Fig. 1 is the flow chart of the method for the formation the air gap of the embodiment of the present invention, with reference to Fig. 1, between the formation air
The method of gap includes the following steps:
S10: providing a substrate, and gate structure, the functional layer of the covering gate structure and position are formed on the substrate
The first plug in the functional layer；
S20: forming interconnection line in the functional layer, and the interconnection line and first plug are electrically connected；
S30: forming a mask layer, and the mask layer covers the interconnection line and the functional layer；
S40: the functional layer of mask layer and segment thickness described in dry etching is to form groove；
S50: cineration technics is executed；
S60: dielectric layer, the dielectric layer fill the groove and the covering mask layer, wherein are located at the ditch
The air gap is formed in the dielectric layer in slot.
Further, Fig. 2-Fig. 8 is please referred to, Fig. 2-Fig. 8 is each of the method for the formation the air gap of the embodiment of the present invention
Semiconductor structure schematic diagram in step.
Firstly, providing a substrate 100 with reference to Fig. 2, gate structure 110, the covering grid are formed on the substrate 100
The functional layer 120 of pole structure 110 and the first plug 130 in the functional layer 120.Specifically, the substrate 100 is for example
One such for silicon substrate, silicon-Germanium substrate, germanium substrate, 100 surface of substrate can also form several epitaxial layers to improve
The electric property of semiconductor devices.The gate structure 110 be, for example, include stack setting gate dielectric layer and gate electrode and
The side wall of the gate electrode is surrounded, the material of the gate electrode is, for example, the compound of polysilicon, metal or polysilicon and metal,
The material of the gate dielectric layer is, for example, silica or high K dielectric material.The functional layer 120 is, for example, including sequentially forming
Silicon nitride layer 121, silicon oxide layer 122 and carbon doped silicon oxide layer 123, wherein the silicon oxide layer 122 covers the silicon nitride
Layer 121, the silicon oxide layer 122 covers the carbon doped silicon oxide layer 123, and the silicon nitride layer 121 covers the grid knot
Structure 110 and 100 surface of semiconductor substrate not covered by gate structure 110.Wherein, the silicon nitride 121, the silicon oxide layer
122 and carbon doped silicon oxide layer 123 not only act as and protect the effect of the gate structure 110 (by the gate structure 110 with after
The continuous conductive layer needed to form is kept apart), and play the substrate 100 when preventing from being subsequently formed through-hole structure and accidentally etched
Effect.In the present embodiment, the functional layer 120 is deposited in the way of plasma activated chemical vapour deposition.
Further, the carbon doped silicon oxide layer 123, silicon oxide layer 122 and described are etched using dry etch process
Silicon nitride layer 121 is to 100 surface of substrate, in the carbon doped silicon oxide layer 123, silicon oxide layer 122 and the nitridation
Through-hole structure is formed in silicon layer 121, fills metal in the through-hole structure to form the first plug 130.Wherein, described first
The material of plug 130 is preferably tungsten, i.e., the metal filled in the described through-hole structure be tungsten, first plug 130 for realizing
The electric connection of interconnection line 141 in semiconductor devices between different layers.
Further, be deposited on the thickness of the functional layer 120 on the gate structure 110 betweenBetween, wherein the sum of the silicon nitride layer 121 and the thickness of the silicon oxide layer 122 are typically in the range ofThe thickness of the carbon doped silicon oxide layer 123 is typically in the range ofThe carbon adulterates oxygen
SiClx layer 123 is mainly used for being subsequently formed deeper groove moulding to be managed in the dielectric layer when dielectric layer in the trench
The air gap thought, so the carbon doped silicon oxide layer 123 spreads with a thickness of being subsequently formed the high groove of depth-to-width ratio example
Pad.
Then, with reference to Fig. 3, a conductive layer 140, the 140 covering function layer 120 of conductive layer and first plug are formed
130, specifically, the material of the conductive layer 140 may include aluminium, copper or tungsten.In the present embodiment, the conductive layer 140
Material be aluminium, the resistance conductive layer rate made of metallic aluminium is low, the resistance for the integrated circuit being subsequently formed can be effectively reduced,
It is also easier to be etched to form subsequent interconnection line simultaneously.Further, with reference to Fig. 4, in the 140 spin coating photoetching of conductive layer
Glue carries out photoetching to obtain patterned photoresist layer, at this point, patterned photoresist to obtain photoresist layer, to photoresist layer
Layer defines shape and the position of interconnection line 141 in the conductive layer 140, utilizes by exposure mask of patterned second photoresist layer
Dry etch process etching conductive layer 140, and it is passed through Cl2、BCl3And N2Etching is participated in, is obtained with first plug 130 electrically
The interconnection line 141 of connection.
Then, as shown in figure 5, forming a mask layer 150, the mask layer 150 covers the interconnection line 141 and the function
Ergosphere 120, the mask layer 150 are hard mask layer, and the material of hard mask layer may include silica, silicon nitride or nitrogen oxidation
Silicon, the mask layer 150 can play the role of exposure mask when etching the conductive layer 140 to protect the interconnection line 141 to be missed
Etching.In the present embodiment, it is formed by chemical vapor deposition the mask layer 150.
Then, with reference to Fig. 6, the functional layer 120 of mask layer 150 described in dry etching and segment thickness is to form groove
200.Specifically, one layer photoresist of spin coating on mask layer 150, is formed on the photoresist corresponding by exposure and imaging technique
Pattern, and the pattern on photoresist is transferred on the mask layer 150, i.e., by etching technics in the mask layer 150
And the functional layer 120 forms groove 200 corresponding with the pattern on photoresist, wherein when etching the functional layer 120, only
The carbon doped silicon oxide layer 123 of etched portions thickness.In the present embodiment, it etches the mask layer 150 and the carbon is mixed
The dry etch process such as plasma etch process can be selected when miscellaneous silicon oxide layer 123.Meanwhile being passed through Cl2And BCl3It participates in carving
Erosion.
Preferably, the depth of the groove 200 in the interconnection line 141 and the functional layer 120 is greater than
And the depth-to-width ratio of the groove 200 is greater than 2.The biggish groove 200 of depth-to-width ratio may insure subsequent in the groove 200
When filling dielectric layer, the volume of the air gap in the dielectric layer in the groove 200 is larger, even disappears to reduce
Except the parasitic capacitance between the interconnection line 141, it is effectively improved the RC retardation ratio of semiconductor devices, to optimize the whole of semiconductor devices
Body performance.
Then, cineration technics is executed to the groove 200 and 141 surface of the interconnection line to remove the etching mask layer
150 and the carbon doped silicon oxide layer 123 generate high polymer impurity.Specifically, cineration technics is executed using oxygen-containing gas,
Oxygen-containing gas can be the mixed gas of oxygen either oxygen and hydrogen, and ashing time is between 30s~600s.In this reality
It applies in example, the mixed gas that oxygen and hydrogen that ratio is 30:1 can be used participates in cineration technics, meanwhile, it is passed through hydrogen and oxygen
Mixed gas in, oxygen gas flow rate between 6000ml/min~9000ml/min, hydrogen flow rate between 200ml/min~
400ml/min, pressure is between 6pa~20pa, and power is between 7.5kw~15.5kw.The mixed gas of hydrogen and oxygen can
To react with remaining high polymer impurity high polymer impurity is efficiently removed.To the groove 200 and described
150 surface of mask layer executes that cineration technics can be effectively removed the etching mask layer 150 and the functional layer 120 formed
High polymer impurity avoids high polymer impurity and generates shadow to the pattern of the subsequent the air gap formed in the dielectric layer of deposition
The case where sound, ensure that the top integrality of the air gap, and the second plug for also avoiding being subsequently formed is corroded, to optimize
The electrical property of semiconductor devices.
Preferably, executing cineration technics and then to execute wet process to the groove 200 and 141 surface of the interconnection line clear
Technique is washed, the high polymer impurity generated when further can remove to form groove 200.Specifically, to the groove 200 and institute
It states 141 surface of interconnection line and executes the duration of wet clean process between 18min~22min.In the present embodiment, because of the ditch
It include acidic residues pollutant in the high polymer impurity on 141 surface of slot 200 and the interconnection line, so utilizing alkali organic solvent
Wet clean process is executed to the groove 200 and 141 surface of the interconnection line, can more effectively remove high polymer impurity.
Further, with reference to Fig. 7, dielectric layer 160, the dielectric layer 160 is filled described in the groove 200 and covering
Interconnection line 141, wherein the air gap 161 is formed in the dielectric layer 160 in the groove 200.Specifically, the dielectric layer
160 can be formed using chemical vapor deposition (CVD) technique, in the present embodiment, select plasma activated chemical vapour deposition
(PECVD) dielectric layer 160 described in process deposits, the material of the dielectric layer 160 are typically chosen the silica of doping fluorine, adulterate fluorine
Silica dielectric layer dielectric constant K it is lower because parasitic capacitance C and dielectric constant K are proportional, dielectric layer
The low parasitic capacitance advantageously reduced in the interconnection line 141 of 160 dielectric constant, to optimize the electricity of the semiconductor devices
Performance.The depth-to-width ratio of the groove 200 is typically greater than 2, it is seen that groove 200 is deep, because of the characteristic of depositing operation, can not keep away
The air gap 161 can be generated when can fill the dielectric layer 160 in groove 200 with exempting from.If etching the mask layer 150 before
And the high polymer impurity that the functional layer 120 is formed has remnants, will receive influence when forming the air gap 161, leads to institute
The final pattern existing defects of the air gap 161 are stated, so before depositing the dielectric layer 160, to the groove 200 and described
150 surface of mask layer executes cineration technics, can effectively effectively remove and etch the mask layer 150 and the functional layer
The 120 high polymer impurity residuals formed, avoid high polymer impurity and have an impact to the pattern of the air gap 161, thus
The volume of the air gap 161 is increased, reduction even has been eliminated parasitic capacitance, and it is dry to reduce electromagnetism caused by unwanted currents
It disturbs.Wet clean process is further executed, then can be better removed high polymer impurity residual.
In the present embodiment, the high polymer impurity for etching the mask layer 150 and the formation of the functional layer 120 is adhered to institute
200 surface of groove is stated, the deposition that may cause the dielectric layer 160 is squeezed, to increase the dielectric layer 160 and mutually
Stress between line 141 causes the interconnection line 141 to precipitate into the air gap 161 by extruding and causes to leak electricity, institute
To execute cineration technics to the groove 200 and 141 surface of the interconnection line, the dielectric layer 160 and the interconnection are reduced
Stress between line 141 avoids the 141 stress imbalance of interconnection line and precipitate into the air gap 161 and causes to leak
The risk of electricity.
Finally, as shown in figure 8, chemical mechanical grinding is carried out to 160 surface of dielectric layer, so that the dielectric layer 160
Surface is smooth as much as possible, etches the dielectric layer 160 then to form the second plug 170, second plug 170 is located at institute
It gives an account of in electric layer 160 and is electrically connected with the interconnection line 141, wherein first plug 130, the interconnection line 141 and institute
It states the second plug 170 and constitutes interconnection structure, the material of second plug 170 can choose tungsten.In etching mask layer and
After functional layer, before the deposition dielectric layer 160, the step of existing formation the air gap in, usually not to the groove
200 and 141 surface of interconnection line the step for executing cineration technics, and in the present invention, to the groove 200 and it is described mutually
141 surface of line, which increases, executes cineration technics, is effectively removed in the groove 200 in this way and the height on 141 surface of the interconnection line
Polymers impurity avoids the formation of the adhesion layer for corroding second plug 170, optimizes the electrical property of second plug 170；Into
Stress between the dielectric layer 160 and the interconnection line 141 of one step can be balanced more, be inserted so as to avoid described second
Plug 170 is squeezed and risk outstanding.
To sum up, a kind of method for forming the air gap of the present invention, executes ashing to the groove and the interconnection line surface
It is miscellaneous can effectively to effectively remove high polymer remaining when etching the mask layer, conductive layer and the functional layer for technique
Matter avoids high polymer impurity and results in blockage to the air gap being subsequently formed, ensure that the integrality of the air gap pattern, together
When, corrosion of the high polymer impurity to the second plug is avoided to optimize the electrical property of the second plug, and it is good to improve product
Rate；Effectively remove high polymer impurity and create a further reduction stress between the dielectric layer and interconnection line, avoid it is described mutually
Line stress imbalance precipitate into the risk that electric leakage is caused in the air gap.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (11)
1. a kind of method for forming the air gap, which is characterized in that step includes:
One substrate is provided, gate structure, the functional layer of the covering gate structure are formed on the substrate and positioned at the function
The first plug in ergosphere；
Interconnection line is formed in the functional layer, the interconnection line and first plug are electrically connected；
A mask layer is formed, the mask layer covers the interconnection line and the functional layer；
The functional layer of mask layer and segment thickness described in dry etching is to form groove；
Execute cineration technics；And
Dielectric layer, the dielectric layer fill the groove and the covering mask layer, wherein the institute in the groove
It gives an account of and forms the air gap in electric layer.
2. the method according to claim 1 for forming the air gap, which is characterized in that utilize Cl2And BCl3It is covered described in etching
The functional layer of film layer and segment thickness.
3. the method according to claim 1 for forming the air gap, which is characterized in that described above the gate structure
The thickness of functional layer betweenBetween, the depth of the groove is greater thanThe depth-to-width ratio of the groove
Greater than 2.
4. the method according to claim 1 for forming the air gap, which is characterized in that execute the duration of cineration technics between
30s~600s.
5. the method according to claim 4 for forming the air gap, which is characterized in that execute grey chemical industry using oxygen-containing gas
Skill.
6. the method according to any one of claim 1 to 5 for forming the air gap, which is characterized in that execute grey chemical industry
After skill, before dielectric layer, further includes:
Execute wet clean process.
7. the method according to claim 6 for forming the air gap, which is characterized in that the duration of the wet clean process
Between 18min~22min.
8. the method according to claim 7 for forming the air gap, which is characterized in that executed using alkali organic solvent wet
Method cleaning process.
9. the method according to claim 1 for forming the air gap, which is characterized in that after dielectric layer, further includes:
The second plug being electrically connected with the interconnection line is formed, second plug is located in the dielectric layer.
10. the method according to any one of claim 1 to 5 for forming the air gap, which is characterized in that the mask layer
Material be silica, silicon nitride or silicon oxynitride.
11. the method according to any one of claim 1 to 5 for forming the air gap, which is characterized in that the functional layer
Including the silicon nitride layer, silicon oxide layer and carbon doped silicon oxide layer sequentially formed.
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Application publication date: 20190820 |