CN115632039A

CN115632039A - Method for manufacturing semiconductor structure

Info

Publication number: CN115632039A
Application number: CN202211251990.7A
Authority: CN
Inventors: 张宏敏
Original assignee: Hangzhou Fuxin Semiconductor Co Ltd
Current assignee: Hangzhou Fuxin Semiconductor Co Ltd
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2023-01-20

Abstract

The application provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; sequentially forming a first etching barrier layer, a first dielectric layer, a second etching barrier layer and a second dielectric layer on the surface of the substrate; forming a first photoresist layer and defining a through hole pattern; forming a through hole; filling a bottom anti-reflection layer in the through hole; carrying out back etching to enable the height of the bottom anti-reflection layer to be lower than the depth of the through hole; forming a second photoresist layer, and forming a groove pattern in the second photoresist layer, wherein the groove pattern is positioned right above the through hole, and the size of the groove pattern is larger than that of the through hole; forming a groove, wherein the groove is positioned at the upper part of the through hole and stops at the second etching barrier layer; removing the residual bottom anti-reflection layer, the first etching barrier layer and the second etching barrier layer in the through hole to form a funnel structure with a groove formed at the upper part of the through hole; and filling the interconnecting metal layer in the funnel structure. The method and the device are beneficial to improving the filling of the interconnection metal and improving the performance of the device.

Description

Method for manufacturing semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor structure.

Background

With the rapid development of semiconductor technology, the feature size of devices is gradually reduced and the integration level of devices is gradually improved, so that the space occupied by a single device is smaller and the structural level is more and more, and therefore, the aspect ratio (the ratio of depth to width) of various Contact holes (contacts) and through holes (Via) of an interconnection structure for connecting different conductive layers is also larger and larger, and the difficulty of deep hole filling process for manufacturing the interconnection structure is gradually increased. On one hand, the deep hole with too narrow opening is not beneficial to filling of interconnection metal; on the other hand, the deep hole filling process is prone to generate defects such as gaps or holes, which cause the electrical performance of the device to be reduced, and even may cause the leakage of the device in serious cases, which affects the reliability of the device.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present application is to provide a method for manufacturing a semiconductor structure, which is used to solve the problems in the prior art that the difficulty of a deep hole filling process is increased, defects such as gaps or voids are easily generated, and the reliability of a device is affected due to the fact that the aspect ratio of an interconnection structure is increased more and more.

To achieve the above and other related objects, the present application provides a method for fabricating a semiconductor structure, comprising the steps of:

providing a substrate;

sequentially forming a first etching barrier layer, a first dielectric layer, a second etching barrier layer and a second dielectric layer on the surface of the substrate;

forming a first photoresist layer on the surface of the second dielectric layer, and carrying out patterning treatment to define a through hole pattern in the first photoresist layer;

etching to form a through hole, wherein the through hole sequentially penetrates through the second dielectric layer, the second etching barrier layer and the first dielectric layer downwards until the first etching barrier layer is exposed;

filling a bottom anti-reflection layer in the through hole;

back-etching the bottom anti-reflection layer to enable the height of the bottom anti-reflection layer to be lower than the depth of the through hole;

forming a second photoresist layer covering the through hole and the second dielectric layer, and carrying out graphical treatment to form a groove graph in the second photoresist layer, wherein the groove graph is positioned right above the through hole, and the size of the groove graph is larger than that of the through hole;

etching to form a groove, wherein the groove is positioned at the upper part of the through hole and stops at the second etching barrier layer, and the size of an upper opening of the groove is larger than that of a lower opening;

removing the residual bottom anti-reflection layer, the first etching barrier layer and the second etching barrier layer in the through hole to form a funnel structure with the groove formed at the upper part of the through hole;

and filling the interconnecting metal layer in the funnel structure.

Optionally, a top anti-reflection layer is further formed between the second dielectric layer and the first photoresist layer.

More optionally, the top anti-reflection layer includes a SiON layer, the bottom anti-reflection layer is an organic material layer including a cross-linked resin, a thermal acid generator, a surfactant, and a solvent, the first etching barrier layer and the second etching barrier layer each include a silicon nitride layer, and the first dielectric layer and the second dielectric layer each include a silicon oxide layer.

Optionally, the etching to form the via hole includes:

etching the top anti-reflection layer by using CF4, CHF3 and O2 gases, and ensuring 10% of over-etching amount so as to form an opening exposing the second dielectric layer in the top anti-reflection layer;

etching the second medium layer by adopting C4F8 and O2 gases, and stopping at the second etching barrier layer;

etching the second etching barrier layer by using CF4, CHF3 and O2 gases, and ensuring 10% of over-etching amount so as to form an opening exposing the first dielectric layer in the second etching barrier layer;

and etching the first dielectric layer by using C4F8 and O2 gases, and stopping at the first etching barrier layer.

Optionally, the etching back the bottom anti-reflection layer comprises:

removing the bottom anti-reflection layer on the second dielectric layer by ashing with 150sccm-200sccm O2, and controlling an etching end point by an end point etching detection system in the process;

o of 150sccm-200sccm is adopted ₂ Carrying out the ashAnd bombarding with argon gas, and etching the bottom anti-reflection layer in the through hole under the action of 100W bias voltage, wherein the bottom anti-reflection layer in the through hole is controlled at a preset height by controlling the etching time in the process.

Alternatively, the method for forming the trench is dry etching using a gas including C4F8 or C4F 6.

Optionally, the width of the top of the formed trench is 300nm to 500nm, the depth of the trench is 800nm, the width of the via is 150nm to 300nm, and the depth of the via below the trench is 400nm.

Optionally, during the formation of the trench by the dry etching, the flow rate of the C4F8 gas is 22sccm, the flow rate of the oxygen gas is 13sccm, the flow rate of the argon gas is 350sccm, and the angle of the formed trench is 83 ° to 84 °.

Optionally, before filling the interconnect metal layer in the funnel structure, a step of forming an adhesion layer on the surface of the funnel structure is further included.

In one alternative, the interconnect metal layer is a tungsten layer and the adhesion layer formed comprises a TiN layer.

In another alternative, the interconnect metal layer is a copper layer and the adhesion layer is formed to include a TaN layer and/or a Ta layer.

As described above, the method for manufacturing a semiconductor structure of the present application has the following beneficial effects: according to the preparation method of the semiconductor structure, the dielectric layer where the through hole is located is partitioned into multiple layers through the etching barrier layer, so that step-by-step etching can be performed in the etching process, and the etching rate of each interval can be better controlled; after the through hole structure is etched, the through hole is filled and etched back by utilizing the characteristic that a bottom anti-reflection layer is easy to fill, then a photoresist layer is formed again, a pattern of a groove which is located at the upper part of the through hole and has the size larger than that of the through hole is formed after development, the structure with the inverted trapezoidal groove is obtained by utilizing the accumulation of etching products (such as polymers) generated in the etching process on the side wall, the etching is stopped on an etching barrier layer, then the photoresist and the bottom anti-reflection layer are removed in situ, finally, the etching barrier layer is etched again, and finally, the funnel structure of the upper inverted trapezoidal groove and the lower through hole is formed. Under the condition that the depth-to-width ratio is the same, the funnel structure is more convenient for filling of a bonding layer and metal, and is beneficial to improving the metal deposition capacity, preventing the metal from generating holes and gaps in the deposition process, reducing the risk of generating defects in the metal filling and grinding processes, and improving the electrical performance and the reliability of a device.

Drawings

Fig. 1 shows a flow chart of a method for fabricating a semiconductor structure provided herein.

Fig. 2 is a schematic cross-sectional structure of the first photoresist layer after patterning.

Fig. 3 is a schematic cross-sectional view illustrating the formation of a via hole.

FIG. 4 is a schematic cross-sectional view of the filling of the bottom anti-reflection layer.

FIG. 5 is a schematic cross-sectional view of the bottom anti-reflective layer after etching back.

Fig. 6 is a schematic cross-sectional view illustrating a trench pattern.

FIG. 7 is a graph showing the relationship between trench angle and oxygen flow during trench etch.

Fig. 8 is a schematic cross-sectional view illustrating the formation of trenches.

Fig. 9 is a schematic cross-sectional view of a funnel structure.

Fig. 10 is a schematic cross-sectional view illustrating the formation of an adhesive layer.

Fig. 11 is a schematic cross-sectional view of a filled interconnect metal.

Fig. 12 is a schematic cross-sectional view of the structure of fig. 11 after a surface planarization process.

Description of the element reference numerals

11-a substrate; 12-a protective layer; 13-a first etch stop layer; 14-a first dielectric layer; 15-a second etch stop layer; 16-a second dielectric layer; 17-a first photoresist layer; 18-via pattern; 19-a through hole; 20-bottom anti-reflection layer; 21-a second photoresist layer; 22-trench pattern; 23-a trench; 24-top anti-reflection layer; 25-interconnect metal layer; 26-an adhesive layer; 27-funnel structure

Detailed Description

The following embodiments of the present application are described by specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure of the present application. The application is capable of other and different embodiments and its several details are capable of modifications and various changes in detail without departing from the spirit of the application. As in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for the convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, quantity and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.

One problem caused by the increasing integration level of semiconductor devices is that more and more structural layers are required, the aspect ratio of contact holes/through holes for connecting different conductive layers is larger and larger, so that the metal filling difficulty of the contact holes/through holes is larger and larger, and poor properties such as slits and/or voids (void) are easy to occur during filling, which leads to the performance reduction and even complete failure of the devices. In the prior art, a dielectric layer for forming a contact hole/a through hole is usually a single structural layer, and the etching mode is single-step etching. Because the thickness of a single dielectric layer is larger, the difficulty of keeping the size consistency of the upper opening and the lower opening in the etching process is higher, and the difficulty of metal filling is increased. In view of the above, the inventors of the present application have made a long-term study and have proposed an improvement.

A flow chart of a method for manufacturing a semiconductor structure provided in the present application is shown in fig. 1, and the method will be described in detail with reference to fig. 1 to 12.

As shown in fig. 1, the present application provides a method for fabricating a semiconductor structure, comprising the steps of:

firstly, performing step S1, providing a substrate 11; the substrate 11 may be a wafer made of semiconductor material such as silicon, germanium, silicon on insulator, silicon carbide, or the like. The substrate 11 is usually pre-fabricated with a circuit structure such as a transistor, a bottom metal layer for electrically leading out the related circuit structure, and a protection layer 12 located on the surface of the substrate 11 for protecting the substrate 11, wherein the protection layer 12 is, for example, a titanium layer and/or a titanium nitride layer, and the protection layer 12 comprising a titanium material can also function as an adhesion layer, thereby facilitating better adhesion of the structure layer in the subsequent process to the substrate 11 and reducing interlayer stress. After providing the substrate 11, the substrate 11 may be cleaned, for example, by washing with diluted hydrofluoric acid, and then dried to remove impurities on the surface of the substrate 11.

Next, step S2 is performed to sequentially form a first etching stop layer 13, a first dielectric layer 14, a second etching stop layer 15 and a second dielectric layer 16 on the surface of the substrate 11, for example, each layer is formed by using a chemical vapor deposition process, so that each layer can be continuously formed in the same chemical vapor deposition apparatus, and the manufacturing process can be simplified. In an example, the first etching stop layer 13 and the second etching stop layer 15 are made of the same material, for example, both are silicon nitride layers, and the thicknesses of the two layers may be the same or different, for example, both are 200nm to 500nm; the first dielectric layer 14 and the second dielectric layer 16 are made of the same material, for example, both are silicon oxide layers, which not only helps to simplify the preparation process, but also helps to further simplify the preparation process and reduce the production cost because the same material can be etched in the same etching manner in the subsequent etching process. The thicknesses of the first dielectric layer 14 and the second dielectric layer 16 may be the same or different, and it is important to set the thicknesses of the first dielectric layer 14 and the second dielectric layer 16 according to the size of the interconnect structure to be formed, and the thicknesses of the two are not limited in this embodiment. In the subsequent etching process, the first dielectric layer 14 and the second dielectric layer 16 are separately etched under the etching blocking effect of the first etching blocking layer 13 and the second etching blocking layer 15, so that not only can the etching difficulty be greatly reduced, but also the etching window can be more flexibly adjusted to obtain a required interconnection structure. The first dielectric layer 14 and the second dielectric layer 16 can be a single structural layer, such as a single silicon oxide layer, which can simplify the manufacturing process. In other alternatives, the first dielectric layer 14 and the second dielectric layer 16 may also be made of different materials, and the first dielectric layer 14 and the second dielectric layer 16 may also be a composite layer including multiple structural layers, for example, the first dielectric layer 14 is a material layer including two different etching selection ratios, for example, the upper portion of the first dielectric layer is a pure silicon oxide layer or a low-doped (boron-doped and/or phosphorus-doped) silicon oxide layer, and the lower portion of the first dielectric layer is a high-doped (boron-doped and/or phosphorus-doped) silicon oxide layer (i.e., the lower-doped concentration is greater than the upper-doped concentration), and during etching, anisotropic dry etching is performed first, and then isotropic wet etching is performed, so that the lower-doped silicon oxide layer is etched faster during wet etching, and a relatively smaller etching amount during dry etching can be compensated, thereby ensuring that etching holes with the same size are formed in the upper and lower openings in the first dielectric layer 14, and ensuring that the bottom of the first dielectric layer 14 is sufficiently opened. Under the condition that the thickness of the second dielectric layer 16 is relatively large, similar composite structure layers with different etching selection ratios can be adopted, and details are not repeated. If the aspect ratio of the required interconnection structure is very large, for example, greater than 10, a third etching barrier layer and a third dielectric layer may be further included above the second dielectric layer 16 to reduce the height of each dielectric layer, and prevent the problems of uneven film thickness and excessive interlayer stress in the deposition process, too large etching difficulty in the subsequent etching process, and the like caused by excessive thickness of each dielectric layer. After the second dielectric layer 16 is formed, a top anti-reflection layer 24 may be further formed on the surface of the second dielectric layer 16 (i.e., the top anti-reflection layer 24 is located between the second dielectric layer 16 and the subsequent first photoresist layer 17), which is helpful for controlling the surface reflectivity of the subsequent photoresist layer and improving the photolithography precision. The top anti-reflection layer 24 is preferably an inorganic material layer, such as SiON layer, and can be formed continuously with the structural layers such as the second dielectric layer 16 in the same vapor deposition equipment, so as to simplify the preparation process. Meanwhile, the SiON layer and the second dielectric layer 16 made of silicon oxide have better adhesion force and smaller stress, which is beneficial to improving the interface characteristics of the device. In addition, the inorganic top anti-reflective layer 24 can be used as a protective mask in the subsequent processes. In other alternatives, the top anti-reflective layer 24 may also be a carbon coating (SOC) material or other organic material, to name a few.

And after the formation of each structural layer, performing step S3, forming a first photoresist layer 17 on the surface of the second dielectric layer 16, and performing patterning processing to define a through hole pattern 18 in the first photoresist layer 17. The first photoresist layer 17 is formed, for example, using, but not limited to, spin coating, to a thickness of, for example, 5000nm to 7000nm, and then exposed and developed to form a via pattern 18, resulting in a structure as shown in fig. 2.

And step S4, etching the first photoresist layer 17 with the through hole pattern 18 to form a through hole 19, wherein the through hole 19 penetrates through the second dielectric layer 16, the second etching barrier layer 15 and the first dielectric layer 14 in sequence, until the first etching barrier layer 13 is exposed, that is, the etching stops at the first etching barrier layer 13. The resulting structure after this step is shown in fig. 3. The specific process of this step is different depending on the materials of the second dielectric layer 16, the second etching stop layer 15 and the first dielectric layer 14. In a preferred embodiment, the first dielectric layer 14 and the second dielectric layer 16 are both silicon oxide layers, and the second etching barrier layer 15 and the first etching barrier layer 13 are silicon nitride layers (silicon oxide and silicon nitride are commonly used materials, and the preparation process is very mature, which helps to reduce the preparation cost), then a preferred etching process of this step, which is verified by a lot of experiments by the inventors, is: firstly, CF4, CHF3 and O2 gas are adopted to etch the top anti-reflection layer 24, and 10% of over-etching amount is ensured, so that an opening exposing the second dielectric layer 16 is formed in the top anti-reflection layer 24; then, etching the second dielectric layer 16 by using C4F8 and O2 gases, and stopping at the second etching barrier layer 15; and then, etching the second etching barrier layer 15 by using CF4, CHF3 and O2 gases, and ensuring 10% of over-etching amount so as to form an opening exposing the first dielectric layer 14 in the second etching barrier layer 15, then, etching the first dielectric layer 14 by using C4F8 and O2 gases, stopping on the first etching barrier layer 13, and then, removing the residual first photoresist layer 17 in situ in the same etching chamber. Namely, the etching process of the step is carried out in the same etching equipment, and the etching process adopting the parameters can ensure that the bottom of the through hole is fully opened.

After the via hole 19 is formed, step S5 is performed to fill a bottom anti-reflection layer 20 (BRAC) in the via hole 19. The bottom anti-reflective layer 20 is preferably an organic material layer, such as an organic material layer including a cross-linking resin, a thermal acid generator, a surfactant, and a solvent, and may be formed in the via hole 19 and on the surface of the second dielectric layer 16 (extending to the surface of the top anti-reflective layer 24 if the top anti-reflective layer 24 is formed) by a spin coating process, including but not limited to. The resulting structure after this step is shown in fig. 4.

Next, step S6 is performed, the bottom anti-reflection layer 20 is etched back to make the height of the bottom anti-reflection layer 20 lower than the depth of the through hole 19, the resulting structure after this step is as shown in fig. 5, and this step can be performed on the same etching apparatus as the etching of step S4. In the case where the bottom anti-reflective layer 20 employs the aforementioned organic material layer, the preferred etch-back step includes the following processes: and removing the bottom anti-reflection layer 20 on the second dielectric layer 16 (also on the top anti-reflection layer 24) by ashing with 150sccm-200sccm of O2 on an etching machine, wherein an etching endpoint is controlled by an endpoint etching detection system in the process, then ashing with 150sccm-200sccm of O2 and bombardment with argon are performed, and etching the bottom anti-reflection layer 20 in the through hole 19 under the bias of 100W to partially remove the bottom anti-reflection layer 20, wherein the bottom anti-reflection layer 20 in the through hole 19 is controlled at a preset height by controlling etching time in the process. The height after the back etching affects the shape of the subsequently etched trench 23, so that the specific height can be defined according to the shape of the trench 23, when the back etching height of the bottom anti-reflection layer 20 is too low, the bottom anti-reflection layer 20 is consumed at the same time in the subsequent etching process of the trench 23, the first etching barrier layer 13 is consumed, the structure of the through hole 19 is formed in advance, and therefore the back etching height cannot be too low or too high. For example, in one example, the top of the etched back bottom anti-reflective layer 20 is made slightly higher than the second etch stop layer 15, for example, 1/4 of the height of the second dielectric layer 16.

Then, step S7 is performed to form a second photoresist layer 21 covering the via hole 19 and the second dielectric layer 16, and a patterning process is performed to form a trench pattern 22 in the second photoresist layer 21, wherein the trench pattern 22 is located right above the via hole 19, and the size of the trench pattern 22 is larger than that of the via hole 19, so that the via hole is completely exposed in the trench pattern. The processes of forming the second photoresist layer 21 and the patterning process are not described in detail, and the structure obtained after this step is shown in fig. 6.

Next, step S8 is performed, the second photoresist layer 21 formed with the trench pattern 22 is etched to form a trench 23, the trench 23 is located on the upper portion of the via 19 and stops at the second etching stop layer 15, and the upper opening size of the trench 23 is larger than the lower opening size. Preferably, the method for forming the trench 23 is dry etching, so that this step can be performed in the etching apparatus of step S6. The step of etching is preferably performed using a high fluorocarbon ratio gas, for example, dry etching using a gas including C4F8 or C4F 6. The etching stop is performed by using a high fluorocarbon ratio gas such as C4F8 or C4F6 gas and O2 as an etching gas and stopping on the second etching stop layer 15, wherein the high fluorocarbon ratio gas is used to form polymers (polymers) which are deposited on the sidewalls of the trench 23 and will prevent the sidewalls from being further etched, and O2 can remove a portion of the polymers and prevent the etching stop caused by excessive polymer deposition, and further, by adjusting O2, for example, according to the relationship diagram of the oxygen flow and the trench 23 angle shown in fig. 7, the inverted trapezoidal trench 23 having a series of angles with the upper opening size larger than the lower opening size can be obtained, and the structure shown in fig. 8 can be obtained. It should be noted that, under the condition that the C4F8 is fixed as the fluorocarbon gas and the relevant process conditions such as pressure are not changed, the angle of the trench 23 can be controlled by adjusting the oxygen flow rate. Within a certain range, as the O2 flow increases, the polymer generated in the etching process can be sufficiently removed, so that the angle of the groove 23 gradually tends to 90 degrees, however, when the O2 flow increases to a certain amount, the O2 increase has no great effect because the amount of the polymer is certain; when the flow of O2 is too small, the polymer cannot be removed in time during the etching process, which causes excessive polymer accumulation and eventually stops etching, but causes electrical failure, so the gas flow is very critical in this step. The inventors have found through a lot of experiments that, in the process of forming the trench 23 by dry etching, when the flow rate of the C4F8 gas is preferably 22sccm, the flow rate of the oxygen gas is 13sccm, and the flow rate of the argon gas is 350sccm, in this case, the angle of the formed trench 23 is 83 ° -84 ° (too large angle is not favorable for filling, and too small angle results in too large lateral occupied dimension of the trench 23, which is not favorable for device miniaturization), the structure is optimal, which is most favorable for metal filling, and is favorable for subsequent process steps, for example, short circuit in the subsequent process steps due to too wide interconnect structure is avoided. And the angle is easier to realize in the process. The trench 23 is preferably formed to have a top width of 300nm to 500nm, a depth of the trench 23 of 800nm, a width of the via 19 of 150nm to 300nm, and a depth of the via 19 under the trench 23 of 400nm.

And step S9 is executed after the etching is finished, the residual bottom anti-reflection layer 20, the first etching barrier layer 13 and the second etching barrier layer 15 in the through hole 19 are removed, and a funnel structure 27 with the groove 23 formed at the upper part of the through hole 19 is formed, namely, the upper opening of the through hole 19 is larger than the lower opening. In this step, preferably, in-situ photoresist removal is directly performed in a machine, the second photoresist layer 21 remaining on the surface is removed by O2, the remaining bottom anti-reflection layer 20 in the through hole 19 is removed by oxygen and argon under the action of bias voltage, and then the first etching barrier layer 13 and the second etching barrier layer 15 are etched, so that the obtained structure is as shown in fig. 9.

Then, step S10 is performed to fill the interconnect metal layer 25 in the funnel structure 27, wherein the interconnect metal layer 25 is electrically connected to the bottom metal layer in the substrate 11.

To ensure good filling of interconnect metal layer 25, adhesion layer 26 may also be formed on the surface of funnel structure 27 (e.g., the sidewall and bottom surfaces thereof) before filling of interconnect metal layer 25 in funnel structure 27. The adhesion layer 26 may be formed by a chemical vapor deposition process and may be made of a material compatible with the interconnect metal layer 25. If the interconnect metal layer 25 is a tungsten layer, for example, the adhesion layer 26 is formed to include a TiN layer; if the interconnect metal layer 25 is a copper layer, the adhesion layer 26 is formed to include a TaN layer and/or a Ta layer. The resulting structure after forming the adhesive layer 26 is shown in fig. 10. Several methods of chemical vapor deposition, physical vapor deposition or electroplating may then be used to deposit metal in the funnel structure 27 and above the second dielectric layer 16, for example, a metal seed layer is formed on the surface of the adhesion layer 26 by chemical vapor deposition, and then the entire funnel structure 27 is filled with metal by electroplating to obtain the structure shown in fig. 11, and then a surface planarization process, for example, chemical Mechanical Polishing (CMP) is performed to remove the metal material above the second dielectric layer 16, and only the metal in the funnel structure 27 is remained as the interconnect metal layer 25, so as to obtain the structure shown in fig. 12.

According to the preparation method of the semiconductor structure, the dielectric layer where the through hole is located is partitioned into multiple layers through the etching barrier layer, so that step-by-step etching can be performed in the etching process, and the etching rate of each interval can be better controlled; after the through hole structure is etched, the through hole is filled and etched back by utilizing the characteristic that a bottom anti-reflection layer is easy to fill, then a photoresist layer is formed again, a pattern of a groove which is located at the upper position of the through hole and has a size larger than that of the through hole is formed after development, the structure with the inverted trapezoidal groove is obtained by utilizing the accumulation of etching products (such as polymers) generated in the etching process on the side wall, the etching is stopped on an etching barrier layer, then the photoresist and the bottom anti-reflection layer are removed in situ, finally the etching barrier layer is etched, and finally the funnel structure with the upper inverted trapezoidal groove (the size of an upper opening is larger than that of a lower opening) + the lower through hole is formed. Under the condition that the depth-to-width ratio is the same, the funnel structure is more convenient for filling of a bonding layer and metal, and is beneficial to improving the metal deposition capacity, preventing the metal from generating holes and gaps in the deposition process, reducing the risk of generating defects in the metal filling and grinding processes, and improving the electrical performance and the reliability of a device.

Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.

Claims

1. A method for fabricating a semiconductor structure, comprising the steps of:

providing a substrate (11);

sequentially forming a first etching barrier layer (13), a first dielectric layer (14), a second etching barrier layer (15) and a second dielectric layer (16) on the surface of the substrate (11);

forming a first photoresist layer (17) on the surface of the second dielectric layer (14), and performing patterning treatment to define a through hole pattern (18) in the first photoresist layer (17);

etching to form a through hole (19), wherein the through hole (19) penetrates through the second dielectric layer (16), the second etching barrier layer (15) and the first dielectric layer (14) downwards in sequence until the first etching barrier layer (13) is exposed;

filling a bottom anti-reflection layer (20) in the through hole (19);

back-etching the bottom anti-reflection layer (22) to enable the height of the bottom anti-reflection layer (20) to be lower than the depth of the through hole (19);

forming a second photoresist layer (21) covering the through hole (19) and the second dielectric layer (16), and carrying out patterning treatment to form a groove pattern (22) in the second photoresist layer (21), wherein the groove pattern (22) is positioned right above the through hole (19), and the size of the groove pattern is larger than that of the through hole;

etching to form a groove (23), wherein the groove (23) is positioned at the upper part of the through hole (19) and stops at the second etching barrier layer (15), and the size of the upper opening of the groove (23) is larger than that of the lower opening;

removing the residual bottom anti-reflection layer (20), the first etching barrier layer (13) and the second etching barrier layer (15) in the through hole (19) to form a funnel structure (27) with the groove (23) formed at the upper part of the through hole (19);

an interconnect metal layer (25) is filled within the funnel structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein a top anti-reflection layer (24) is further formed between the second dielectric layer (16) and the first photoresist layer (17).

3. The method of fabricating a semiconductor structure according to claim 2, wherein the top anti-reflection layer (24) comprises a SiON layer, the bottom anti-reflection layer (20) is an organic material layer comprising a cross-linking resin, a thermal acid generator, a surfactant, and a solvent, the first etch stop layer (13) and the second etch stop layer (15) each comprise a silicon nitride layer, and the first dielectric layer (14) and the second dielectric layer (16) each comprise a silicon oxide layer.

4. A method for fabricating a semiconductor structure according to claim 3, wherein the process of etching to form the via hole (19) comprises:

etching the top anti-reflection layer (24) by using CF4, CHF3 and O2 gases, and ensuring 10% of over-etching amount so as to form an opening exposing the second dielectric layer (16) in the top anti-reflection layer (24);

etching the second dielectric layer (16) by using C4F8 and O2 gases, and stopping at the second etching barrier layer (15);

etching the second etching barrier layer (15) by using CF4, CHF3 and O2 gases, and ensuring 10% of over-etching amount so as to form an opening exposing the first dielectric layer (14) in the second etching barrier layer (15);

and etching the first dielectric layer (14) by using C4F8 and O2 gas, and stopping at the first etching barrier layer (13).

5. A method for fabricating a semiconductor structure according to claim 3, wherein the back etching of the bottom anti-reflection layer (20) comprises the steps of:

removing the bottom anti-reflection layer (20) on the second dielectric layer (16) by adopting O2 of 150sccm-200sccm through ashing, and controlling an etching end point by using an end point etching detection system in the process;

ashing by adopting O2 of 150sccm-200sccm and bombarding by argon, and etching the bottom anti-reflection layer (20) in the through hole under the bias action of 100W, wherein the height of the bottom anti-reflection layer (20) in the through hole is controlled to be a preset height by controlling the etching time.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein the method of forming the trench (23) is dry etching using a gas including C4F8 or C4F 6.

7. The method of claim 6, wherein the trench (23) is formed to have a top width of 300nm to 500nm, a trench depth of 800nm, a via width of 150nm to 300nm, and a via depth of 400nm.

8. The method for fabricating a semiconductor structure according to claim 6, wherein in the step of forming the trench (23) by dry etching, a trench angle is formed at an angle of 83 ° to 84 ° with a flow rate of C4F8 gas of 22sccm, a flow rate of oxygen of 13sccm, and a flow rate of argon of 350 sccm.

9. A method for fabricating a semiconductor structure according to claim 1, further comprising a step of forming an adhesive layer (26) on the surface of the funnel structure (27) before filling the interconnect metal layer (25) in the funnel structure (27).

10. The method of manufacturing a semiconductor structure according to claim 9, wherein the interconnection metal layer (25) is a tungsten layer, and the adhesion layer (26) is formed to include a TiN layer; or the interconnection metal layer (25) is a copper layer, and the adhesion layer (26) is formed to include a TaN layer and/or a Ta layer.