KR100452039B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100452039B1 KR100452039B1 KR10-2002-0085470A KR20020085470A KR100452039B1 KR 100452039 B1 KR100452039 B1 KR 100452039B1 KR 20020085470 A KR20020085470 A KR 20020085470A KR 100452039 B1 KR100452039 B1 KR 100452039B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상부에 금속 시드층 및 금속 배선 영역이 정의된 포토레지스트 패턴을 순차적으로 형성하고 전기 도금법으로 포토레지스트 패턴 사이의 공간을 금속 도금층으로 매립하여 금속 배선을 형성한 후 포토레지스트 패턴을 제거하고 전체 상부에 절연막을 형성함으로써, 화학적 기계적 연마 공정을 생략하면서 금속 배선을 형성하여 화학적 기계적 연마 공정에 의해 디싱(Dishing) 현상이나 침식(Erosion) 현상이 발생되는 것을 방지하고 공정의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and sequentially forms a photoresist pattern defining a metal seed layer and a metal wiring region on a semiconductor substrate on which various elements for forming a semiconductor device are formed, By filling the space between the resist patterns with a metal plating layer to form a metal wiring, removing the photoresist pattern and forming an insulating film over the entire surface, forming metal wiring while omitting the chemical mechanical polishing process, dishing by chemical mechanical polishing process Disclosed is a method for forming a metal wiring of a semiconductor device which can prevent the occurrence of machining or erosion and improve the reliability of the process.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선을 형성하는 과정에서 화학적 기계적 연마 공정에 의해 디싱(Dishing) 현상이나 침식(Erosion) 현상이 발생되는 것을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, a semiconductor device capable of preventing dishing or erosion from being generated by a chemical mechanical polishing process in the process of forming a metal wiring. A metal wiring formation method is related.
반도체 소자가 고집적화되어 감에 따라, 소정의 공정을 진행한 후 반도체 기판 표면을 평탄화하는 것은 매우 중요하다. 현재까지는 반도체 기판의 평탄화 기술로 화학적 기계적 연마(Chemical Mechanical Polishing; CMP)가 개발된 기술 중 가장 효과적인 평탄화 방법이다. CMP는 반도체 기판의 표면에 연마액인 슬러리와 기계적 압력을 가하면서 반도체 기판과 패드를 마찰시켜 반도체 기판의 표면에 형성된 수 천Å의 단차를 제거하거나 금속 배선을 형성하는 기술이다.As semiconductor devices become highly integrated, it is very important to planarize the semiconductor substrate surface after a predetermined process. Until now, chemical mechanical polishing (CMP) has been the most effective planarization method for the semiconductor substrate planarization technology. CMP is a technique of removing the thousands of steps formed on the surface of a semiconductor substrate or forming metal wiring by rubbing the semiconductor substrate and the pad while applying a slurry, which is a polishing liquid, to the surface of the semiconductor substrate.
도 1은 화학적 기계적 연마 공정 시 발생되는 디싱 및 침식 현상을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining dishing and erosion occurring during a chemical mechanical polishing process.
도 1을 참조하면, 반도체 기판(101) 상부의 층간 절연막(102)에 트렌치(102a) 및 비아홀(도시되지 않음)을 형성하고 트렌치(102a)를 전도성 물질로 매립하여 금속 배선(103)을 형성한 후, 층간 절연막(102) 상부에 형성된 전도성 물질을 화학적 기계적 연마 공정으로 제거하는 과정에서 금속 배선(103)의 상부에 디싱(Dishing)에 의한 손실(A)이나 침식(B)이 발생되거나, 층간 절연막(102)의 상부가 식각되어 얇아지는(Thining) 문제점이 발생될 수 있다.Referring to FIG. 1, a trench 102a and a via hole (not shown) are formed in the interlayer insulating layer 102 on the semiconductor substrate 101, and the metal wire 103 is formed by filling the trench 102a with a conductive material. Then, in the process of removing the conductive material formed on the interlayer insulating film 102 by a chemical mechanical polishing process, a loss (A) or erosion (B) due to dishing occurs on the upper portion of the metal wiring 103, The upper portion of the interlayer insulating layer 102 may be etched and thinned.
디싱(A) 현상은 금속과 절연 물질간의 연마 속도 차이에 의해 발생되며, 디싱(A)이 발생될 경우 금속 배선 가운데 부분의 두께가 낮아져 일정한 두께의 금속 배선을 형성할 수 없다. 또한, 후속 층의 완전 평탄화를 이룰 수 없기 때문에, 후속의 화학적 기계적 연마 공정 시 금속 잔류물(Residue)이 발생되어 수율을 감소시키고 공정의 신뢰성을 저하시킬 수 있다.The dishing (A) phenomenon is caused by the difference in polishing rate between the metal and the insulating material. When dishing (A) is generated, the thickness of the center portion of the metal wiring is lowered to form a metal wiring having a predetermined thickness. In addition, since it is not possible to achieve full planarization of subsequent layers, metal residues may be generated in subsequent chemical mechanical polishing processes, resulting in reduced yield and lower process reliability.
한편, 침식(B) 현상은 금속과 절연 물질의 연마속도 차이와 패턴 밀도(Pattern density)의 영향으로 인하여 발생되며, 패턴 밀도가 높은 지역의 금속 패턴과 실리콘 절연막 연마 속도가 타지역보다 높아서 발생된다. 실리콘 절연막이 얇아지는 것은 절연막의 목표 두께(Target oxide thickness)보다 많은 양의 절연막이 연마되어 발생된다. 이로 인해, 저유전(Low-k) 절연막의 두께가 얇아져 원하는 커패시턴스(Capacitance) 값을 얻을 수 없고, RC 지연(RC Delay)에 따른 소자의 동작 속도가 저하되는 문제점이 발생될 수 있다.On the other hand, the erosion (B) phenomenon is caused by the difference in the polishing rate of the metal and the insulating material and the influence of the pattern density. . The thinning of the silicon insulating film is caused by the polishing of the insulating film in an amount larger than the target oxide thickness of the insulating film. As a result, the thickness of the low-k insulating layer becomes thin, so that a desired capacitance value cannot be obtained, and a problem in that an operation speed of the device decreases due to RC delay may occur.
이러한, 금속 CMP 공정의 결함들은 금속 배선 두께를 일정하게 제어(Control)할 수 없고, 배선간의 단락도 유발하여 전기적 특성을 저하시키는 문제점이 있다.Such defects of the metal CMP process may not control the thickness of the metal wires uniformly, and may cause short circuits between wires, thereby degrading electrical characteristics.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상부에 금속 시드층 및 금속 배선 영역이 정의된 포토레지스트 패턴을 순차적으로 형성하고 전기 도금법으로 포토레지스트 패턴 사이의 공간을 금속 도금층으로 매립하여 금속 배선을 형성한 후 포토레지스트 패턴을 제거하고 전체 상부에 절연막을 형성함으로써, 화학적 기계적 연마 공정을 생략하면서 금속 배선을 형성하여 화학적 기계적 연마 공정에 의해 디싱(Dishing) 현상이나 침식(Erosion) 현상이 발생되는 것을 방지하고 공정의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention sequentially forms a photoresist pattern in which a metal seed layer and a metal wiring region are defined on a semiconductor substrate on which various elements for forming a semiconductor device are formed, and then forms a photoresist pattern by electroplating. After filling the space between the metal plating layer to form a metal wiring, by removing the photoresist pattern and forming an insulating film on the whole, the metal wiring is formed while omitting the chemical mechanical polishing process, dishing by chemical mechanical polishing process It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of preventing occurrence of phenomena or erosion and improving process reliability.
도 1은 화학적 기계적 연마 공정 시 발생되는 디싱 현상 및 침식 현상을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining dishing and erosion occurring during a chemical mechanical polishing process.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.2A through 2E are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101, 201 : 반도체 기판 102, 202 : 층간 절연막101, 201: semiconductor substrate 102, 202: interlayer insulating film
102a : 트렌치 103 : 금속 배선102a: trench 103: metal wiring
203 : 장벽 금속층 204 ; 금속 시드층203: barrier metal layer 204; Metal seed layer
205 ; 포토레지스트 패턴 206 : 금속 도금층, 금속 배선205; Photoresist Pattern 206: Metal Plating Layer, Metal Wiring
207 : 확산 방지막 208 : 저유전 물질207: diffusion barrier 208: low dielectric material
209 : PETEOS막 A : 디싱 현상에 의한 손상209: PETEOS film A: damage caused by dishing
B : 침식 현상에 의한 손상B: damage due to erosion
본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 금속 시드층을 형성하는 단계와, 금속 시드층 상부에 금속 배선 영역이 정의된 포토레지스트 패턴을 형성하는 단계와, 전기 도금법으로 포토레지스트 패턴 사이의 공간을 금속 도금층으로 매립하는 단계와, 포토레지스트 패턴을 제거하는 단계와, 포토레지스트 패턴이 제거되면서 노출된 금속 시드층을 제거하는 단계 및 금속 도금층으로 이루어진 금속 배선을 포함한 전체 상부에 절연막을 형성하는 단계를 포함한다.According to an embodiment of the present invention, a method of forming metal wirings of a semiconductor device may include forming a metal seed layer on a semiconductor substrate on which various elements for forming a semiconductor device are formed, and a metal wiring region on the metal seed layer. Forming a resist pattern, filling a space between the photoresist patterns with a metal plating layer by an electroplating method, removing the photoresist pattern, and removing the exposed metal seed layer while the photoresist pattern is removed. And forming an insulating film over the entirety of the metal wiring including the metal wiring layer.
상기에서, 금속 시드층을 형성하기 전에, 장벽 금속층을 더 형성할 수 있으며, 장벽 금속층은 스퍼터 방식으로 Ta 또는 TaN을 증착하여 50 내지 100Å의 두께로 형성할 수 있다.In the above, before forming the metal seed layer, a barrier metal layer may be further formed, and the barrier metal layer may be formed to a thickness of 50 to 100 μm by depositing Ta or TaN in a sputtering manner.
한편, 금속 도금층은 금속 시드층 식각 공정 시 식각될 량을 고려하여 목표 높이보다 높게 형성한다. 이후, 포토레지스트 패턴은 O2플라즈마 처리로 제거하고, 금속 시드층은 Cl2가스를 이용하여 식각할 수 있다. 이때, 금속 시드층 식각 공정은 부산물의 증기 압력을 높여 금속 식각이 원활하게 이루어지도록 200 내지 1000℃의 온도에서 실시할 수 있다.On the other hand, the metal plating layer is formed higher than the target height in consideration of the amount to be etched during the metal seed layer etching process. Thereafter, the photoresist pattern may be removed by an O 2 plasma treatment, and the metal seed layer may be etched using Cl 2 gas. In this case, the metal seed layer etching process may be performed at a temperature of 200 to 1000 ° C. to increase the vapor pressure of the by-products so as to smoothly etch the metal.
금속 시드층을 형성한 후 절연막을 형성하기 전에, 금속 배선을 포함한 전체 상부 표면에 확산 방지막을 더 형성할 수 있으며, 확산 방지막은 SiC로 형성할 수 있다. 한편, 절연막은 전체 상부에 저유전 물질을 스핀 코팅 방식으로 도포한 후 PETEOS막을 증착하여 형성할 수 있다.After forming the metal seed layer and before forming the insulating film, a diffusion barrier may be further formed on the entire upper surface including the metal wiring, and the diffusion barrier may be formed of SiC. On the other hand, the insulating film may be formed by depositing a PETEOS film after applying a low-k dielectric material on the entire upper portion by a spin coating method.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 한편, 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.2A through 2E are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 소정의 공정을 통해 반도체 소자를 형성하기 위하여 트랜지스터나 플래시 메모리 셀과 같은 여러 요소(도시되지 않음)가 형성된 반도체 기판(201) 상에 층간 절연막(202)을 형성한다.Referring to FIG. 2A, an interlayer insulating layer 202 is formed on a semiconductor substrate 201 in which various elements (not shown), such as a transistor or a flash memory cell, are formed to form a semiconductor device through a predetermined process.
이어서, 상부에 형성될 금속 배선이나 금속 시드층의 금속 성분이 층간 절연막(202)으로 침투하지 못하도록 층간 절연막(202) 상부에 장벽 금속층(203)을 형성한 후, 금속 시드층(204)을 순차적으로 형성한다. 이때, 장벽 금속층(203)은 Ta 또는 TaN으로 형성할 수 있으며, 평탄화된 상태에서 형성되므로 50 내지 100Å의 얇은 두께로 형성할 수 있다. 이러한, 장벽 금속층(203)은 스퍼터(Sputter) 방식으로 형성할 수 있다. 한편, 금속 시드층(204)은 100 내지 200Å의 두께로 형성한다.Subsequently, the barrier metal layer 203 is formed on the interlayer insulating film 202 so that the metal component of the metal wiring or metal seed layer to be formed thereon does not penetrate into the interlayer insulating film 202, and then the metal seed layer 204 is sequentially formed. To form. In this case, the barrier metal layer 203 may be formed of Ta or TaN, and may be formed in a thin thickness of 50 to 100 μm because it is formed in a planarized state. The barrier metal layer 203 may be formed by a sputter method. On the other hand, the metal seed layer 204 is formed to a thickness of 100 ~ 200Å.
계속해서, 금속 시드층(204) 상부에는 금속 배선이 형성될 영역이 정의된 포토레지스트 패턴(205)을 형성하여 금속 배선이 형성될 영역의 금속 시드층(204)만을 노출시킨다.Subsequently, a photoresist pattern 205 defining a region in which the metal wiring is to be defined is formed on the metal seed layer 204 to expose only the metal seed layer 204 in the region in which the metal wiring is to be formed.
도 2b를 참조하면, 전기 도금법으로 금속 물질을 도금하여 포토레지스트 패턴(204) 사이의 공간을 금속 도금층(206)으로 매립한다. 이때, 금속 도금층(206)은 하부의 금속 시드층(204)으로부터 전해액(Electrolyte)의 촉진(Accelerator) 현상에 의해 상부 방향으로 형성된다. 한편, 금속 도금층(206)은 후속 공정으로 포토레지스트 패턴(205) 하부의 금속 시드층(204)을 식각하는 과정에서 같이 식각되므로, 이를 고려하여 포토레지스트 패턴(205)의 높이보다 높게 형성한다. 예를 들면, 금속 시드층(204)의 두께만큼 포토레지스트 패턴(205)의 높이보다 높게 금속 도금층(206)을 형성한다.Referring to FIG. 2B, the metal material is plated by electroplating to fill the space between the photoresist patterns 204 with the metal plating layer 206. In this case, the metal plating layer 206 is formed in the upper direction by the accelerator phenomenon of the electrolytic solution from the lower metal seed layer 204. Meanwhile, since the metal plating layer 206 is etched in the subsequent process of etching the metal seed layer 204 under the photoresist pattern 205, the metal plating layer 206 is formed higher than the height of the photoresist pattern 205. For example, the metal plating layer 206 is formed higher than the height of the photoresist pattern 205 by the thickness of the metal seed layer 204.
도 2c를 참조하면, 포토레지스트 패턴(도 2b의 204)을 제거한다. 이어서, 포토레지스트 패턴이 제거되면서 노출된 금속 시드층(204)을 제거하고, 계속해서 하부의 장벽 금속층(203)을 제거하여 금속 배선(206)을 전기적으로 격리시킨다. 이때, 포토레지스트 패턴은 산소 플라즈마 처리로 제거한다. 그리고, 금속 시드층(204) 및 장벽 금속층(203)은 Cl2가스를 이용하여 식각한다. 금속 시드층(204)이 식각되면서 금속 배선(206)의 과도 도금된 상부도 식각되지만, 금속 시드층(204)의 식각량이 적기 때문에 금속 배선(206)의 전기적 특성에는 거의 영향을 주지 않는다. 한편, 금속 시드층(204) 식각 시 부산물(By-product)의 증기 압력(Vapor pressure)이 낮으면 금속 식각이 어려워지므로, 금속 시드층(204)을 쉽게 식각하기 위하여 200 내지 1000℃의 고온에서 식각 공정을 실시한다.Referring to FIG. 2C, the photoresist pattern 204 of FIG. 2B is removed. The metal seed layer 204 is then removed while the photoresist pattern is removed, and the underlying barrier metal layer 203 is subsequently removed to electrically isolate the metal interconnect 206. At this time, the photoresist pattern is removed by oxygen plasma treatment. The metal seed layer 204 and the barrier metal layer 203 are etched using Cl 2 gas. While the metal seed layer 204 is etched, the over-plated upper portion of the metal wiring 206 is also etched. However, since the etching amount of the metal seed layer 204 is small, it hardly affects the electrical characteristics of the metal wiring 206. On the other hand, if the vapor pressure of the by-product (By-product) during the etching of the metal seed layer 204 is difficult metal etching, in order to easily etch the metal seed layer 204 at a high temperature of 200 to 1000 ℃ Carry out an etching process.
도 2d를 참조하면, 금속 배선(206) 상부에 형성될 금속 배선과의 전기적인 절연을 위하여 금속 배선(206)을 포함한 전체 상부에 절연막을 형성한다. 절연막을 형성하는 방법에 대해서 좀 더 구체적으로 설명하면 다음과 같다. 먼저, 금속 배선(206)을 포함한 전체 상부 표면에 확산 방지막(207)을 형성한다. 이때, 확산 방지막(207)은 SiC로 형성할 수 있다. 이어서, 전체 상부에 저유전 물질(Low-k material; 208)을 스핀 코팅 방식으로 도포한 후, PETEOS막(209)을 순차적으로 형성한다. 이로써, 금속 배선(206) 상부에 절연막이 형성된다.Referring to FIG. 2D, an insulating film is formed over the entirety of the metal wire 206 including the metal wire 206 to electrically insulate the metal wire from the metal wire 206. A method of forming the insulating film will be described in more detail as follows. First, the diffusion barrier film 207 is formed on the entire upper surface including the metal wiring 206. At this time, the diffusion barrier 207 may be formed of SiC. Subsequently, after applying a low-k material 208 on the whole by spin coating, the PETEOS film 209 is sequentially formed. As a result, an insulating film is formed over the metal wiring 206.
상술한 바와 같이, 본 발명은 화학적 기계적 연마 공정을 생략하면서 금속 배선을 형성하여 화학적 기계적 연마 공정에 의해 디싱(Dishing) 현상이나침식(Erosion) 현상이 발생되는 것을 방지하고 공정의 신뢰성을 향상시킬 수 있다.As described above, the present invention can form a metal wiring while omitting the chemical mechanical polishing process to prevent dishing or erosion caused by the chemical mechanical polishing process and improve the reliability of the process. have.
또한, 그에 따라 저유전(Low-k) 절연막의 두께를 일정하게 유지하여 일정한 커패시턴스(Capacitance) 값을 얻을 수 있고, RC 지연(RC Delay)에 따라 소자의 동작 속도가 저하되는 문제점을 해결하여 소자의 전기적 특성을 향상시킬 수 있다.In addition, a constant capacitance value can be obtained by keeping the thickness of the low-k insulating film constant, and the device's operation speed decreases due to the RC delay. It can improve the electrical characteristics.
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| US9564398B2 (en) * | 2013-03-12 | 2017-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chemical direct pattern plating interconnect metallization and metal structure produced by the same |
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