KR100476037B1 - Method for forming Cu wiring of semiconductor device - Google Patents
Method for forming Cu wiring of semiconductor device Download PDFInfo
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- KR100476037B1 KR100476037B1 KR10-2002-0078661A KR20020078661A KR100476037B1 KR 100476037 B1 KR100476037 B1 KR 100476037B1 KR 20020078661 A KR20020078661 A KR 20020078661A KR 100476037 B1 KR100476037 B1 KR 100476037B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
본 발명은 구리배선 형성방법을 개시한다. 개시된 본 발명의 방법은, 제1층간절연막이 형성된 반도체 기판을 제공하는 단계와, 상기 제1층간절연막을 식각하여 수 개의 비아홀을 형성하는 단계와, 상기 비아홀을 매립하도록 제1층간절연막 상에 텅스텐막을 증착하는 단계와, 상기 텅스텐막을 CMP하여 텅스텐 플러그를 형성하는 단계와, 상기 텅스텐막의 CMP(Chemical Mechanical Polishing)시 국부적으로 패턴 밀도가 높은 지역에서 단차가 발생되어진 기판 결과물 상에 제2층간절연막을 증착하는 단계와, 상기 제2층간절연막 상에 소정 두께로 PETEOS막으로 이루어진 희생산화막을 증착하는 단계와, 상기 희생산화막의 소정 두께만큼을 CMP하여 평탄화시키는 단계와, 상기 희생산화막 및 제2층간절연막을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 매립하도록 희생산화막 상에 구리막을 증착하는 단계와, 상기 희생산화막이 노출되도록 상기 구리막을 CMP하는 단계를 포함한다. 본 발명에 따르면, 층간절연막의 증착 후에 희생산화막을 추가 증착하여 단차를 제거하고, 이러한 상태로 비아 식각 및 구리막의 증착을 포함하는 후속 공정들을 진행함으로써 구리 잔류물의 발생을 용이하게 방지할 수 있으며, 이에 따라, 소자 신뢰성을 확보할 수 있다. The present invention discloses a copper wiring forming method. The disclosed method includes providing a semiconductor substrate having a first interlayer insulating film, etching the first interlayer insulating film to form several via holes, and filling a tungsten on the first interlayer insulating film to fill the via holes. Depositing a film, forming a tungsten plug by CMP of the tungsten film, and forming a second interlayer insulating film on a substrate resultant in which a step is generated in a region having a high pattern density during CMP (Chemical Mechanical Polishing) of the tungsten film. Depositing, depositing a sacrificial oxide film made of a PETEOS film with a predetermined thickness on the second interlayer insulating film, CMP to planarize by a predetermined thickness of the sacrificial oxide film, and the sacrificial oxide film and the second interlayer insulating film. Etching to form a trench, and depositing a copper film on the sacrificial oxide layer to fill the trench And CMP the copper film to expose the sacrificial oxide film. According to the present invention, after the deposition of the interlayer insulating film, the sacrificial oxide film is further deposited to remove the step, and in this state, the subsequent processes including the etching of the via and the deposition of the copper film can be easily prevented from generating copper residues. As a result, device reliability can be ensured.
Description
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 특히, 구리배선 형성시의 구리 잔류물의 발생을 방지하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper wiring in a semiconductor device, and more particularly, to a method for preventing generation of copper residues during copper wiring formation.
CMP(Chemical Mechanical Polishing) 공정은 슬러리(slurry)에 의한 화학 반응과 연마 패드(polishing pad)에 의한 기계적 가공이 동시에 수행되는 평탄화 공정으로서, 평탄화를 위해 기존에 이용되어져 왔던 리플로우(reflow) 공정 또는 에치-백(etch-back) 공정 등과 비교해서 글로벌(global) 평탄화를 얻을 수 있고, 아울러, 저온에서 수행될 수 있다는 잇점이 있다. CMP (Chemical Mechanical Polishing) process is a planarization process in which chemical reaction by slurry and mechanical processing by polishing pad are performed at the same time. The reflow process that has been conventionally used for planarization or Compared to an etch-back process and the like, global planarization can be obtained and, in addition, it can be performed at low temperatures.
이러한 CMP 공정은 평탄화 공정의 일환으로 제안된 것이지만, 최근에 들어서는 콘택플러그 형성을 위한 폴리실리콘막의 식각 및 금속 배선 형성을 위한 금속막의 식각 공정에 이용되고 있으며, 그 이용 분야가 점차 확대되고 있는 추세이다.The CMP process has been proposed as part of the planarization process, but recently, the CMP process has been used for the etching of polysilicon films for forming contact plugs and the etching of metal films for forming metal wirings. .
한편, 상기 CMP 공정을 이용하여 금속배선, 예컨데, 구리배선을 형성함에 있어서 구리막을 CMP한 후에 가장 신경을 써야 하는 사항들중의 하나는 구리 잔류물(residue)이다. 이것은 구리 잔류물이 소자에 치명적인 이물질로 작용하기 때문이다. On the other hand, one of the things to pay attention to after the CMP of the copper film in forming the metal wiring, for example, copper wiring using the CMP process is the copper residue (residue). This is because the copper residue acts as a lethal foreign material to the device.
여기서, 상기 구리 잔류물은 금속배선의 패턴 밀도(pattern density), 크기, 토폴로지(topology) 및 하지층(under layer) 등에 영향을 받으며, 이 중에서도 하지층에 가장 큰 영향을 받는다. 여기서, 제1층 구리배선의 경우, 텅스텐막을 CMP한 층이 하지층이 되며, 제2층 구리배선부터는 구리배선을 CMP한 층이 하지층이 된다.Here, the copper residue is influenced by the pattern density, size, topology and under layer of the metallization, among which is most affected by the underlayer. In this case, in the case of the first layer copper wiring, the tungsten film CMP layer becomes the underlayer, and from the second layer copper wiring, the layer CMP the copper wiring becomes the underlayer.
예컨데, 텅스텐 플러그를 형성하기 위한 텅스텐막의 CMP 후에는, 도 1에 도시된 바와 같이, 표면 평탄화가 이루어져야 한다. For example, after the CMP of the tungsten film for forming the tungsten plug, surface planarization should be made as shown in FIG.
그러나, 실제로는 CMP 공정의 특성상 이로젼(erosion)이나 디싱(dishing)의 발생을 피할 수 없으며, 이에 따라, 텅스텐막의 CMP 후에는, 도 2a에 도시된 바와 같이, 부분적으로 디싱, 즉, 단차(A1)가 발생된 표면을 얻게 된다.However, in practice, erosion or dishing cannot be avoided due to the characteristics of the CMP process. Accordingly, after the CMP of the tungsten film, as shown in FIG. 2A, partly dishing, that is, a step ( The surface on which A1) is generated is obtained.
이 경우, 도 2b에 도시된 바와 같이, 단차가 발생된 기판 결과물 상에 제2층간절연막(4)을 증착하면, 그 표면 또한 단차(A2)를 갖게 되고, 이어서, 도 2c에 도시된 바와 같이, 제2층간절연막(4)에 트렌치를 형성한 후에 구리막(5)을 증착하면, 그 또한 단차(A3)를 가짐으로써, 결국, 이렇게 단차(A3)를 갖는 구리막(5)을 CMP함에 따라, 도 2d에 도시된 바와 같이, 트렌치 내에는 최종적으로 구리배선(5a)이 형성되지만, 이와 더불어 제2층간절연막(4)의 단차에 구리 잔류물(6)이 남게 됨은 물론 이러한 구리 잔류물이 인접하는 구리배선들과간의 브릿지(bridge)를 유발하게 된다. In this case, as shown in FIG. 2B, when the second interlayer insulating film 4 is deposited on the substrate resultant in which the step is generated, the surface also has a step A2, and then as shown in FIG. 2C. When the copper film 5 is deposited after the trench is formed in the second interlayer insulating film 4, the copper film 5 also has a step A3. As a result, the copper film 5 having the step A3 is thus subjected to CMP. Accordingly, as shown in FIG. 2D, the copper wiring 5a is finally formed in the trench, but the copper residue 6 remains at the step of the second interlayer insulating film 4 as well as the copper residue. This will cause a bridge between these adjacent copper wires.
결국, 종래의 CMP 공정을 이용한 구리배선 형성방법에서는 필연적으로 구리 잔류물이 발생되므로, 이러한 구리 잔류물에 의해 제품 신뢰성을 확보할 수 없다. As a result, copper residues are inevitably generated in the conventional method of forming copper wirings using the CMP process, and thus, product reliability cannot be secured by such copper residues.
도 1 및 도 2a 내지 도 2d에서, 미설명된 도면부호 1은 소정의 도전패턴을 포함한 반도체 기판, 2는 제1층간절연막, 3은 텅스텐 플러그를 각각 나타낸다.1 and 2A to 2D, reference numeral 1 denotes a semiconductor substrate including a predetermined conductive pattern, 2 denotes a first interlayer insulating film, and 3 denotes a tungsten plug.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 하지층의 단차로 인해 유발되는 구리 잔류물의 발생을 방지할 수 있는 구리배선 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a copper wiring that can prevent the occurrence of copper residues caused by the step of the underlying layer as devised to solve the above problems.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 제1층간절연막이 형성된 반도체 기판을 제공하는 단계; 상기 제1층간절연막을 식각하여 수 개의 비아홀을 형성하는 단계; 상기 비아홀을 매립하도록 제1층간절연막 상에 텅스텐막을 증착하는 단계; 상기 텅스텐막을 CMP하여 텅스텐 플러그를 형성하는 단계; 상기 텅스텐막의 CMP시 국부적으로 패턴 밀도가 높은 지역에서 단차가 발생되어진 기판 결과물 상에 제2층간절연막을 증착하는 단계; 상기 제2층간절연막 상에 소정 두께로 PETEOS막으로 이루어진 희생산화막을 증착하는 단계; 상기 희생산화막의 소정 두께만큼을 CMP하여 평탄화시키는 단계; 상기 희생산화막 및 제2층간절연막을 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 희생산화막 상에 구리막을 증착하는 단계; 및 상기 희생산화막이 노출되도록 상기 구리막을 CMP하는 단계를 포함하는 반도체 소자의 구리배선 형성방법을 제공한다. In order to achieve the above object, the present invention comprises the steps of providing a semiconductor substrate formed with a first interlayer insulating film; Etching the first interlayer insulating film to form several via holes; Depositing a tungsten film on a first interlayer insulating film to fill the via hole; CMP the tungsten film to form a tungsten plug; Depositing a second interlayer insulating film on a substrate resultant in which a step is generated in a region having a high pattern density during CMP of the tungsten film; Depositing a sacrificial oxide film made of a PETEOS film on the second interlayer insulating film to a predetermined thickness; CMP planarization by a predetermined thickness of the sacrificial oxide film; Etching the sacrificial oxide layer and the second interlayer dielectric layer to form a trench; Depositing a copper film on the sacrificial oxide film so as to fill the trench; And CMPing the copper film to expose the sacrificial oxide film.
여기서, 상기 희생산화막은 PETEOS막이며, 1000∼3000Å 두께로 증착한다. Herein, the sacrificial oxide film is a PETEOS film and is deposited at a thickness of 1000 to 3000 GPa.
상기 희생산화막의 CMP는 그 증착 두께가 2000Å인 경우에 1000∼1500Å의 두께만큼을 CMP하며, 그리고, 평탄화가 잘 이루어질 수 있도록 단단한 연마패드를 사용하면서 연마압력을 3psi 미만, 그리고, 연마판의 회전속도를 50rpm 이상으로 하는 조건으로 수행한다. The CMP of the sacrificial oxide film has a CMP of 1000 to 1500 kPa when its deposition thickness is 2000 kPa, and the polishing pressure is less than 3 psi while using a hard polishing pad for flattening, and the polishing plate rotates. It is carried out under the condition that the speed is 50rpm or more.
본 발명에 따르면, 제2층간절연막의 증착 후에 희생산화막을 추가 증착하여 단차를 제거한 상태로 후속 공정을 진행함으로써 구리 잔류물의 발생을 용이하게 방지할 수 있다. According to the present invention, after the deposition of the second interlayer insulating film, the sacrificial oxide film is additionally deposited to proceed with a subsequent process with the step removed to prevent the generation of copper residues.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명의 실시예에 따른 구리배선 형성방법을 설명하기 위한 공정별 단면도이다.3A to 3E are cross-sectional views of processes for describing a method of forming a copper wiring according to an embodiment of the present invention.
도 3a를 참조하면, 공지의 반도체 제조 공정에 따라 소정의 도전 패턴들을 포함하는 하지층(도시안됨)이 형성된 반도체 기판(31) 상에 제1층간절연막(32)을 증착한다. 그런다음, 상기 제1층간절연막(32)의 소정 부분들을 비아 식각하여 기판 또는 도전 패턴을 노출시키는 비아홀들을 형성한 후, 이 비아홀들을 매립하도록 텅스텐막을 증착하고, 이를 CMP하여 텅스텐 플러그들(33)을 형성한다. Referring to FIG. 3A, a first interlayer insulating film 32 is deposited on a semiconductor substrate 31 on which an underlayer (not shown) including predetermined conductive patterns is formed according to a known semiconductor manufacturing process. Thereafter, via portions of the first interlayer dielectric layer 32 are etched to form via holes for exposing the substrate or the conductive pattern. Then, a tungsten film is deposited to fill the via holes, and CMP is used to deposit the tungsten plugs 33. To form.
이때, CMP 공정의 특성상 부식 또는 디싱이 발생되며, 이로 인해, 패턴 밀도가 높은 지역에서 국부적으로 단차(B1)가 발생된다. At this time, corrosion or dishing occurs due to the characteristics of the CMP process, and thus, a step B1 is locally generated in a region having a high pattern density.
도 3b를 참조하면, 상기 기판 결과물 상에 단차가 발생된 상태 그대로 저유전(Low-k) 물질로 이루어진 제2층간절연막(34)을 증착한다. 이때, 상기 제2층간절연막(34) 또한 그 표면에 국부적으로 단차(B2)가 발생된다. 이어서, 상기 제2층간절연막(34) 상에 PETEOS막 등으로 이루어진 희생산화막(35)을 1000∼3000Å의 두께로 증착한다. 상기 PETEOS막으로 이루어진 희생산화막(35)은 구리막 증착 이전에 국부적으로 발생된 단차를 제거해주기 위해 추가 증착하는 산화막이며, 그 또한 표면에 단차(B3)가 발생된다. Referring to FIG. 3B, a second interlayer insulating layer 34 made of a low-k material is deposited on the substrate resultant as a step is generated. At this time, the second interlayer insulating film 34 also has a step B2 locally generated on its surface. Subsequently, a sacrificial oxide film 35 made of a PETEOS film or the like is deposited on the second interlayer insulating film 34 to a thickness of 1000 to 3000 GPa. The sacrificial oxide film 35 made of the PETEOS film is an oxide film additionally deposited to remove a step generated locally before the copper film is deposited, and a step B3 is also generated on the surface thereof.
도 3c를 참조하면, 희생산화막의 표면을 CMP하고, 이를 통해, 희생산화막에 국부적으로 발생되었던 단차를 제거한다. 도면부호 35a는 잔류된 희생산화막을 나타낸다. Referring to FIG. 3C, the surface of the sacrificial oxide film is CMP, thereby removing a step that is locally generated in the sacrificial oxide film. Reference numeral 35a denotes a remaining sacrificial oxide film.
여기서, CMP하는 희생산화막의 두께는 그 증착 두께에 따라 상이하겠지만, 2000Å의 두께로 희생산화막을 증착한 경우, 1000∼1500Å 정도의 두께를 CMP하면 평탄화를 얻을 수 있을 것으로 예상된다. 또한, 상기 희생산화막을 CMP함에 있어서는 평탄화 특성이 우수한 조건으로 수행함이 바람직하며, 예컨데, 매우 단단한 연마패드를 사용하면서 연마압력을 3psi 미만, 그리고, 연마판의 회전속도를 50rpm 이상으로 하는 조건으로 수행하여 국부 평탄화가 빠르고 효과적으로 이루어지도록 한다. Here, the thickness of the sacrificial oxide film subjected to CMP will vary depending on the deposition thickness. However, when the sacrificial oxide film is deposited at a thickness of 2000 GPa, it is expected that planarization can be obtained by CMP of about 1000 to 1500 GPa. In addition, in the CMP of the sacrificial oxide film, the planarization property is preferably performed under excellent conditions. For example, while using a very hard polishing pad, the polishing pressure is less than 3 psi, and the polishing rate is 50 rpm or more. So that localized flattening can be done quickly and effectively.
도 3d를 참조하면, 잔류된 희생산화막(35a) 및 제2층간절연막을 식각하여 구리배선이 형성될 영역을 한정하는 트렌치들을 형성한다. 그런다음, 상기 트렌치들을 매립하도록 잔류된 희생산화막(35a) 상에 구리막(35)을 증착한다. Referring to FIG. 3D, the remaining sacrificial oxide film 35a and the second interlayer insulating film are etched to form trenches defining regions in which copper wirings are to be formed. Then, a copper film 35 is deposited on the remaining sacrificial oxide film 35a to fill the trenches.
도 3e를 참조하면, 잔류된 희생산화막(35a)이 노출될 때까지 상기 구리막을 CMP하고, 이 결과로서 본 발명에 따른 구리배선(36a)을 형성한다. Referring to FIG. 3E, the copper film is CMP until the remaining sacrificial oxide film 35a is exposed, thereby forming a copper wiring 36a according to the present invention.
여기서, 구리막의 증착 전, 희생산화막의 증착 및 CMP를 통해 하지층에 존재하였던 국부적인 단차를 제거하였으므로, 상기 구리막의 CMP 후, 구리 잔류물의 발생은 일어나지 않으며, 그래서, 인접하는 구리배선들(36a)간의 브릿지 유발되지 않는 바, 소자 신뢰성을 확보할 수 있게 된다. Here, before the deposition of the copper film, the local step existing in the underlying layer was removed through the deposition of the sacrificial oxide film and the CMP, so that after the CMP of the copper film, no generation of copper residues occurred, and thus, adjacent copper wirings 36a. Since no bridge is induced between the elements, device reliability can be ensured.
이상에서와 같이, 본 발명은 단차가 발생된 하지층 상에 희생산화막의 증착 및 이에 대한 CMP를 추가하여 상기 단차를 제거함과 동시에 표면 평탄화를 이룸으로써, 후속하는 구리막의 CMP 후에 구리 잔류물의 발생을 방지할 수 있다. 여기서, 단차가 발생된 하지층은 본 발명에서 제시하는 텅스텐 CMP가 진행된 층일 수도 있고, 구리배선 CMP가 진행된 층일 수도 있다. As described above, the present invention removes the step by depositing the sacrificial oxide film and adding CMP thereto on the underlayer on which the step is generated, thereby achieving a surface planarization, thereby preventing the generation of copper residues after the CMP of the subsequent copper film. You can prevent it. Here, the base layer in which the step is generated may be a layer in which tungsten CMP is advanced according to the present invention or a layer in which copper wiring CMP is advanced.
따라서, 본 발명은 구리 잔류물의 발생을 방지할 수 있으므로, 구리배선 자체의 신뢰성 및 제조수율은 물론 소자의 신뢰성 또한 확보할 수 있다. Therefore, the present invention can prevent the generation of copper residues, thereby ensuring the reliability and manufacturing yield of the copper wiring itself as well as the reliability of the device.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
도 1은 텅스텐 CMP(Chemical Mechanical Polishing) 후의 이상적인 기판을 도시한 단면도. 1 is a cross-sectional view illustrating an ideal substrate after tungsten chemical mechanical polishing (CMP).
도 2a 내지 도 2d는 종래의 문제점을 설명하기 위한 단면도. 2A to 2D are cross-sectional views illustrating a conventional problem.
도 3a 내지 도 3e는 본 발명의 실시예에 따른 구리배선 형성방법을 설명하기 위한 공정별 단면도.Figure 3a to Figure 3e is a cross-sectional view for each process for explaining a copper wiring forming method according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
31 : 반도체 기판 32 : 제1층간절연막31 semiconductor substrate 32 first interlayer insulating film
33 : 텅스텐 플러그 34 : 제2층간절연막33 tungsten plug 34 second interlayer insulating film
35 : 희생산화막 35a : 잔류된 희생산화막35: sacrificial oxide film 35a: remaining sacrificial oxide film
36 : 구리막 36a : 구리배선36: copper film 36a: copper wiring
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100772252B1 (en) | 2006-07-12 | 2007-11-01 | 동부일렉트로닉스 주식회사 | Method for manufacturing the copper line |
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| JPH11165253A (en) * | 1997-12-03 | 1999-06-22 | Matsushita Electric Ind Co Ltd | Abrasive slurry, polishing device for substrate and polishing method of substrate |
| KR19990055200A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming inlaid metal wiring |
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| KR100772252B1 (en) | 2006-07-12 | 2007-11-01 | 동부일렉트로닉스 주식회사 | Method for manufacturing the copper line |
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