KR100680968B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR100680968B1
KR100680968B1 KR1020050067869A KR20050067869A KR100680968B1 KR 100680968 B1 KR100680968 B1 KR 100680968B1 KR 1020050067869 A KR1020050067869 A KR 1020050067869A KR 20050067869 A KR20050067869 A KR 20050067869A KR 100680968 B1 KR100680968 B1 KR 100680968B1
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contact hole
interlayer insulating
plug
contact
forming
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KR1020050067869A
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Korean (ko)
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KR20070013507A (en
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유영호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, 하부구조물을 구비한 반도체기판 상에 층간절연막을 형성하는 단계와, 상기 하부구조물이 노출되도록 층간절연막을 식각하여 상단부가 항아리 모양을 갖는 콘택홀을 형성하는 단계와, 상기 콘택홀 내에 감광막으로 이루어진 희생플러그를 매립하는 단계와, 상기 희생플러그 상부를 포함한 층간절연막의 표면 일부 두께를 제거하여 콘택홀 상부의 너비를 넓혀주는 단계와, 상기 희생플러그를 제거하는 단계와, 상기 상부의 너비가 확장된 콘택홀 내에 도전막을 매립하여 콘택플러그를 형성하는 단계와, 상기 층간절연막 상에 콘택플러그와 콘택되는 금속배선을 형성하는 단계를 포함한다. 본 발명에 따르면, 반도체 소자의 금속배선을 형성함에 있어서, 상단부가 항아리 모양을 갖는 콘택홀의 상부 일부를 CMP 또는 에치백 방식으로 제거하여 콘택홀 상부의 너비를 넓혀줌으로써, 콘택홀 내에 콘택플러그 매립시 매립 특성을 개선할 수 있다. The present invention discloses a method for manufacturing a semiconductor device. The disclosed method includes forming an interlayer insulating film on a semiconductor substrate having a lower structure, etching the interlayer insulating film to expose the lower structure, and forming a contact hole having an upper end in a jar shape; Embedding a sacrificial plug made of a photoresist film in the contact hole; Forming a contact plug by filling a conductive film in a contact hole having an upper width, and forming a metal wiring contacting the contact plug on the interlayer insulating layer. According to the present invention, in forming the metal wiring of the semiconductor device, the upper portion of the upper portion of the contact hole having a jar shape by removing the CMP or etch back method to increase the width of the upper contact hole, when filling the contact plug in the contact hole Landfill characteristics can be improved.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래 기술의 문제점을 설명하기 위한 반도체 소자의 단면도. 1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체기판 22 : 하부구조물21: semiconductor substrate 22: substructure

23 : 층간절연막 24 : 콘택홀23: interlayer insulating film 24: contact hole

25 : 희생플러그 26 : 콘택플러그25: sacrificial plug 26: contact plug

27 : 금속배선27 metal wiring

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 금속배선용 콘택홀의 매립 특성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the embedding characteristics of a contact hole for metal wiring.

주지된 바와 같이, 금속배선의 재료로서는 전기 전도도가 매우 우수한 알루미늄(Al)이 주로 이용되어 왔다. 그런데, 반도체 소자의 집적도 향상에 기인해서 전기적 연결 통로를 제공하는 콘택홀의 너비는 감소하고, 아울러, 콘택홀의 깊이는 깊어짐에 따라, 알루미늄으로는 미세 크기의 콘택홀을 완전 매립시키는 것이 어렵게 되었다. As is well known, aluminum (Al) having excellent electrical conductivity has been mainly used as a material for metal wiring. However, due to the increase in the degree of integration of semiconductor devices, the width of the contact hole providing the electrical connection passage is reduced, and the depth of the contact hole is deepened, making it difficult to completely fill the contact hole having a fine size with aluminum.

따라서, 이러한 콘택홀 매립의 문제를 해결하기 위해, 알루미늄 보다 매립 특성이 우수한 금속막, 예컨데, 텅스텐막으로 콘택홀을 완전 매립시켜, 이것을 금속배선과 하부구조물간의 전기적 연결을 위한 콘택플러그로 이용하는 기술이 제안되었다. Therefore, in order to solve the problem of contact hole embedding, the contact hole is completely filled with a metal film, for example, a tungsten film, which has better embedding properties than aluminum, and uses this as a contact plug for electrical connection between the metal wiring and the substructure. This has been proposed.

자세하게, 종래의 금속배선 공정을 살펴보면, 먼저, 층간절연막의 식각을 통해 하부구조물을 노출시키는 콘택홀을 형성한 상태에서, 상기 콘택홀을 매립시키도록 텅스텐막을 증착하고, 이어, 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정으로 상기 텅스텐막을 연마하여 콘택홀 내에 텅스텐 플러그를 형성한다. 그런다음, 금속막의 증착 및 패터닝을 통해 상기 텅스텐 플러그와 콘택되게 알루미늄 배선을 형성한다. In detail, in the conventional metallization process, first, a tungsten film is deposited to fill a contact hole in a state in which a contact hole for exposing a lower structure is formed through etching of an interlayer insulating film, and then chemical mechanical polishing (Chemical) is performed. Mechanical Polishing: Hereinafter, the tungsten film is polished by a CMP process to form a tungsten plug in the contact hole. Then, an aluminum wiring is formed in contact with the tungsten plug through the deposition and patterning of the metal film.

그러나, 반도체 소자의 고집적화로 콘택홀 크기가 더욱 감소됨에 따라, 콘택홀을 매립하기 위해 매립 특성이 우수한 텅스텐을 사용하더라도 콘택홀을 완전 매립하기가 어려워지게 되었다. However, as the contact hole size is further reduced due to high integration of semiconductor devices, even when tungsten having excellent embedding characteristics is used to fill the contact hole, it is difficult to completely fill the contact hole.

자세하게, 도 1은 상기한 종래 기술의 문제점을 설명하기 위한 반도체 소자의 단면도로서, 이를 설명하면 다음과 같다. In detail, Figure 1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art described above, as follows.

도 1을 참조하면, 하부구조물(12)을 구비한 반도체기판(11) 상에 층간절연막 (13)을 형성하고, 상기 하부구조물(12)이 노출되도록 층간절연막(13)을 식각하여 콘택홀(14)을 형성하고 나서, 상기 콘택홀(14) 내에 텅스텐을 매립하여 콘택플러그(15)를 형성한 후, 상기 콘택플러그(15)와 콘택되는 금속배선(16)을 형성시킨다.Referring to FIG. 1, an interlayer insulating layer 13 is formed on a semiconductor substrate 11 having a lower structure 12, and the interlayer insulating layer 13 is etched to expose the lower structure 12. After forming 14, tungsten is embedded in the contact hole 14 to form the contact plug 15, and then the metal wiring 16 contacting the contact plug 15 is formed.

그런데, 고집적화로 인해 콘택홀(14)의 크기가 감소됨에 따라, 도시된 바와 같이, 콘택홀(14) 형성시 콘택홀(14) 상부의 모양이 항아리와 같은 형태를 갖게 되므로, 콘택홀(14) 상부의 너비가 더욱 감소되어, 콘택플러그(15) 형성을 위한 텅스텐 매립시 콘택홀(14)의 입구부에서 병목현상이 발생한다. 이로 인해, 알루미늄 보다 매립 특성이 우수한 텅스텐을 사용하더라도 콘택홀(14) 매립이 어려워지게 되고, 도면의 A표시영역과 B표시영역과 같은 불량이 발생한다. However, as the size of the contact hole 14 is reduced due to high integration, as shown in the figure, the upper portion of the contact hole 14 when forming the contact hole 14 has a shape like a jar, and thus, the contact hole 14 The width of the upper part is further reduced, and bottlenecks occur at the inlet of the contact hole 14 when the tungsten is embedded to form the contact plug 15. As a result, even when tungsten having better embedding characteristics is used than aluminum, embedding of the contact hole 14 becomes difficult, and defects such as A display area and B display area in the drawing occur.

결과적으로, 종래에는 상기와 같은 불량 발생으로 금속배선의 신뢰성 확보가 어려워지고, 제품의 특성 및 수율이 저하되는 문제가 있다. As a result, there is a problem in that it is difficult to secure the reliability of the metal wiring due to the above-described failure, and the characteristics and yield of the product are lowered.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출된 것으로서, 금속배선용 콘택홀의 매립 특성을 향상시켜 금속배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the reliability of metal wiring by improving the buried characteristics of the metal contact holes.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법, 하부구조물을 구비한 반도체기판 상에 층간절연막을 형성하는 단계; 상기 하부구조물이 노출되도록 층간절연막을 식각하여 상단부가 항아리 모양을 갖는 콘택홀을 형성하는 단계; 상기 콘택홀 내에 감광막으로 이루어진 희생플러그를 매립하는 단계; 상기 희생플러그 상부를 포함한 층간절연막의 표면 일부 두께를 제거하여 콘택홀 상부의 너비를 넓혀주는 단계; 상기 희생플러그를 제거하는 단계; 상기 상부의 너비가 확장된 콘택홀 내에 도전막을 매립하여 콘택플러그를 형성하는 단계; 및 상기 층간절연막 상에 콘택플러그와 콘택되는 금속배선을 형성하는 단계;를 포함한다. A method of manufacturing a semiconductor device of the present invention for achieving the above object, the step of forming an interlayer insulating film on a semiconductor substrate having a lower structure; Etching the interlayer insulating layer to expose the lower structure to form a contact hole having an upper end in a jar shape; Embedding a sacrificial plug made of a photosensitive film in the contact hole; Widening the width of the upper portion of the contact hole by removing a portion of the surface of the interlayer insulating layer including the upper portion of the sacrificial plug; Removing the sacrificial plug; Forming a contact plug by burying a conductive film in the contact hole having an upper width; And forming a metal wiring contacting the contact plug on the interlayer insulating layer.

여기서, 상기 콘택플러그는 텅스텐으로 형성한다. Here, the contact plug is formed of tungsten.

한편, 상기 희생플러그 상부를 포함한 층간절연막의 표면 일부 두께를 제거하는 단계는 CMP 또는 에치백 방식으로 수행한다. On the other hand, removing the thickness of the portion of the surface of the interlayer insulating film including the upper portion of the sacrificial plug is performed by a CMP or etch back method.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 2A through 2D are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 비트라인과 같은 하부구조물(22)이 구비된 반도체기판(21)을 마련한다. 그런다음, 상기 기판(21) 전면 상에 층간절연막(23)을 형성한다. 이어서, 상기 하부구조물(22)이 노출되도록 층간절연막(23)을 식각하여 금속배선용 콘택홀(24)을 형성한다. Referring to FIG. 2A, a semiconductor substrate 21 having a lower structure 22 such as a bit line is provided. Then, an interlayer insulating film 23 is formed on the entire surface of the substrate 21. Subsequently, the interlayer insulating layer 23 is etched to expose the lower structure 22 to form a contact hole 24 for metal wiring.

이때, 상기 콘택홀(24)은, 도시된 바와 같이, 그 상단부가 항아리 모양을 갖도록 형성된다. At this time, the contact hole 24, as shown, the upper end is formed to have a jar shape.

도 2b를 참조하면, 상기 콘택홀(24)을 매립하도록 콘택홀(24)을 포함한 결과물 전면 상에 매립 특성이 매우 우수한 감광막을 증착한다. 여기서, 상기 콘택홀 (24) 내에 매립된 감광막은 희생플러그(25)로서, 이후 수행할 CMP(Chemical Mechanical Polishing) 또는 에치백(Etch-back)공정시 콘택홀(24)의 형상을 유지시켜주는 역할을 한다. Referring to FIG. 2B, a photoresist film having excellent embedding characteristics is deposited on the entire surface of the resultant including the contact hole 24 to fill the contact hole 24. Here, the photoresist embedded in the contact hole 24 is a sacrificial plug 25, which maintains the shape of the contact hole 24 during a chemical mechanical polishing (CMP) or etch-back process. Play a role.

도 2c를 참조하면, 상기 희생플러그(25)의 상부를 포함한 층간절연막(23)의 표면 일부 두께를 CMP 또는 에치백 방식으로 제거한다. 이를 통해, 콘택홀(24) 상부의 너비가 넓어지게된다. 그런다음, 상기 콘택홀(24) 내의 희생플러그(25)를 제거한다. Referring to FIG. 2C, the thickness of a portion of the surface of the interlayer insulating layer 23 including the upper portion of the sacrificial plug 25 is removed by CMP or etch back. Through this, the width of the upper portion of the contact hole 24 is widened. Then, the sacrificial plug 25 in the contact hole 24 is removed.

도 2d를 참조하면, 상기 상부의 너비가 확장된 콘택홀(24)을 매립하도록 층간절연막(23) 상에 텅스텐 재질의 도전막을 증착한 후, 상기 도전막을 CMP하여 콘택홀(24) 내에 콘택플러그(26)를 형성한다. 그런 다음, 상기 층간절연막(23) 상에 콘택플러그(26)와 콘택되는 금속배선(27)을 형성한다. Referring to FIG. 2D, after depositing a tungsten material conductive layer on the interlayer insulating layer 23 so as to fill the contact hole 24 having an upper width, the conductive film is CMP to contact plug 24 in the contact hole 24. (26) is formed. Then, the metal wiring 27 in contact with the contact plug 26 is formed on the interlayer insulating film 23.

여기서, 본 발명은 상기한 바와 같이 상단부가 항아리 모양을 갖는 콘택홀(24)의 상부 일부를 CMP 또는 에치백 방식으로 제거하여 콘택홀(24) 상부의 너비를 넓혀줌으로써, 콘택홀(24) 내에 콘택플러그(26) 매립시 입구부의 병목현상을 방지할 수 있어 매립 특성을 개선할 수 있다.Here, the present invention by removing a portion of the upper portion of the contact hole 24 having a jar shape as described above by CMP or etch back method to widen the width of the upper portion of the contact hole 24, the contact hole 24 in the When the contact plug 26 is buried, bottlenecks of the inlet may be prevented, thereby improving the embedding characteristics.

이후, 도시하지는 않았으나, 공지의 후속 공정을 수행하여 본 발명의 반도체 소자를 완성한다.Thereafter, although not shown, the semiconductor device of the present invention is completed by performing a known subsequent process.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 반도체 소자의 금속배선을 형성함에 있어서, 상단부가 항아리 모양을 갖는 콘택홀의 상부 일부를 CMP 또는 에치백 방식으로 제거하여 콘택홀 상부의 너비를 넓혀줌으로써, 콘택홀 내에 콘택플러그 매립시 매립 특성을 개선할 수 있고, 이에 따라, 금속배선의 신뢰성 및 제품의 수율을 향상시킬 수 있다. As described above, the present invention in forming the metal wiring of the semiconductor device, by removing a portion of the upper portion of the contact hole having a jar shape by the CMP or etch back method to increase the width of the upper contact hole, the contact in the contact hole It is possible to improve the embedding characteristics when the plug is embedded, thereby improving the reliability of the metal wiring and the yield of the product.

Claims (4)

하부구조물을 구비한 반도체기판 상에 층간절연막을 형성하는 단계; Forming an interlayer insulating film on the semiconductor substrate having a lower structure; 상기 하부구조물이 노출되도록 층간절연막을 식각하여 상단부가 항아리 모양을 갖는 콘택홀을 형성하는 단계; Etching the interlayer insulating layer to expose the lower structure to form a contact hole having an upper end in a jar shape; 상기 콘택홀 내에 감광막으로 이루어진 희생플러그를 매립하는 단계; Embedding a sacrificial plug made of a photosensitive film in the contact hole; 상기 희생플러그 상부를 포함한 층간절연막의 표면 일부 두께를 제거하여 콘택홀 상부의 너비를 넓혀주는 단계; Widening the width of the upper portion of the contact hole by removing a portion of the surface of the interlayer insulating layer including the upper portion of the sacrificial plug; 상기 희생플러그를 제거하는 단계; Removing the sacrificial plug; 상기 상부의 너비가 확장된 콘택홀 내에 도전막을 매립하여 콘택플러그를 형성하는 단계; 및Forming a contact plug by burying a conductive film in the contact hole having an upper width; And 상기 층간절연막 상에 콘택플러그와 콘택되는 금속배선을 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법. And forming a metal wiring contacting the contact plug on the interlayer insulating film. 삭제delete 제 1 항에 있어서, 상기 희생플러그 상부를 포함한 층간절연막의 표면 일부 두께를 제거하는 단계는 CMP 또는 에치백 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the removing of the thickness of a portion of the surface of the interlayer insulating layer including the upper portion of the sacrificial plug is performed by a CMP or an etch back method. 제 1 항에 있어서, 상기 콘택플러그는 텅스텐으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the contact plug is made of tungsten.
KR1020050067869A 2005-07-26 2005-07-26 Method of manufacturing semiconductor device KR100680968B1 (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
KR19980048950A (en) * 1996-12-18 1998-09-15 김영환 Method for forming contact hole in semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980048950A (en) * 1996-12-18 1998-09-15 김영환 Method for forming contact hole in semiconductor device

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* Cited by examiner, † Cited by third party
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1019950021497 *
1019980048950 *

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