KR100831248B1 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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KR100831248B1
KR100831248B1 KR1020070047548A KR20070047548A KR100831248B1 KR 100831248 B1 KR100831248 B1 KR 100831248B1 KR 1020070047548 A KR1020070047548 A KR 1020070047548A KR 20070047548 A KR20070047548 A KR 20070047548A KR 100831248 B1 KR100831248 B1 KR 100831248B1
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metal
layer
contact
insulating film
forming
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KR1020070047548A
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Korean (ko)
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신민정
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming metal wiring of a semiconductor device is provided to enhance resistance characteristics in accordance with the contact area between the upper surface of a contact hole and a metal wiring layer by increasing the contact area during a CMP process. A method of forming metal wiring of a semiconductor device includes the following steps of: forming a pattern on a semiconductor substrate(11) on which an inter layer dielectric(13) is deposited; etching the pattern to form a contact hole; filling the contact hole with a metal insulation layer(14) and a contact metal layer(15); performing a first CMP process to form a planarization layer until the metal insulation layer and the contact metal layer are exposed; performing a second CMP process for the planarization layer to protrude the metal insulation layer and the contact metal layer; and depositing a metal wiring layer(16) to entire surface of the protruded metal insulation layer and contact metal layer to form metal wiring.

Description

반도체 소자의 금속배선 형성방법{method for forming metal line of semiconductor device}Method for forming metal line of semiconductor device

도 1a 내지 도 1e는 종래기술에 따른 반도체 소자의 금속배선 형성방법을 나타낸 공정 단면도. 1A to 1E are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the related art.

도 2a 내지 도 2f는 본 발명의 일실시 예에 따른 반도체 소자의 금속배선 형성방법을 나타낸 공정 단면도. 2A to 2F are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

본 발명은 반도체 소자의 금속배선 형성방법에 있어서, 특히 층간 저항 특성을 향상시킨 반도체 소자의 금속배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly to a method for forming metal wiring of a semiconductor device having improved interlayer resistance characteristics.

반도체 소자의 고집적화가 진행됨에 따라 소자의 크기를 축소하는 것 이외에도 소자의 성능을 향상시키기 위한 연구가 진행되고 있다. As the integration of semiconductor devices increases, research has been conducted to improve device performance in addition to reducing the size of the device.

현재 대부분의 반도체 소자의 배선공정은 단일 배선만으로는 고집적 소자의 동작시 요구되는 신호를 신속하게 전달하는데 어려움이 있기 때문에, 이를 극복하기 위하여 다층 배선구조를 채택하고 있다. Currently, the wiring process of most semiconductor devices has a difficulty in transferring signals required for the operation of the highly integrated device with only a single wiring, and thus adopts a multilayer wiring structure to overcome this problem.

이하, 첨부된 도 1a 내지 도 1e를 참조하여, 종래기술에 따른 반도체 소자의 금속배선 형성방법을 설명하기로 한다. Hereinafter, a method of forming metal wirings of a semiconductor device according to the related art will be described with reference to FIGS. 1A to 1E.

도 1a 내지 도 1e는 종래기술에 따른 반도체 소자의 금속배선 형성방법을 나타낸 공정 단면도이다. 1A to 1E are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the prior art.

우선, 도 1a는 금속 배선 공정 진행 전의 단면으로서, 공지된 기술에 따라 반도체 기판(1)에 트랜지스터(Transistor: 2)가 형성된 것이다. First, FIG. 1A is a cross section before a metal wiring process progresses, and the transistor (Transistor) 2 is formed in the semiconductor substrate 1 by well-known technique.

도 1b는 상기 트랜지스터(2)가 형성된 기판(1)상에 층간 절연막(3)을 증착한 후, 패턴을 형성하고 식각하여 콘택홀을 형성한 것이다. In FIG. 1B, after the interlayer insulating layer 3 is deposited on the substrate 1 on which the transistor 2 is formed, a pattern is formed and then etched to form a contact hole.

이후, 도 1c에 따라, 상기 콘택홀에 Ti/TiN을 증착하여 금속절연막(4)을 형성하고, 텅스텐(W)을 채워넣어 콘택금속층(5)을 형성한다. Thereafter, according to FIG. 1C, Ti / TiN is deposited in the contact hole to form the metal insulating layer 4, and tungsten (W) is filled to form the contact metal layer 5.

그리고, 도 1d에 따라, 상기 금속절연막(4)이 드러날 때까지 상기 콘택금속층(5)을 평탄화하여 콘택 플러그를 형성한다. 이때, 상기 평탄화 과정은 기계적 및 화학적 연마를 동시에 수행하는 CMP(Chemical Mechnical Polishing) 공정을 통해 이루어지는 것이다. 1D, the contact metal layer 5 is planarized until the metal insulating film 4 is exposed to form a contact plug. In this case, the planarization process is performed through a chemical mechanical polishing (CMP) process that simultaneously performs mechanical and chemical polishing.

그런 다음, 도 1e와 같이, 상기 평탄화된 콘택금속층(5) 위에 금속물질(Al)을 증착하여 금속배선층(6)을 형성한다. Then, as shown in FIG. 1E, a metal material Al is deposited on the planarized contact metal layer 5 to form a metal wiring layer 6.

그러나, 상기와 같이, 종래기술에 따라 생성된 콘택홀 상단면과 금속배선층의 접촉면적이 제한적이므로, 금속 저항 특성에 취약한 문제점이 있다. However, as described above, since the contact area between the contact hole top surface and the metal wiring layer generated according to the prior art is limited, there is a problem that the metal resistance characteristics are weak.

본 발명의 목적은 상기한 문제점을 감안하여 안출한 것으로서, CMP 공정에서 사용되는 슬러리(slurry)의 식각 선택비를 이용하여, 콘택홀 상단면과 금속배선층 의 접촉면적을 증가시킴으로써, 상기 접촉면적에 따른 저항 특성을 향상시키는 반도체 소자의 금속배선 형성방법을 제공하는 것이다. An object of the present invention has been made in view of the above problems, by using the etching selectivity of the slurry used in the CMP process, by increasing the contact area between the upper surface of the contact hole and the metal wiring layer, It is to provide a metal wiring forming method of a semiconductor device to improve the resistance characteristics according to.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성방법의 일 특징은, 층간 절연막이 증착된 반도체 기판에 패턴을 형성하는 단계, 상기 패턴을 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀에 금속절연막 및 콘택금속층을 매립하는 단계, 상기 금속절연막 및 콘택금속층이 드러날 때까지 1차 CMP 공정을 실시하여 평탄화층을 형성하는 단계, 상기 평탄화층에 2차 CMP 공정을 실시하여 상기 금속절연막 및 콘택금속층을 돌출시키는 단계 및 상기 돌출된 금속절연막 및 콘택금속층 전면에 금속배선층을 증착하여 금속배선을 형성하는 단계를 포함한다. According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: forming a pattern on a semiconductor substrate on which an interlayer insulating film is deposited; forming a contact hole by etching the pattern; Embedding a metal insulating film and a contact metal layer in the contact hole, performing a first CMP process until the metal insulating film and the contact metal layer are exposed to form a planarization layer, and performing a second CMP process on the planarization layer. Protruding the metal insulating film and the contact metal layer and forming a metal wiring by depositing a metal wiring layer on the entire surface of the protruding metal insulating film and the contact metal layer.

보다 바람직하게, 상기 2차 CMP 공정은 상기 층간 절연막에 대해 높은 선택비를 갖는 슬러리를 사용한다. More preferably, the secondary CMP process uses a slurry having a high selectivity to the interlayer insulating film.

보다 바람직하게, 상기 2차 CMP 공정은 상기 층간 절연막에 대한 상기 금속절연막 및 콘택금속층의 식각 선택비가 1:20인 슬러리를 사용한다. More preferably, the secondary CMP process uses a slurry having an etching selectivity of 1:20 of the metal insulating film and the contact metal layer with respect to the interlayer insulating film.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예의 구성과 그 작용을 설명하며, 도면에 도시되고 또 이것에 의해서 설명되는 본 발명의 구성과 작용은 적어도 하나의 실시 예로서 설명되는 것이며, 이것에 의해서 상기한 본 발명의 기술적 사상과 그 핵심 구성 및 작용이 제한되지는 않는다.Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

도 2a 내지 도 2f는 본 발명의 일실시 예에 따른 반도체 소자의 금속배선 형 성방법을 나타낸 공정 단면도이다. 2A through 2F are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

우선, 도 2a는 금속 배선 공정 진행 전의 단면으로서, 종래기술과 같이, 공지된 기술에 따라 반도체 기판(11)에 트랜지스터(Transistor: 12)가 형성된 것이다. First, FIG. 2A is a cross section before a metal wiring process progresses, and the transistor 12 is formed in the semiconductor substrate 11 according to a well-known technique like the prior art.

도 2b는 상기 트랜지스터(12)가 형성된 기판(11) 상에 층간절연막(13)을 증착한 후, 패턴을 형성하고 식각하여 콘택홀을 형성한 것이다. In FIG. 2B, after the interlayer insulating layer 13 is deposited on the substrate 11 on which the transistor 12 is formed, a pattern is formed and then etched to form a contact hole.

이후, 도 2c에 따라, 상기 콘택홀에 금속절연막(14)으로서 Ti/TiN을 증착하고, 상기 금속절연막(14)이 형성된 콘택홀에 텅스텐(W)을 채워넣어 콘택금속층(15)을 형성한다. After that, according to FIG. 2C, Ti / TiN is deposited as the metal insulating layer 14 in the contact hole, and the contact metal layer 15 is formed by filling tungsten (W) into the contact hole in which the metal insulating layer 14 is formed. .

그리고, 도 2d와 같이, 상기 금속절연막(14) 및 콘택금속층(15)이 드러날 때까지 1차 CMP를 진행하여 평탄화한다. As shown in FIG. 2D, the first CMP is flattened until the metal insulating film 14 and the contact metal layer 15 are exposed.

상기 평탄화는 CMP(Chemical Mechnical Polishing) 공정을 통해 이루어지는 것으로서, 상기 CMP 공정은 패드(pad)에 의한 기계적인 연마 및 슬러리(slurry)에 의한 화학적인 연마가 동시에 수행되는 것이다. The planarization is performed through a chemical mechanical polishing (CMP) process, in which the mechanical polishing by a pad and chemical polishing by a slurry are simultaneously performed.

이때, 상기 슬러리의 선택비에 의해 CMP할 물질의 연마 정도가 다르므로, 상기 슬러리의 식각 선택비를 조절하여 상기 CMP할 물질을 선택적으로 연마할 수 있다. In this case, since the degree of polishing of the material to be CMP varies depending on the selectivity of the slurry, the material to be CMP may be selectively polished by adjusting the etching selectivity of the slurry.

예를 들어, CMP할 물질에 대해 높은 식각 선택비를 갖는 슬러리를 사용하여 CMP 공정을 실시하면, 상기 CMP할 물질이 많이 식각되고, 또한, CMP할 물질에 대해 낮은 식각 선택비를 갖는 슬러리를 사용하여 CMP를 실시하면, 그 반대의 경우가 발 생하게 된다. For example, when the CMP process is performed using a slurry having a high etching selectivity with respect to the material to be CMP, a lot of the material to be CMP is etched, and a slurry having a low etching selectivity with respect to the material to be CMP is used. If CMP is executed, the opposite is the case.

이후, 상기 층간 절연막(13)에 대해 낮은 선택비를 갖는 슬러리를 사용하여 CMP 공정을 진행한다. Thereafter, a CMP process is performed using a slurry having a low selectivity with respect to the interlayer insulating layer 13.

그러면, 도 2e에 도시된 바와 같이, 상기 층간 절연막(13)이 상기 금속절연막(14) 및 콘택금속층(15) 보다 더 많이 연마된다. 따라서, 상대적으로 상기 금속절연막(14) 및 콘택금속층(15)이 돌출된다. Then, as shown in FIG. 2E, the interlayer insulating film 13 is polished more than the metal insulating film 14 and the contact metal layer 15. Accordingly, the metal insulating film 14 and the contact metal layer 15 protrude relatively.

도 2f는 상기 돌출된 금속절연막(14) 및 콘택금속층(15)의 상부 전면에 금속배선층(16)을 증착하여 배선을 형성한 것이다. FIG. 2F is a wiring formed by depositing a metal wiring layer 16 on the upper surface of the protruding metal insulating film 14 and the contact metal layer 15.

상기 금속절연막(14) 및 콘택금속층(15)이 돌출됨으로써, 상기 금속절연막(14) 및 콘택금속층(15)과 그 위에 증착된 금속배선층(16)의 접촉면적이 늘어났음을 알 수 있다. 또한, 상기 접촉면적이 늘어남에 따라, 상기 콘택금속층(15)의 전기적 저항이 줄어드는 장점이 있다. As the metal insulating layer 14 and the contact metal layer 15 protrude, it can be seen that the contact area between the metal insulating layer 14 and the contact metal layer 15 and the metal wiring layer 16 deposited thereon is increased. In addition, as the contact area increases, the electrical resistance of the contact metal layer 15 is reduced.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 실시 예에 기재된 내용으로 한정하는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

이상에서 설명한 바와 같이, 본 발명은 CMP 공정 시, 콘택홀 상단면과 금속배선트의 접촉면적을 증가시킴으로써, 상기 접촉면적에 따른 저항특성을 향상시킬 수 있는 효과가 있다. As described above, the present invention increases the contact area of the contact hole top surface and the metal wiring in the CMP process, thereby improving the resistance characteristics according to the contact area.

Claims (3)

층간 절연막이 증착된 반도체 기판에 패턴을 형성하는 단계; Forming a pattern on the semiconductor substrate on which the interlayer insulating film is deposited; 상기 패턴을 식각하여 콘택홀을 형성하는 단계; Etching the pattern to form contact holes; 상기 콘택홀에 금속절연막 및 콘택금속층을 매립하는 단계: Embedding a metal insulating film and a contact metal layer in the contact hole: 상기 금속절연막 및 콘택금속층이 드러날 때까지 1차 CMP 공정을 실시하여 평탄화층을 형성하는 단계; Forming a planarization layer by performing a first CMP process until the metal insulating layer and the contact metal layer are exposed; 상기 평탄화층에 2차 CMP 공정을 실시하여 상기 금속절연막 및 콘택금속층을 돌출시키는 단계; 및Performing a second CMP process on the planarization layer to protrude the metal insulating layer and the contact metal layer; And 상기 돌출된 금속절연막 및 콘택금속층 전면에 금속배선층을 증착하여 금속배선을 형성하는 단계를 포함하여 이루어지는 반도체 소자의 금속배선 형성방법. Forming a metal wiring by depositing a metal wiring layer on the entire surface of the protruding metal insulating film and the contact metal layer. 제 1 항에 있어서, The method of claim 1, 상기 2차 CMP 공정은 상기 층간 절연막에 대해 높은 선택비를 갖는 슬러리를 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법. The second CMP process uses a slurry having a high selectivity with respect to the interlayer insulating film. 제 1 항에 있어서, The method of claim 1, 상기 2차 CMP 공정은 상기 층간 절연막에 대한 상기 금속절연막 및 콘택금속층의 식각 선택비가 1:20인 슬러리를 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법. The second CMP process uses a slurry in which an etch selectivity of the metal insulating film and the contact metal layer is 1:20 with respect to the interlayer insulating film.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009814A (en) * 1999-07-14 2001-02-05 윤종용 Method for forming a contact plug of a semiconductor device
KR20010026126A (en) * 1999-09-03 2001-04-06 윤종용 Method of manufacturing electrical interconnection for semiconductor device
KR20020086100A (en) * 2001-05-11 2002-11-18 아남반도체 주식회사 a forming method of a contact for multi-level interconnects

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009814A (en) * 1999-07-14 2001-02-05 윤종용 Method for forming a contact plug of a semiconductor device
KR20010026126A (en) * 1999-09-03 2001-04-06 윤종용 Method of manufacturing electrical interconnection for semiconductor device
KR20020086100A (en) * 2001-05-11 2002-11-18 아남반도체 주식회사 a forming method of a contact for multi-level interconnects

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