KR20080000895A - Method for forming metal line in semiconductor device - Google Patents

Method for forming metal line in semiconductor device Download PDF

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Publication number
KR20080000895A
KR20080000895A KR1020060058763A KR20060058763A KR20080000895A KR 20080000895 A KR20080000895 A KR 20080000895A KR 1020060058763 A KR1020060058763 A KR 1020060058763A KR 20060058763 A KR20060058763 A KR 20060058763A KR 20080000895 A KR20080000895 A KR 20080000895A
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South Korea
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forming
film
conductive film
wiring
interlayer insulating
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KR1020060058763A
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Korean (ko)
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이현우
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주식회사 하이닉스반도체
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Publication of KR20080000895A publication Critical patent/KR20080000895A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a wiring of a semiconductor device is provided to reduce a volume of a barrier metal layer and to increase a volume of a main wiring material by forming a lower part of the wiring with a damascene method and forming an upper part of the wiring with an RIE method. A first interlayer dielectric(23) is formed on a semiconductor substrate(20). An opening is formed by etching a predetermined region of the first interlayer dielectric. A first conductive layer(26) is formed by inserting a barrier metal layer(25) into the opening. A second conductive layer(27) is formed on the first conductive layer and the predetermined region of the first interlayer dielectric adjacent to the first conductive layer to form a wiring(28). A second interlayer dielectric is formed on the entire surface including the second conductive layer. The second interlayer dielectric is planarized to expose the second conductive layer.

Description

반도체 소자의 배선 형성방법{Method for forming metal line in semiconductor device}Method for forming metal line in semiconductor device

도 1a 내지 도 1d는 본 발명의 실시예에 따른 배선 형성 공정에 따른 단면도들1A to 1D are cross-sectional views of a wire forming process according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

20 : 반도체 기판 23 : 제 1 층간절연막20 semiconductor substrate 23 first interlayer insulating film

24 : 개구부 25 : 장벽 금속막24: opening 25: barrier metal film

26 : 제 1 금속막 27 : 제 2 금속막26: first metal film 27: second metal film

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 배선의 저항을 줄이기 위한 반도체 소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming wirings in semiconductor devices for reducing resistance of wirings.

반도체 소자의 선폭이 미세화되고 집적도가 증가함에 따라 기존의 RIE(Reactive Ion Etch) 공정을 이용한 배선 형성 방법으로는 원하는 선폭의 배선 을 형성하는데 한계가 있다. 따라서, 현재는 상감법(damascene)을 이용하여 배선을 형성하고 있다. As the line width of the semiconductor device becomes smaller and the degree of integration increases, there is a limit in forming a wire having a desired line width using a conventional wire formation method using a reactive ion etching (RIE) process. Therefore, wiring is currently formed by using a damascene method.

상감법은 층간절연막에 개구부를 형성하고 개구부에 금속 물질을 매립하여 배선을 형성하는 방법이다. 금속 물질로는 텅스텐(W)을 주로 사용하였으나, 선폭이 감소됨에 따라 증가되는 배선 저항을 줄이기 위하여 텅스텐 대신 텅스텐보다 저항이 낮은 알루미늄(Al)을 사용하게 되었다.The damascene method is a method of forming wirings by forming openings in an interlayer insulating film and embedding a metal material in the openings. Although tungsten (W) was mainly used as a metal material, aluminum (Al) having lower resistance than tungsten was used instead of tungsten in order to reduce wiring resistance that increases as the line width decreases.

금속 물질을 형성하기 전에 금속 물질에 비하여 상대적으로 큰 저항값을 갖는 Ti/TiN 구조의 장벽 금속막을 형성해야 하는데, 집적도 향상으로 개구부의 사이즈가 감소됨에 따라서 개구부 내에서 장벽 금속막이 차지하는 비중이 커지게 되어 배선의 저항은 증가되게 된다.Before forming the metal material, a barrier metal film having a Ti / TiN structure having a relatively higher resistance value than that of the metal material should be formed. As the size of the opening decreases due to the increase in the density, the portion of the barrier metal film in the opening increases. As a result, the resistance of the wiring is increased.

따라서, 본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 배선의 저항을 줄이기 위한 반도체 소자의 배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a wiring of a semiconductor device for reducing the resistance of the wiring, which has been devised to solve the above-described problems of the prior art.

본 발명에 따른 반도체 소자의 배선 형성방법은 반도체 기판상에 제 1 층간절연막을 형성하는 단계와, 상기 제 1 층간절연막의 소정 영역을 식각하여 개구부를 형성하는 단계와, 상기 개구부 내에 장벽 금속막을 개재하여 제 1 도전막을 형 성하는 단계와, 상기 제 1 도전막 및 이에 인접한 상기 제 1 층간절연막의 소정 영역상에 제 2 도전막을 형성하여 상기 제 1 도전막과 상기 제 2 도전막으로 구성되는 배선을 형성하는 단계와, 상기 제 2 도전막을 포함한 전면에 제 2 층간절연막을 형성하고 상기 제 2 도전막이 노출되도록 상기 제 2 층간절연막을 평탄화하는 단계를 포함한다. A method of forming a wiring of a semiconductor device according to the present invention includes forming a first interlayer insulating film on a semiconductor substrate, forming an opening by etching a predetermined region of the first interlayer insulating film, and interposing a barrier metal film in the opening. Forming a first conductive film, and forming a second conductive film on a predetermined region of the first conductive film and the first interlayer insulating film adjacent thereto to form a first conductive film and the second conductive film. Forming a second interlayer insulating film on the entire surface including the second conductive film and planarizing the second interlayer insulating film to expose the second conductive film.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A to 1D are cross-sectional views of devices for describing a method of forming wirings of a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(20)이 제공된다. 예를 들면, 반도체 기판(20)에는 트랜지스터나 메모리 셀(미도시)이 형성될 수 있다. Referring to FIG. 1A, a semiconductor substrate 20 having various elements for forming a semiconductor device is provided. For example, a transistor or a memory cell (not shown) may be formed in the semiconductor substrate 20.

이어서, 반도체 기판(20)상에 버퍼 산화막(21)과 스탑퍼 질화막(22)과 제 1 층간절연막(23)을 순차 형성한다. 버퍼 산화막(21)은 이후 개구부 형성을 위한 식각 공정시 반도체 기판(20)을 보호하기 위한 것이고, 스탑퍼 질화막(22)은 개구부의 깊이를 균일하게 형성하기 위한 것으로, 경우에 따라서 버퍼 산화막(21)과 스탑 퍼 질화막(22)은 형성하지 않아도 무방하다.Subsequently, a buffer oxide film 21, a stopper nitride film 22, and a first interlayer insulating film 23 are sequentially formed on the semiconductor substrate 20. The buffer oxide film 21 is intended to protect the semiconductor substrate 20 during the etching process for forming the opening thereafter, and the stopper nitride film 22 is for uniformly forming the depth of the opening, and in some cases, the buffer oxide film 21. ) And the stopper nitride film 22 may not be formed.

이어, 제 1 층간절연막(23)의 소정 부분을 식각하여 개구부(24)를 형성한다. 식각 공정은 스탑퍼 질화막(22)이 노출되도록 제 1 층간절연막(23)을 식각하는 메인 식각 공정과 제 1 층간절연막(23)의 식각된 하부의 스탑퍼 질화막(22)을 제거하는 오버 식각(over etch) 공정 순으로 진행한다. 메인 식각 공정이 스탑퍼 질화막(22)에 의해 멈춰지게 되므로 개구부(24)는 균일한 깊이를 갖게 된다. Subsequently, a predetermined portion of the first interlayer insulating layer 23 is etched to form the opening 24. The etching process includes a main etching process for etching the first interlayer insulating film 23 so that the stopper nitride film 22 is exposed, and an over etching for removing the etched lower stopper nitride film 22 of the first interlayer insulating film 23 ( over etch) process. Since the main etching process is stopped by the stopper nitride film 22, the opening 24 has a uniform depth.

도 1b를 참조하면, 개구부(24)를 포함한 전체 구조상에 장벽 금속막(25)을 형성한다. 장벽 금속막(25)은 TiN 또는 TiW로 형성할 수 있으며, Ti/TiN 또는 Ti/TiW의 적층 구조로 형성할 수도 있다. 여기서, Ti는 TiN 또는 TiW와 하부층간의 접착(adhesion) 특성을 향상시키기 위하여 형성한다.Referring to FIG. 1B, a barrier metal film 25 is formed on the entire structure including the opening 24. The barrier metal film 25 may be formed of TiN or TiW, or may be formed of a stacked structure of Ti / TiN or Ti / TiW. Here, Ti is formed to improve the adhesion characteristics between TiN or TiW and the lower layer.

이어, 주배선재료용 금속 물질을 증착하여 제 1 금속막(26)을 형성한다. 주배선재료용 금속 물질은 텅스텐(W) 또는 알루미늄(Al)을 사용할 수 있으며, 텅스텐보다 저항이 낮은 알루미늄을 사용하는 것이 보다 바람직하다.Subsequently, a metal material for the main wiring material is deposited to form the first metal film 26. Tungsten (W) or aluminum (Al) may be used as the metal material for the main wiring material, and it is more preferable to use aluminum having a lower resistance than tungsten.

도 1c를 참조하면, 제 1 층간절연막(23)이 노출되도록 전면에 평탄화 공정을 실시하여 장벽 금속막(25) 및 제 1 금속막(26)을 개구부(24) 내에만 남긴다. 평탄화 공정은 CMP(Chemical Mechanical Polishing) 공정 또는 에치백(etchback) 공정을 이용함이 바람직하다.Referring to FIG. 1C, a planarization process is performed on the entire surface of the first interlayer insulating film 23 to expose the barrier metal film 25 and the first metal film 26 only in the opening 24. The planarization process is preferably a chemical mechanical polishing (CMP) process or an etchback process.

도 1d를 참조하면, RIE(Reactive Ion Etching) 공정으로 제 1 금속막(26) 및 이에 인접한 제 1 층간절연막(23)의 소정 영역상에 제 2 금속막(27)을 형성한다.Referring to FIG. 1D, a second metal layer 27 is formed on a predetermined region of the first metal layer 26 and the first interlayer insulating layer 23 adjacent thereto by a reactive ion etching (RIE) process.

즉, 전면에 주배선재료용 금속 물질을 형성하고 제 1 금속막(26) 및 이에 인 접한 제 1 층간절연막(23)의 소정 영역에 남도록 주배선재료용 금속 물질을 식각하여 제 2 금속막(27)을 형성한다. 주배선재료용 금속 물질은 텅스텐(W) 또는 알루미늄(Al)을 사용할 수 있으며, 텅스텐보다 저항이 낮은 알루미늄을 사용하는 것이 보다 바람직하다.That is, the metal material for the main wiring material is etched to form the metal material for the main wiring material on the entire surface and to remain in the predetermined region of the first metal film 26 and the first interlayer insulating film 23 adjacent thereto. 27). Tungsten (W) or aluminum (Al) may be used as the metal material for the main wiring material, and it is more preferable to use aluminum having a lower resistance than tungsten.

이로써, 제 1 금속막(26) 및 제 2 금속막(27)으로 이루어진 배선(28)이 형성된다. Thereby, the wiring 28 which consists of the 1st metal film 26 and the 2nd metal film 27 is formed.

제 2 금속막(27)의 두께는 제 1 금속막(26)의 두께와 동일한 두께로 형성하는 것이 바람직하지만, 이에 한정되는 것은 아니다. The thickness of the second metal film 27 is preferably formed to be the same as the thickness of the first metal film 26, but is not limited thereto.

그리고, 제 2 금속막(27)을 포함한 전면에 제 2 층간절연막(29)을 형성하고, 제 2 금속막(27)이 노출되도록 제 2 층간절연막(29)을 평탄화한다.Then, the second interlayer insulating film 29 is formed on the entire surface including the second metal film 27, and the second interlayer insulating film 29 is planarized so that the second metal film 27 is exposed.

이상으로, 본 발명에 따른 반도체 소자의 배선 형성 공정을 완료한다.In the above, the wiring formation process of the semiconductor element which concerns on this invention is completed.

본 발명에서는 배선의 하부는 다마신법으로 형성하고 배선의 상부는 RIE법으로 형성하여 장벽 금속막이 차지하는 비중을 줄이고 대신 주배선재료가 차지하는 비중을 늘리어 배선의 저항을 줄일 수 있다. In the present invention, the lower part of the wiring is formed by the damascene method and the upper part of the wiring is formed by the RIE method, thereby reducing the specific gravity of the barrier metal film and increasing the specific gravity of the main wiring material, thereby reducing the resistance of the wiring.

또한, 배선의 상부를 다마신법과 달리 수직한 측면 프로파일을 형성할 수 있는 RIE 공정으로 형성하여 주배선재료의 체적을 늘릴 수 있으므로 배선 저항을 줄일 수 있다.In addition, unlike the damascene method, the upper portion of the wiring may be formed by a RIE process capable of forming a vertical side profile, thereby increasing the volume of the main wiring material, thereby reducing wiring resistance.

예를 들어, 배선의 하부 1/2를 다마신법으로 형성하고 나머지 상부 1/2를 RIE법으로 형성한 경우 장벽 금속층의 비중 감소에 따른 주배선재료의 체적 증가는 최대 39.4% 정도이고, 수직한 측면 프로파일 형성이 가능한 RIE법을 적용함에 따른 주배선재료의 체적 증가는 최대 15.1% 정도이다.For example, when the lower half of the wiring is formed by the damascene method and the remaining upper half is formed by the RIE method, the volume increase of the main wiring material according to the decrease of the specific gravity of the barrier metal layer is up to 39.4%, The volume increase of the main wiring material by applying the RIE method which can form the side profile is up to 15.1%.

상술한 바와 같이, 본 발명은 배선 하부는 다마신 법으로 형성하고 배선 상부는 RIE법으로 형성하여 장벽 금속막의 체적을 줄이는 대신 주배선재료의 체적을 늘릴 수 있고, RIE법으로 수직한 측면 프로파일을 형성하여 주배선재료의 체적을 늘릴 수 있으므로 배선의 저항을 줄일 수 있는 효과가 있다.As described above, in the present invention, the lower part of the wiring is formed by the damascene method and the upper part of the wiring is formed by the RIE method, so that the volume of the main wiring material can be increased instead of reducing the volume of the barrier metal film. Since the volume of the main wiring material can be increased by forming, the resistance of the wiring can be reduced.

Claims (4)

반도체 기판상에 제 1 층간절연막을 형성하는 단계;Forming a first interlayer insulating film on the semiconductor substrate; 상기 제 1 층간절연막의 소정 영역을 식각하여 개구부를 형성하는 단계;Etching an area of the first interlayer insulating film to form an opening; 상기 개구부 내에 장벽 금속막을 개재하여 제 1 도전막을 형성하는 단계;Forming a first conductive film through the barrier metal film in the opening; 상기 제 1 도전막 및 이에 인접한 상기 제 1 층간절연막의 소정 영역상에 제 2 도전막을 형성하여 상기 제 1 도전막과 상기 제 2 도전막으로 구성되는 배선을 형성하는 단계; 및Forming a second conductive film on a predetermined region of the first conductive film and the first interlayer insulating film adjacent to the first conductive film and forming a wiring including the first conductive film and the second conductive film; And 상기 제 2 도전막을 포함한 전면에 제 2 층간절연막을 형성하고 상기 제 2 도전막이 노출되도록 상기 제 2 층간절연막을 평탄화하는 단계를 포함하는 반도체 소자의 배선 형성방법.And forming a second interlayer insulating film on the entire surface including the second conductive film and planarizing the second interlayer insulating film to expose the second conductive film. 제 1항에 있어서, 상기 제 1 도전막 및 상기 제 2 도전막은 알루미늄막으로 형성하는 반도체 소자의 배선 형성방법.The method of forming a wiring according to claim 1, wherein the first conductive film and the second conductive film are formed of an aluminum film. 제 1항에 있어서, 상기 절연막을 형성하기 전에 상기 반도체 기판에 버퍼 산화막과 스탑퍼 질화막을 형성하는 단계를 더 포함하는 반도체 소자의 배선 형성방법.The method of claim 1, further comprising forming a buffer oxide film and a stopper nitride film on the semiconductor substrate before forming the insulating film. 제 1항에 있어서, 상기 제 2 도전막은 상기 제 1 도전막을 포함한 전면에 도전막을 형성하고 상기 제 1 도전막 및 이에 인접한 상기 제 1 층간절연막의 소정 영역상에 남도록 도전막을 패터닝하여 형성하는 반도체 소자의 형성방법.The semiconductor device of claim 1, wherein the second conductive film is formed by forming a conductive film on an entire surface including the first conductive film and patterning the conductive film so as to remain on a predetermined region of the first conductive film and the first interlayer insulating film adjacent thereto. Method of formation.
KR1020060058763A 2006-06-28 2006-06-28 Method for forming metal line in semiconductor device KR20080000895A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210296265A1 (en) * 2020-03-23 2021-09-23 Kabushiki Kaisha Toshiba Isolator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210296265A1 (en) * 2020-03-23 2021-09-23 Kabushiki Kaisha Toshiba Isolator
US11916027B2 (en) * 2020-03-23 2024-02-27 Kabushiki Kaisha Toshiba Isolator

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