JP2002299343A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dishing or erosion generated by over-polishing in CMP, in forming wiring trenches arranged densely and sparsely for forming highly reliable trench wiring. SOLUTION: A first conductive layer 16 is formed so as to fill at least a part of the wiring trenches (recesses) 13, by plating on a substrate 11 having the recesses. On the first conductive film 16, a second conductive film 17 is formed so as to fill all of the wiring trenches 13. Then, the second conductive film 17 and the first conductive film 16 are removed from the peripheries of the wiring trenches 13 on the substrate 11, to form the wiring 18 by the first conductive film 16 and the second conductive film 17, filled in the wiring trenches 13 which is formed on the substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which dishing and erosion are reduced to form a buried wiring.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a trench wiring connected to a lower conductive layer, a formation method by a so-called dual damascene method and a formation method by a so-called damascene method are known. For example, “Next-generation ULSI process technology”
12-2-29) FIG. 14 of Realize Inc. p. 42 shows a cross-sectional view of an LSI wiring structure. The upper layer has a dual damascene structure of copper, and the lower layer has a laminated structure of a damascene structure of tungsten and a single damascene structure of copper.

The copper dual damascene structure is a method in which a wiring groove and a wiring hole are formed at once, and then a buried wiring is formed. The method is described in Monthly Semiconductor World, [12] (1998) p.
138-139.

[0004] This manufacturing method will be described with reference to FIG. As shown in FIG. 5A, an interlayer insulating film 1 is formed on a substrate 111.
12 is formed. Next, as shown in FIG.
A wiring groove 113 is formed in the interlayer insulating film 112, and a wiring hole 114 is formed at the bottom of the wiring groove 113.

Next, as shown in FIG. 5C, a barrier metal layer 115 is formed of, for example, a tantalum nitride film on the inner walls of the wiring grooves 113 and the wiring holes 114 and on the interlayer insulating film 112. Next, as shown in (4) of FIG.
The wiring groove 113 and the wiring hole 114 are formed by plating.
Is buried with a copper film 116. At this time, the copper film 116 is also formed on the interlayer insulating film 112.

Thereafter, the copper film 116 and the barrier metal layer 115 on the interlayer insulating film 112 are removed by chemical mechanical polishing (hereinafter referred to as CMP), and as shown in FIG. Then, a buried plug 117 is formed in the wiring hole 114 while the copper film 116 is left inside the wiring groove 113 and the wiring hole 114, and a buried wiring 118 is formed in the wiring groove 113.

Next, a manufacturing method for forming a laminated structure of a damascene structure of tungsten and a damascene structure of copper will be described with reference to FIG.
This will be described with reference to the manufacturing process sectional views of FIG.

As shown in FIG. 6A, an interlayer insulating film 212 is formed on a substrate 211. Next, a wiring hole 213 is formed in the interlayer insulating film 212.

Next, as shown in FIG. 6B, a barrier metal layer 214 is formed of, for example, a titanium nitride film on the inner wall of the wiring hole 213 and on the interlayer insulating film 212. Next, for example, chemical vapor deposition (hereinafter referred to as CVD)
The inside of the wiring hole 213 is filled with a tungsten film 215 by a Chemical Vapor Deposition method. At this time, the tungsten film 215 is also formed on the interlayer insulating film 212.
Is formed.

Thereafter, the interlayer insulating film 212 is formed by CMP.
The upper tungsten film 215 and the barrier metal layer 214 are removed, and as shown in FIG. 6C, the tungsten film 215 is left inside the wiring hole 213 via the barrier metal layer 214 and the wiring An embedded plug 216 is formed in the hole 213.

[0011] Then, as shown in FIG. 6 (4), an interlayer insulating film 222 is further formed on the interlayer insulating film 212. Next, a wiring groove 223 is formed in the interlayer insulating film 222.

Next, as shown in FIG. 6 (5), a barrier metal layer 224 is formed of, for example, a tantalum nitride film on the inner wall of the wiring groove 223 and the interlayer insulating film 222. Next, the inside of the wiring groove 223 is filled with a copper film 225 by plating. At this time, a copper film 225 is also formed on the interlayer insulating film 222.

Thereafter, the copper film 225 and the barrier metal layer 224 on the interlayer insulating film 222 are removed by CMP, which is referred to as “CMP”. As shown in FIG. The buried wiring 226 connected to the buried plug 216 is formed in the wiring groove 223 while leaving the film 225.

[0014]

However, at the time of forming a film by burying copper, a wide concave portion is sufficiently covered and copper is removed by C.
It is necessary to form a film having a depth that is greater than the depth of the concave portion by taking a margin for removing by MP into consideration. In the prior art, this copper film is formed by a plating method, but at the same time, as a characteristic of plating, a film forming speed on a thin portion of a wiring is higher than that of a wide wiring portion. Therefore, there is a problem that the thickness of the copper film on the insulating film varies. This is presumably because the surface condition of copper is different between a narrow portion of the wiring and a wide portion of the wiring due to the effect of an additive mixed with the plating solution for embedding in the fine wiring.

In a state where the thickness of the copper film varies, the CMP
In this case, since it is necessary to perform CMP until the copper in the thickest portion disappears, overpolishing occurs in the portion where the copper is thinner, causing a problem of dishing and erosion.

[0016]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a first conductive film on a substrate surface having a concave portion by plating so as to bury at least a part of the concave portion;
Forming a second conductive film on the first conductive film so as to fill the whole of the concave portion, and removing the second conductive film and the first conductive film on the substrate around the concave portion; Forming a wiring with the first conductive film and the second conductive film embedded in the concave portion.

In the method of manufacturing a semiconductor device, since the first conductive film is buried in the concave portion by the plating method and then the second conductive film is buried, the thickness of the concave portion is removed only by the plating method and removed by polishing. Therefore, it is not necessary to form a film having a thickness that includes an extra thickness in consideration of the above, and the thickness of the recess and the extra thickness are adjusted in a state where the first conductive film and the second conductive film are combined. What is necessary is just to set it as a film thickness.

Plating is characterized in that the smaller the amount of film formation, the smaller the variation in thickness. Therefore, if a sputtering method or a CVD method other than the plating method is used as a method for forming the second conductive film, a uniform film can be formed regardless of the surface state of the first conductive film formed by plating. Variation in thickness before polishing is suppressed. As a result, overpolishing during polishing can be suppressed, and dishing and erosion are reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to a cross-sectional view of a manufacturing process shown in FIG.

As shown in FIG. 1A, an interlayer insulating film 12 is formed on a substrate 11 by, for example, a silicon oxide film having a thickness of 1000 nm.

Next, as shown in FIG. 1B, a concave portion (hereinafter referred to as a wiring groove) 1 is formed in the interlayer insulating film 12.
Form 3 The wiring groove 13 is formed by densely forming narrow wiring grooves 13 (13sa) having a width of, for example, 0.2 μm at a pitch of, for example, 0.4 μm in a certain area, and having a width of, for example, 0.2 μm in a certain area. Wiring groove 13 (13s
b) is sparsely formed at a pitch of, for example, 100 μm, and a wide wiring groove 13 (13w) having a width of, for example, 100 μm is formed in a certain region.

Then, as shown in FIG. 1C, a barrier metal layer (not shown) is formed on the inner wall of the wiring groove 13 and the interlayer insulating film 12 by, for example, sputtering to form a tantalum nitride film having a thickness of 30 nm. Formed on the surface. Further, for example, by sputtering, the copper seed layer 15 is formed.
Is formed by depositing a copper film to a thickness of 100 nm, for example. The thickness of the copper seed layer 15 is not limited to 100 nm, but may be any thickness as long as it sufficiently covers the inner wall surface of the wiring groove 13.

Next, the inside of the wiring groove 13 is used as a first conductive film 16 by plating, for example, a copper film
It is deposited to a thickness of 00 nm and embedded. At this time, in the drawing, the narrow wiring grooves 13sa and 13sb are filled with the first conductive film 16, but the film thickness of the first conductive film 16 is reduced, and The wiring grooves 13sa and 13sb need not be completely buried. Subsequently, a second conductive film 17 is formed by depositing a copper film to a thickness of 1000 nm by sputtering.

Next, the second and first conductive films 17 and 1 made of copper formed on the interlayer insulating film 12 by CMP.
6. The copper seed layer 15 and the barrier metal layer made of tantalum nitride are removed. As a result, as shown in FIG. 1D, the wiring 18 is formed of copper buried via the barrier metal layer left in the wiring groove 13. The above C
As the MP, general copper CMP conditions were used, and a slurry containing alumina as a main material was used for the slurry. In FIG. 4D, the copper seed layer 15 was included in the first conductive film 16.

The step of forming the interlayer insulating film described with reference to FIG. 1A and the step of forming the wiring groove described with reference to FIG. 1B are performed so as to form a dual damascene structure. A wiring hole may be formed.

The first conductive film 16 may be any conductive material formed by a plating method. For example, nickel (Ni), chromium (Cr), gold (Au), silver (Ag), or the like is used. it can. The second conductive film 17 is made of tantalum (Ta), tantalum nitride (TaN), titanium nitride (Ti).
N), titanium nitride silicide (TiSiN), nickel (N
The same effect as copper can be obtained by using i), chromium (Cr), gold (Au), silver (Ag), aluminum (Al), tungsten (W), or the like. In addition, although CMP has been exemplified as polishing when removing the first and second conductive films 16 and 17 on the protrusions between the wiring grooves 13, for example, electrolytic polishing or another polishing method can be used. .

In the method of manufacturing a semiconductor device described with reference to FIG. 1, since the first conductive film 16 is buried in the wiring groove 13 by the plating method and then the second conductive film 17 is buried, the wiring groove is formed only by the plating method. The first conductive film 16 and the second conductive film 17 need not be formed to have a thickness obtained by adding the thickness of the first conductive film 16 to the thickness of the second conductive film 17 in consideration of an allowance to be removed by polishing. In this case, the film thickness may be a combination of the thickness of the wiring groove 13 and a marginal thickness.

Since the second conductive film 17 is formed by a sputtering method, a uniform film is formed regardless of the surface condition of the first conductive film 16 formed by plating. Therefore, the narrow wiring groove 1 before polishing is used.
On the region where the thickness th and the width of the wiring groove 13s having a small width are formed sparsely, including the first and second conductive films 16 and 17 including the copper seed layer 15 on the region where 3s is densely formed. Of the first and second conductive films 16 and 17 including the copper seed layer 15, that is, the thickness variation of the conductive film is suppressed. Therefore, overpolishing during polishing can be suppressed, and erosion and dishing are reduced.

Since the first conductive film 16 and the second conductive film 17 are formed of the same material, the thickness of the first conductive film 16 formed by plating is set to be equal to or less than the thickness of the wiring groove 13. Even in this case, there is an advantage that a wiring of a single material can be formed.
Also, sufficient adhesion between the first conductive film 16 and the second conductive film 17 can be obtained.

Since the first conductive film 16 is formed of copper, the wiring 18 has a low resistance. Further, even when the first conductive film 16 is formed of an alloy containing copper, the wiring 18 having a low resistance can be similarly formed.

Since the second conductive film 17 is formed by sputtering, there is an advantage that a high-purity film can be easily formed.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

As shown in FIG. 2A, an interlayer insulating film 12 is formed on a substrate 11 by, for example, a silicon oxide film having a thickness of 1000 nm.

Next, as shown in FIG. 2B, a wiring groove 13 is formed in the interlayer insulating film 12. This wiring groove 1
Reference numeral 3 denotes a small area in which narrow wiring grooves 13 (13sa) having a width of, for example, 0.2 μm are densely formed at a pitch of, for example, 0.4 μm, and a certain area has a width of, for example, 0.2 μm.
Wiring groove 13 (13 sb) is sparse, for example, 100 μm
The wiring grooves 13 (13w) having a width of, for example, 100 μm are formed in a certain region.

Next, as shown in FIG. 2C, a barrier metal layer (not shown) is formed on the inner wall of the wiring groove 13 and the interlayer insulating film 12 by, for example, sputtering to form a 30 nm thick tantalum nitride film. Formed on the surface. Further, for example, by sputtering, the copper seed layer 15 is formed.
Is formed by depositing a copper film to a thickness of 100 nm, for example.

Next, the inside of the wiring groove 13 is used as a first conductive film 16 by plating, for example, a copper film
It is deposited to a thickness of 00 nm and embedded. Subsequently, a second conductive film 17 is formed by depositing a copper film to a thickness of 800 nm by sputtering. It is desirable that the copper film formed here has a film thickness enough to fill the wide wiring groove 13w, but it is even better if the copper film is just filled because the stop film works effectively. In this embodiment, the thickness is set to 800 nm so that the wide wiring groove 13w is just filled.

Further, a polishing stop film 21 is formed on the second conductive film 17 by depositing a tantalum nitride film to a thickness of 30 nm by, for example, a sputtering method. The polishing stop film 21 may be any film having a polishing rate lower than that of copper, but any film that can be formed by sputtering.
As in the case of the tantalum nitride film used here, there is an advantage that the film can be formed using a sputtering apparatus used for sputtering copper. For example, a film such as a titanium nitride film or a tantalum film can be used. The polishing stop film 21 is formed of a conductive film, an inorganic insulating film [for example, silicon oxide (SiO ₂ ), silicon nitride (SiN)] in consideration of a polishing selectivity with the base, adhesion to the base, and polished properties. , Silicon carbide (SiC), silicon oxynitride (SiON), silicon oxyfluoride (SiOF), etc.], and organic insulating films (polyaryl ether resin, polytetrafluoroethylene resin, etc.). Can be.

Next, the polishing stop film 2 is formed by CMP.
1, and the second and first conductive films 17 and 16 made of copper formed on the interlayer insulating film 12, the copper seed layer 15, and the barrier metal layer made of tantalum nitride are removed. As a result, as shown in FIG. 2D, the wiring 18 is formed of copper buried via the barrier metal layer left in the wiring groove 13. In FIG. 4D, the copper seed layer 15
Was included in the first conductive film 16.

The above CMP is more effective than the polishing stop film 2 for copper.
No. 1 used a CMP condition in which the polishing rate was slower, and a slurry containing alumina as a main material was used for the slurry. As an example of the conditions, a general CMP apparatus is used for the polishing apparatus, urethane foam is used for the polishing pad, an alumina-based acidic slurry is used for the slurry, and the polishing pressure is 300 g / cm ^2. , The rotation speed of the polishing cloth is 60 rpm,
The rotational speed of the wafer was 60 rpm, and the polishing rate (the polishing rate for a solid film) was copper: tantalum nitride: silicon oxide =
500 nm / min: 5.0 nm / min: 20 nm /
min was obtained. The end point detection is of an optical type that detects the reflection intensity of laser light from the wafer surface.

The step of forming the interlayer insulating film described with reference to FIG. 2A and the step of forming the wiring groove described with reference to FIG. A damascene structure may be formed.

The first conductive film 16 may be a conductive material formed by a plating method, and may be made of the same material as the first conductive film described in the first embodiment. The same effect as copper can be obtained. Also, the wiring groove 13
Although CMP has been exemplified as polishing when the first and second conductive films 16 and 17 on the surrounding substrate 11 are removed, for example, electrolytic polishing or another polishing method can be used.

In the method for manufacturing a semiconductor device described with reference to FIG. 2, the first conductive film 16 is buried in the wiring groove 13 by the plating method and then the second conductive film 17 is buried. The first conductive film 16 and the second conductive film 17 need not be formed to have a thickness obtained by adding the thickness of the first conductive film 16 to the thickness of the second conductive film 17 in consideration of an allowance to be removed by polishing. In this case, the film thickness may be a combination of the thickness of the wiring groove 13 and a marginal thickness.

Since the second conductive film 17 is formed by a sputtering method, a uniform film is formed regardless of the surface condition of the first conductive film 16 formed by plating. Therefore, the narrow wiring groove 1 before polishing is used.
The thickness th and the width of the wiring groove 13s having a small width and the combined thickness of the first and second conductive films 16 and 17 on the region where 3s is densely formed
Of the first and second conductive films 1 on a region where
The difference from the film thickness tl obtained by adding the thicknesses 6 and 17, that is, the thickness variation of the conductive film is suppressed. Therefore, overpolishing during polishing can be suppressed, and erosion and dishing are reduced.

As shown in FIG. 3A, the second conductive film 17 has a depression 17h on the wide wiring groove 13w due to the characteristic of film formation by sputtering. Second conductive film 17 formed in such a shape
Since the polishing stop film 21 is formed thereon, the polishing stop layer 21 is also formed at the bottom of the recess 17h.

When the above polishing is performed in such a state, the uppermost polishing stop layer 21 is mainly polished at first, and when the uppermost polishing stop layer 21 is removed, the second conductive film 1 is removed.
7 is mainly polished. As this polishing progresses, FIG.
As shown in (2), the polishing rate eventually decreases on the polishing stop layer 21 formed at the bottom of the recess 17h. By further polishing in this state, the polishing rate is once suppressed by the polishing stop layer 21 on the wiring groove 13w, and polishing proceeds in other regions.
Eventually, the polishing stop layer 21 on the wiring groove 13w is also removed. Then, as shown in FIG. 3C, the interlayer insulating film 12 is formed.
The top surface is exposed. At this time, over-polishing is performed so that the uppermost surface of the interlayer insulating film 12 is completely exposed. In this overpolishing, the first insulating film 12 in the interlayer insulating film 12 and the wiring groove 13 is removed.
The upper portions of the second conductive layers 16 and 17 are polished, and the polishing stop layer 21 (see FIG. 3) remaining on the wiring grooves 13w is completely removed by polishing. In addition,
In FIG. 3, the copper seed layer 15 (see FIG. 2) is included in the first conductive film 16.

Even if the above-mentioned over-polishing is performed, the wiring groove 1w is not removed by the polishing stop layer 21 on the wide wiring groove 13w.
Dishing hardly occurs in the first and second conductive films 16 and 17 within 3w. Thus, the polishing stop layer 21
The second conductive film 17 in the wide wiring groove 13w
Dishing is suppressed.

Since the first conductive film 16 and the second conductive film 17 are formed of the same material, the thickness of the first conductive film 16 formed by plating is set to be equal to or less than the thickness of the wiring groove 13. Even in this case, there is an advantage that a wiring of a single material can be formed.
Also, sufficient adhesion between the first conductive film 16 and the second conductive film 17 can be obtained.

Since the first conductive film 16 is made of copper, the wiring 18 has a low resistance. Further, even when the first conductive film 16 is formed of an alloy containing copper, the wiring 18 having a low resistance can be similarly formed.

Since the second conductive film 17 is formed by sputtering, there is an advantage that a high-purity film can be easily formed.

Next, a comparative example will be described with reference to a cross-sectional view of a manufacturing process shown in FIG. As shown in FIG. 4 (1), an interlayer insulating film 12 is formed on a substrate 11 in the same manner as described with reference to FIG. 1 (1) to (3). As shown, a wiring groove 13 similar to that of the first embodiment is formed in the interlayer insulating film 12.

Next, as shown in FIG. 4C, similarly to the first embodiment, a barrier metal layer (not shown) is formed on the inner wall of the wiring groove 13 and on the interlayer insulating film 12, for example. 30 nm tantalum nitride film by sputtering
And formed to a thickness of Further, for example, by sputtering, the copper seed layer 15 is
It is formed by depositing to a thickness of m. Furthermore, by plating method,
For example, a copper film is deposited and buried to a thickness of, for example, 1100 nm using the inside of the wiring groove 13 as the conductive film 26.

Then, a conductive film 26 made of copper, a copper seed layer 15 and a barrier metal layer made of tantalum nitride (not shown) formed on the interlayer insulating film 12 by CMP.
Is removed. As a result, as shown in (4) of FIG. 4, the wiring 28 is formed of copper buried via the barrier metal layer (not shown) left in the wiring groove 13,
Erosion and dishing occurred significantly. In the CMP, general copper CMP conditions were used, and a slurry containing alumina as a main material was used for the slurry. (4)
In the drawing, the copper seed layer 15 (see FIG. 2) is included in the conductive film 26.

The thickness of the copper film on the insulating film after the copper film was formed, dishing after CMP, erosion, etc., of the samples manufactured in the embodiment described with reference to FIGS. 1 and 2 and the comparative example. Is shown in Table 1 for each pattern of the concave portions. All patterns in Table 1 are line and space (L & S).
Represents a line, and S represents a space. That is, a pattern in which a similar pattern was repeatedly formed in a 3 mm square was used. The thickness of the copper film was 3 m by taking a photograph of a cross section of the central part of a 3 mm square with a scanning electron microscope.
The thickness of the copper film on the tantalum nitride film at the center of the m-square (the thickness of the copper seed layer + the thickness of the plating layer + the thickness of the sputtered layer) was measured.

[0055]

[Table 1]

Note that dishing and erosion in Table 1 were measured from an SEM photograph of a section taken with the height of the oxide film surface in a region where the existing density of wiring grooves was 0% as 0. As can be seen from Table 1, for example, 0.3 μm
Under the L & S condition of m, the dishing was 0 nm and the erosion was 20 nm in the first and second embodiments. In the comparative example formed by the conventional technique, the dishing was 0 nm, but the erosion was 30 nm. Further, under the L & S condition of 10 μm, the first and second
In the embodiment, the dishing was 10 nm and the erosion was 20 nm. In the comparative example formed by the conventional technique, the dishing was 20 nm, but the erosion was 50 nm. Thus, it was found that under the same L & S conditions, according to the manufacturing method of the present invention, both dishing and erosion were improved.

[0057]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the first conductive film is formed by plating, and the second conductive film is formed by sputtering or chemical vapor deposition. Since variation in thickness of the conductive film embedded in the wiring groove before polishing can be suppressed, overpolishing during polishing can be suppressed. Therefore, dishing and erosion can be reduced, so that a trench wiring with low resistance and high reliability can be formed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view showing a first embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process according to a second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a manufacturing process sectional view showing the operation of a polishing stop layer.

FIG. 4 is a manufacturing process sectional view showing a comparative example.

FIG. 5 is a sectional view showing a manufacturing process for explaining a method for manufacturing a copper dual damascene structure.

FIG. 6 is a manufacturing process sectional view showing a manufacturing method for forming a stacked structure of a tungsten damascene structure and a copper damascene structure.

[Explanation of symbols]

11: substrate, 13: wiring groove (recess), 16: first conductive film, 17: second conductive film, 18: wiring

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (4)

[Claims] A step of forming a first conductive film so as to bury at least a part of the concave portion on a substrate surface having the concave portion by plating, and burying all of the concave portion on the first conductive film. Forming a second conductive film on the substrate, removing the second conductive film and the first conductive film on the substrate around the concave portion, and removing the first conductive film and the first conductive film embedded in the concave portion. Forming a wiring with the second conductive film. 2. The method according to claim 1, further comprising, after the step of forming the second conductive film, a step of forming a polishing stop film having a lower polishing rate than the second conductive film on the second conductive film; The step of removing the second conductive film and the first conductive film on the surrounding substrate is performed in a state where the polishing stop film is left at the bottom of the depression formed in the second conductive film on the concave portion. After removing the polishing stop film and the second conductive film around the recess by the above, the second conductive film and the first conductive film on the polishing stop film left at the bottom of the recess and the substrate around the concave portion 2. The method according to claim 1, wherein the film is removed. 3. The method according to claim 1, wherein the second conductive film is formed of the same material as the first conductive film. 4. The method according to claim 2, wherein the second conductive film is formed of the same material as the first conductive film.