CN100372098C

CN100372098C - Method of manufacturing a semiconductor device and semiconductor device

Info

Publication number: CN100372098C
Application number: CNB2005100748244A
Authority: CN
Inventors: 森田敏行; 丰田启; 松井嘉孝; 池谷文敏; 坂田敦子; 坚田富夫; 尾本诚一
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2004-06-04
Filing date: 2005-06-03
Publication date: 2008-02-27
Anticipated expiration: 2025-06-03
Also published as: CN1707772A

Abstract

According to one aspect of the present invention, provided is a method of manufacturing a semiconductor device, including: forming a first metal film on a substrate having a recessed portion in a surface thereof, by a plating method so as to bury the first metal film in at least part of the recessed portion; forming a second metal film on the first metal film by a film deposition method different from the plating method, the second metal film including, as a main component, a metal that is a main component of the first metal film and containing an impurity whose concentration is lower than concentration of an impurity contained in the first metal film; heat-treating the first and second metal films; and removing the first and second metal films except portions buried in the recessed portion.

Description

The manufacture method of semiconductor device and semiconductor device

The cross reference of related application

The application based on and require the preference of the 2004-167763 of Japanese patent application formerly that submitted on July 4th, 2004; Be incorporated herein its full content as a reference.

Technical field

The present invention relates to the manufacture method and the semiconductor device of semiconductor device.

Background technology

As the material of wiring semiconductor device, bring into use Cu to replace Al recently, with reduction cloth line resistance, and improve anti-transfer ability, for example electromigration of described migration (EM) and the stress migration (SM) that may lead to errors and connect up.

Be different from Al, Cu is difficult to handle by RIE (reactive ion etching).Therefore, in order to form wiring, use method for embedding with Cu, wherein, in the dielectric film surface, form groove or hole earlier, on dielectric film, form the Cu film then, Cu is imbedded groove or hole, do not need part by what CMP (chemico-mechanical polishing) removed the Cu film subsequently, thereby form wiring.

For the method that in method for embedding, forms the Cu film, use to allow the electro-plating method of the deposition of (bottom-up) from bottom to top.In the used here electroplating solution, three kinds of additives of mix predetermined quantities, i.e. catalyst, inhibitor and smoothing agent (leveler), and the effect of described additive has realized deposition from bottom to top.

Yet,, in the Cu film, sneaked into impurity if additive is blended in the electroplating solution.This problem is relevant to the deposition velocity of film, in being difficult to take place the wide wiring groove of deposition from bottom to top than in the narrow wiring groove that deposition from bottom to top significantly takes place, having mixed more impurity.Because the impurity in the wide wiring groove will become the factor that causes defective, therefore need to reduce the method for impurity.

Summary of the invention

According to an aspect of the present invention, the method of making semiconductor device is provided, described method comprises: have in its surface by electro-plating method and form first metal film on the substrate of groove part, with described first metal film is imbedded described groove part to small part; On described first metal film, form second metal film by the film deposition method that is different from described electro-plating method, described second metal film comprises as the metal of main component and comprises impurity, described metal is the main component of described first metal film, and the concentration of described impurity is lower than the concentration of the impurity that comprises in described first metal film; Described first and second metal films of heat treatment; And after described heat treatment, remove described first and second metal films the part in imbedding described groove.

According to another aspect of the present invention, the method of making semiconductor device is provided, described method comprises: in the electroplating solution that has in its surface in the substrate immersion plating solution pool of groove part, and when rotating described substrate with 50rpm or lower rotary speed, with 15L/ minute or higher feed speed described electroplating solution is supplied in the described electroplating solution pond, thereby on described substrate, form metal film by electro-plating method, thereby to small part, imbed described metal film at described groove part; And remove described metal film the part in imbedding described groove part.

According to another aspect of the present invention, provide a kind of semiconductor device, described device comprises: substrate; Dielectric film forms on described substrate and has first groove part and at same lip-deep second groove part; First wiring is embedded in described first groove part and has 0.3 μ m or littler live width; And second wiring, be embedded in described second groove part and have live width, and comprise concentration is lower than the impurity concentration that comprises in described first wiring impurity greater than 0.3 μ m.

Description of drawings

Fig. 1 is the flow chart that illustrates according to the flow process of the manufacture method of the semiconductor device of first embodiment;

Fig. 2 A to Fig. 2 H diagram shows the manufacture method according to the semiconductor device of first embodiment;

Fig. 3 is the flow chart that illustrates according to the flow process of the manufacture method of the semiconductor device of second embodiment;

Fig. 4 diagram shows the manufacture method according to the semiconductor device of second embodiment;

Fig. 5 diagram shows the formation method according to the electroplating film of second embodiment;

Fig. 6 illustrates when when supplying with electroplating solution and electroplate with 15L/ minute or higher feed speed in 50rpm or lower rotary speed rotation wafer, the concentration of Cu ion and additive and curve chart to the relation of the distance of wafer surface;

Fig. 7 illustrates when when supplying with electroplating solution and electroplate with 15L/ minute or higher feed speed in the rotary speed of about 100rpm rotation wafer, the concentration of Cu ion and additive and curve chart to the relation of the distance of wafer surface;

Fig. 8 illustrates when when supplying with electroplating solution and electroplate with the feed speed that is lower than 15L/ minute in 50rpm or lower rotary speed rotation wafer, the concentration of Cu ion and additive and curve chart to the relation of the distance of wafer surface;

Fig. 9 is the curve chart that illustrates according to the wafer rotary speed and the relation between the defect concentration of experiment embodiment 2;

Figure 10 A to Figure 10 N diagram shows the manufacture method according to the semiconductor device of the 3rd embodiment;

Figure 11 A diagram shows according to the 3rd embodiment, when the main component of wide wiring is Cu and barrier metal film when being made of Ti, and the interface state between wide wiring and barrier metal film; And Figure 11 B diagram to show main component when wide wiring be Cu and barrier metal film when being made of Ta, the interface state between wide wiring and barrier metal film.

Embodiment

(first embodiment)

Below first embodiment will be described.Fig. 1 is the flow chart that illustrates according to the flow process of the manufacture method of the semiconductor device of this embodiment, and Fig. 2 A to Fig. 2 H diagram shows the manufacture method according to the semiconductor device of this embodiment.

Shown in Fig. 2 A, by for example chemical vapor deposition (CVD) or be coated in semiconductor wafer W (below abbreviate " wafer " as) and go up and form interlayer dielectric 1 (step 1a).The examples of materials that constitutes interlayer dielectric 1 is the insulating film with low dielectric constant as organic Si oxidation film, organic resin film and porous Si oxidation film, SiO ₂Film etc.

After forming interlayer dielectric 1, shown in Fig. 2 B, in interlayer dielectric 1, form each wide 0.3 μ m or narrow wiring groove 1A still less and each by photoetching technique and reactive ion etching (RIE) and be wider than the wide wiring groove 1B (step 2a) of 0.3 μ m.In order to form narrow wiring groove 1A and wide wiring groove 1B, when the rotation wafer W, on interlayer dielectric 1, apply anti-reflection film and chemically-amplified resist.After applying photoresist, utilize the mask that is formed with predetermined pattern thereon to expose by ultraviolet light.Then, develop, thereby on interlayer dielectric 1, form the resist figure with developing solution.When after forming the resist figure on the interlayer dielectric 1, utilize mask to pass through RIE etching interlayer dielectric 1, thereby in interlayer dielectric 1, form narrow wiring groove 1A and wide wiring groove 1B as the resist figure.After in interlayer dielectric 1, forming narrow wiring groove 1A and wide wiring groove 1B, remove resist and anti-reflection film by ashing or similar processing.

After in interlayer dielectric 1, forming narrow wiring groove 1A and wide wiring groove 1B, shown in Fig. 2 C, on interlayer dielectric 1, form barrier metal film 2 by for example sputter or CVD, go into interlayer dielectric 1 (step 3a) to suppress metal diffusing.The examples of materials that constitutes barrier metal film 2 is the electric conducting material as Ta, Ti, TaN, TiN, NbN, WN and VN.Barrier metal film 2 can be formed by the lamination of these materials.

When after forming barrier metal film 2 on the interlayer dielectric 1, shown in Fig. 2 D, form seed crystal film 3 on the barrier metal film 2 by for example sputtering at, with when the metallide by electric current (step 4a).The examples of materials that constitutes seed crystal film 3 is the metal of Cu for example.

When after forming seed crystal film 3 on the barrier metal film 2, electroplating solution is supplied on the surface of seed crystal film 3, and provide electric current to the seed crystal film simultaneously, thereby shown in Fig. 2 E, on seed crystal film 3, form electroplating film (first metal film) 4 (step 5a) by electroplating.In electroplating solution, except that the metal ion of for example Cu ion, go back the additive of mix predetermined quantities, for example catalyst, inhibitor and smoothing agent.And, form electroplating film 4 like this, it is imbedded among whole each narrow wiring groove 1A that deposition from bottom to top wherein takes place easily and part wherein is difficult to take place among each wide wiring groove 1B of deposition from bottom to top.Electroplating film 4 mainly is made of the metal of for example Cu, but wherein is mixed with impurity.Here " impurity " refers to contain at least a material in the following material: S, Cl, O, C and N.

When after forming electroplating film 4 on the seed crystal film 3, shown in Fig. 2 F, by for example sputter, forming thickness on electroplating film 4 is sputtered film (second metal film) 5 (the step 6a) of for example about 500nm.Sputtered film 5 can form in high vacuum and Ar gas by utilizing highly purified target.Form sputtered film 5 like this with in the other parts of imbedding each wide wiring groove 1B.The main component of sputtered film 5 is metals identical with the main component metal of electroplating film 4.

The concentration of the impurity in the sputtered film 5 (below be called " impurity concentration ") is lower than the impurity concentration in the electroplating film 4.Here, the impurity concentration that impurity concentration in the sputtered film 5 is lower than in the electroplating film 4 represents, the concentration that has the composition of maximum concentration in sputtered film 5 at least a among S, Cl, O, C and the N that exists is lower than the concentration that has the composition of maximum concentration in electroplating film 4 at least a among S, Cl, O, C and the N that exists.Can measure impurity concentration by for example ion microprobe (SIMS).The concentration that has the composition of maximum concentration in sputtered film 5 at least a among S, Cl, O, C and the N that exists is preferably 1.00 * 10 ¹⁷Atom/cm ³Or it is lower.

Described method in addition, in this embodiment, forms sputtered film 5, but can use any film deposition method to replace sputter, as long as can form the impurity concentration film lower than electroplating film 4 by sputter.The example of such film deposition method is CVD.

When after forming sputtered film 5 on the electroplating film 4, the heat treatment wafer W with the crystal of growth seed crystal film 3, electroplating film 4 and sputtered film 5, thereby forms wiring membrane 6 (step 7a) shown in Fig. 2 G.Here, when the heat treatment wafer W, the diffusion of impurities in the electroplating film 4 enters sputtered film 5 to become even.For example under 150 ℃ to 300 ℃, carry out 30 seconds to 60 minutes heat treatment.

After the heat treatment wafer W, carry out for example chemico-mechanical polishing (CMP), with shown in Fig. 2 H, that removes barrier metal film 2 on interlayer dielectric 1 and wiring membrane 6 does not need part, and stays barrier metal film 2 and wiring membrane 6 (step 8a) in narrow wiring groove 1A and wide wiring groove 1B.Especially, under the situation of wafer W contact polished silicon wafer, when rotation wafer W and polished silicon wafer (not shown), the slurries (not shown) is supplied on the wafer W.Thereby, polishing wiring membrane 6 etc.This finishing method is not limited to CMP, but can use other method.The example of other method is an electrobrightening.

By these methods, the live width that has formed each is 0.3 μ m or littler narrow wiring (first wiring) 6A and the live width of each wide wiring (second wiring) 6B greater than 0.3 μ m.At this moment, the impurity concentration in the wide wiring 6B that obtains is lower than the impurity concentration in narrow wiring 6A.This is because wide wiring 6B is formed than electroplating film 4 low sputtered film 5 by seed crystal film 2, electroplating film 4 and impurity concentration, and narrow wiring 6A is formed by seed crystal film 2 and electroplating film 4.

Here, for narrow wiring 6A and wide wiring 6B impurity concentration separately, the impurity concentration among the preferred narrow wiring 6A is substantially 5 * 10 ¹⁸Atom/cm ³To 1 * 10 ¹⁹Atom/cm ³Scope in, and the impurity concentration among the wide wiring 6B is being lower than about 5 * 10 substantially ¹⁸Atom/cm ³Scope in.That is to say, if the impurity concentration in narrow wiring 6A is too low, fixing (pinning) in the hole in the wiring that is caused by impurity will be very undesirable, and, depart from above-mentioned scope separately if the impurity concentration among narrow wiring 6A and the wide wiring 6B is too high, with the defective that more may take place to cause owing to accumulation of impurities.In this embodiment, for example, preferably, the live width of each is not less than 0.05 μ m and is not higher than 0.3 μ m and the impurity concentration that wherein takes place easily among the narrow wiring 6A of deposition from bottom to top is set to 5 * 10 when electroplating film deposits ¹⁸Atom/cm ³To 1 * 10 ¹⁹Atom/cm ³, the live width of each is greater than 0.3 μ m and be not more than 10 μ m and be set to be lower than 5 * 10 with impurity concentration that narrow wiring 6A is formed among the same lip-deep wide wiring 6B ¹⁸Atom/cm ³The impurity concentration here can be defined as the concentration of the composition at least a among S, Cl, O, C and the N that in each narrow wiring 6A and wide wiring 6B, exists with maximum concentration.

According to this embodiment, can reduce the impurity concentration among the wide wiring groove 1B, this can make the wide wiring 6B of formation have the number of defects of minimizing.The existence of impurity causes the possible cause of defective as follows among the wide wiring groove 1B.Specifically be, taking place easily among the narrow wiring groove 1A of deposition from bottom to top, even excessive additive is supplied to wherein, because the bigger film deposition velocity of electroplating film 4, can not form higher impurity concentration, but be difficult to therein take place among the wide wiring groove 1B of deposition from bottom to top, the too much supply of additive has increased impurity concentration.According to the progress of the crystal growth in heat treatment process, think that this part in the accumulation of impurities of wide wiring groove 1B has caused the generation of defective.

In this embodiment, because form the impurity concentration sputtered film 5 lower than electroplating film 4 on electroplating film 4, in heat treatment process, the impurity in the electroplating film 4 may be diffused in the sputtered film 5.This can reduce the impurity concentration among the wide wiring groove 1B, so that the wide wiring 6B that forms has the number of defects of minimizing, thereby can provide the wiring reliability improved semiconductor device.

And, according to this embodiment, electroplating film 4 is formed in the part of imbedding each wide wiring groove 1B, and subsequently sputtered film 5 is formed in the other parts of imbedding wide wiring groove 1B, this can reduce impurity among the wide wiring groove 1B than situation among the whole wide wiring groove 1B that electroplating film 4 is imbedded.This feasible wide wiring 6B that can form number of defects with minimizing.

And according to this embodiment, the width of each narrow wiring groove 1A is 0.3 μ m or littler, and electroplating film 4 is embedded among the whole narrow wiring groove 1A, and this has guaranteed by deposition from bottom to top electroplating film 4 to be imbedded among the narrow wiring groove 1A.Note, think that at width be the deposition that takes place easily in 0.3 μ m or the littler groove from bottom to top.And in so narrow wiring 6A, the progress of crystal growth is limited to the width of narrow wiring groove 1A or littler, thereby the defective that causes owing to accumulation of impurities in crystal growth will still less take place possibly.

In addition, according to this embodiment, move in narrow wiring 6A to prevent the hole in the feasible hole that can fix among the narrow wiring 6A of the impurity of the specified quantitative that exists in narrow wiring 6A.This can be suppressed at the big space of generation in the wiring, and it may cause cloth thread breakage or resistance to increase, thereby can provide the wiring reliability improved semiconductor device.

(experiment embodiment 1)

Below experiment embodiment 1 will be described.

In this experiment embodiment, measured the impurity concentration in the Cu film, and measured the defect concentration in the Cu wiring.

In this experiment embodiment, used the wafer that forms by following method.After formation thickness is the oxide-film of 20nm on the Si substrate that has active part at each, form the SiOC base insulating film with low dielectric constant (interlayer dielectric) that thickness is 300nm by CVD.Then, the width that forms each by photoetching process and RIE technology is that 4 μ m, the degree of depth are the wiring groove (wide wiring groove) of 250nm.Then, after removing resist, by long Ta film (barrier metal film) and the Cu film (seed crystal film) that is respectively 30nm and 80nm that form apart from sputter by wet etching process.Then, form the Cu film by two kinds of film deposition methods.In condition 1, forming thickness by metallide under the current condition of 1A/ wafer is the Cu film (electroplating film) of 210nm.In addition, in condition 2, forming thickness by metallide under the current condition of 1A/ wafer is the Cu film (electroplating film) of 10nm, and then, forming thickness by length apart from sputter is the Cu film (sputtered film) of 200nm.Then, be in the formation gas of about 10 volume % at density of hydrogen, under 270 ℃, these wafers are carried out 40 minutes heat treatment, and subsequently, do not need part by what CMP removed Cu film etc., thereby form the Cu wiring.

Then, utilize these wafers to measure the impurity concentration in each Cu film and measure defect concentration in each Cu wiring.In the measurement of impurity concentration, removing not the needing before the part of Cu film etc. by CMP, use CIMS to measure Cl, O in the Cu film and the concentration of C.In the measurement of defect concentration, use defect detector to measure the defect concentration of each Cu wiring.

Below the result will be discussed.Table 1 shows the defect concentration in impurity concentration in

condition

1 and 2 times Cu films of condition and the Cu wiring.

[table 1]

	Condition 1	Condition 2
	Condition 1	Condition 2	Cl impurity concentration (atom/cm ³)	1.00×10 ¹⁹	1.30×10 ¹⁶
O impurity concentration (atom/cm ³)	2.00×10 ¹⁹	5.00×10 ¹⁵	Cl impurity concentration (atom/cm ³)	1.00×10 ¹⁹	1.30×10 ¹⁶
O impurity concentration (atom/cm ³)	2.00×10 ¹⁹	5.00×10 ¹⁵	C impurity concentration (atom/cm ³)	1.50×10 ¹⁹	1.50×10 ¹⁶
Defect concentration	1500	2	C impurity concentration (atom/cm ³)	1.50×10 ¹⁹	1.50×10 ¹⁶

As shown in table 1, than the condition of general condition 1 time, the impurity concentration in the Cu film under condition 2 has reduced near about 3 figure places.Therefore, greatly reduced defect concentration in the Cu wiring.Can determine from these results, form the Cu film by sputter, realize reducing the impurity concentration in the Cu film and reduced defect concentration in the Cu wiring by after electroplate forming the Cu film.In addition, in this experiment embodiment, the Cu wiring has been described, if but on Ag electroplating film and Au electroplating film, form Ag sputtered film and Au sputtered film etc. respectively, then in Ag wiring and Au wiring, can obtain same effect.

(second embodiment)

Below second embodiment will be described.This embodiment will describe such example, wherein by in 50rpm or lower rotary speed rotation wafer, supply with electroplating solution and will form electroplating film with 15L/ minute or higher feed speed.Some will be omitted with content identical in first embodiment.

Fig. 3 is the flow chart that illustrates according to the flow process of the manufacture method of the semiconductor device of this embodiment, Fig. 4 diagram shows the manufacture method according to the semiconductor device of this embodiment, Fig. 5 diagram shows the formation method according to the electroplating film of this embodiment, Fig. 6 shows when when supplying with electroplating solution and electroplate with 15L/ minute or higher feed speed in 50rpm or lower rotary speed rotation wafer, the concentration of Cu ion and additive and relation to the distance of wafer surface, Fig. 7 shows when when supplying with electroplating solution and electroplate with 15L/ minute or higher feed speed in the rotary speed of about 100rpm rotation wafer, the concentration of Cu ion and additive and relation to the distance of wafer surface, and Fig. 8 shows when when supplying with electroplating solution and electroplate with the feed speed that is lower than 15L/ minute in 50rpm or lower rotary speed rotation wafer, the concentration of Cu ion and additive and relation to the distance of wafer surface.

As shown in Figure 3, on wafer W, form interlayer dielectric 1 (step 1b).After forming interlayer dielectric 1, in interlayer dielectric 1, form narrow wiring groove 1A and wide wiring groove 1B (step 2b) by photoetching technique and reactive ion etching (RIE).

After in interlayer dielectric 1, forming narrow wiring groove 1A and wide wiring groove 1B, on interlayer dielectric 1, form barrier metal film 2 (step 3b).When after forming barrier metal film 2 on the interlayer dielectric 1, on barrier metal film 2, form seed crystal film 3 (step 4b).

When after forming seed crystal film 3 on the barrier metal film 2, electroplating solution is supplied on the surface of seed crystal film 3, thereby as shown in Figure 4, form electroplating film 4 (step 5b) by metallide.In this embodiment, electroplating film 4 is formed imbed among whole each narrow wiring groove 1A and whole each wide wiring groove 1B.

As shown in Figure 5, in order to form electroplating film 4 that wafer W is fixing by fixture 10, and seed crystal film 3 is set on lower surface, between wafer W that is used as negative electrode and anode 11, apply voltage.Then, wafer W is tilted and be immersed in the electroplating solution pond in the electroplating solution with 15L/ minute or higher feed speed jet flow.At this moment, preferably rotate wafer W, preventing bubble adhesion on wafer surface, if but can wait the adhesion that prevents bubble by the immersion method of some particular design, can be not rotatably in the immersion plating solution with wafer W.

Subsequently, in the time of in wafer W immersion plating solution, the feed speed of electroplating solution and the rotary speed of wafer W were remained on respectively 15L/ minute or higher and 50rpm or lower.Thereby, electroplating film 4 formed imbeds among narrow wiring groove 1A and the wide wiring groove 1B.Here, the rotary speed of wafer W need not remain unchanged in the process of whole electroplating film deposition, but can change in 50rpm or lower scope, and perhaps the rotation of wafer W will be stopped temporarily.That is to say, only need like this, when imbed with electroplating film 4 each narrow wiring groove 1A and wide wiring groove 1B to small part the time, supply with the electroplating solution that is used to electroplate with 15L/ minute or higher feed speed, rotate wafer W with 50rpm or lower speed simultaneously.In addition, can be used for extracting the pump 13 of electroplating solution out or be used for providing the flowmeter (not shown) of the supply pipe 14 etc. of the electroplating solution of being extracted out by pump 13 to measure the feed speed of electroplating solution by being installed in to electroplating solution pond 12.

This embodiment uses so-called hot access method, wherein immerses wafer W when applying voltage, thereby begins to electroplate from the part that immerses.Therefore, when wafer W was dipped into, its rotary speed also was preferably 50rpm or lower.It has been generally acknowledged that, when wafer W is rotated under low rotary speed, if wafer W contact plating solution will form bubble on the surface of wafer W, and the surface uniformity of destruction electroplating film 4.Yet our experiment illustrates, and when when being higher than 0rpm and rotating wafer W smaller or equal to the rotary speed of 50rpm, even wafer W contacts with electroplating solution, still can suppress the formation of bubble.Therefore, can prevent destruction to the surface uniformity of electroplating film 4.

When after forming electroplating film 4 on the seed crystal film 3, the heat treatment wafer W is with the crystal of growth seed crystal film 3 and electroplating film 4, thus formation wiring membrane 6 (step 6b).

After forming wiring membrane 6, polish by for example CMP, stay barrier metal film 2 and wiring membrane 6 (step 7b) in narrow wiring groove 1A and wide wiring groove 1B with the unwanted part of removing barrier metal film 2 on interlayer dielectric 1 and wiring membrane 6.By these technology, the live width that has formed each is 0.3 μ m or lower narrow wiring 6A and the live width of each the wide wiring 6B greater than 0.3 μ m.

According to this embodiment, can reduce the impurity concentration among the wide wiring groove 1B, thereby can form the wide wiring 6B that number of defects reduces.In addition, can obtain the effect of additive, thereby can imbed electroplating film 4 from bottom to top by being deposited among the narrow wiring groove 1A.Especially, when the rotation wafer W, on the surface of wafer W, form diffusion layer.The thickness of diffusion layer is expressed by following Levich formula (1) about rotation electrode.

δ＝1.61D ₀ ^1/3υ ^1/6ω ^-1/2(1)

Here, D ₀Be diffusion coefficient, υ is the viscosity coefficient of solution, and ω is an angular speed.This formula shows, and the rotary speed of wafer is low more, and then the thickness δ of diffusion layer is big more.

At initial stage electroplating, current density is adjusted to about 10mA/cm ²To guarantee the buried regions character of minimum feature.Under this condition, the Cu ion in the electroplating solution exists with the amount of abundance, thereby and be in the decision reaction speed state.Thereby, think the concentration (Cu ion concentration) of Cu ion also substantially constant in diffusion layer.On the other hand, show effect when having only additive to be a small amount of, thus the concentration of the additive in the electroplating solution (additive concentration) much smaller than the concentration of Cu ion, and additive is in the state of decision diffusion velocity on the surface of wafer W.Therefore, can think that the additive concentration in the diffusion layer shows the concentration gradient of substantially linear.

As shown in Figure 7, when the rotary speed of wafer W during for about 100rpm, the thickness of diffusion layer becomes littler, thereby in the additive concentration increase of the near surface of wafer W, this causes the high impurity concentration in the electroplating film 4.On the other hand, shown in Fig. 6 and 8, when the rotary speed of wafer W is 50rpm or when lower, it is big that the thickness of diffusion layer becomes, thereby at the additive concentration step-down of the near surface of wafer W.Therefore, reduce the amount of the additive that enters electroplating film 4, thereby reduced the impurity concentration of electroplating film 4.Therefore, can form the wide wiring 6B that number of defects reduces.

Yet, when the feed speed of electroplating solution is lower than 15L/ minute, has increased additive in the electroplating solution in electroplating solution pond 12 in the lip-deep adhesiveness of wafer W, thereby reduced the outer additive concentration of diffusion layer, as shown in Figure 8.As a result, becoming at the lip-deep additive concentration of wafer W is lower than requirement, thereby can not obtain the effect of additive.On the other hand, when supplying with electroplating solution with 15L/ minute or higher feed speed, additive becomes the state that is in decision diffusion velocity in the diffusion layer, thereby the additive concentration outside diffusion layer can keep constant substantially, as shown in Figure 6.Therefore, can obtain the effect of additive, thereby can electroplating film 4 be imbedded narrow wiring groove 1A by deposition from bottom to top.

(experiment embodiment 2)

Below experiment embodiment 2 will be described.In this experiment embodiment, measured the defect concentration of narrow wiring and wide wiring, and carried out the reliability testing of wide wiring.In addition, observed when wafer contacts with electroplating solution the state of wafer surface.

In this experiment embodiment, the wafer that has prepared a plurality of 300mm by the process of describing in a second embodiment, narrow linewidth that its live width with each is 0.09 μ m and the live width of each are the wide live width of 0.5 μ m, and measured the narrow wiring of each wafer and the defect concentration of wide wiring, and carried out the reliability testing of wide wiring.Here, form each electroplating film under such condition, wherein, the feed speed of electroplating solution is set to 20L/ minute, and with different rotary speed rotation wafers.In addition, when forming electroplating film, when wafer is contacted with electroplating solution, the surface state of observing each wafer.

The result is discussed below.Fig. 9 is the curve chart that illustrates according to the wafer rotary speed and the relation between the defect concentration of experiment embodiment 2.As shown in Figure 9,, also do not change the defect concentration in the narrow wiring substantially, but in wide wiring, defect concentration reduces along with the reduction of the rotary speed of wafer even change the rotary speed of wafer.Can determine that from these results the rotary speed of wafer does not influence narrow wiring substantially, but for the preferred lower wafer rotary speed of wide wiring.In addition, in to the reliability testing of wide wiring, can also determine especially preferred lower wafer rotary speed.

In addition, for the surface state of wafer when the contact plating solution, do not form bubble substantially.Can determine from these results,,, but suppress destruction the surface uniformity of electroplating film even with wafer contact plating solution when with greater than 0rpm during smaller or equal to the rotary speed of 50rpm rotation wafer.

(the 3rd embodiment)

Below the 3rd embodiment will be described.This embodiment will describe such example, wherein form barrier metal film by the metal that belongs to one of 2A family, 4A family, 5A family, 6A family and 2B family, and described metal can form reactant with the metal as the main component of electroplating film.Some contents identical with first embodiment will be omitted.

Figure 10 A to 10N diagram shows the manufacture method according to the semiconductor device of this embodiment.Figure 11 A diagram shows according to the 3rd embodiment, when the main component of wide wiring is that Cu and barrier metal film are when being made of Ti, interface state between wide wiring and barrier metal film, and Figure 11 B diagram to show main component when wide wiring be Cu and barrier metal film when being made of Ta, the interface state between wide wiring and barrier metal film.

Shown in Figure 10 A, at the SiO of lower electrode with unshowned exposure ₂ Form interlayer dielectric 22 on the film 21.In this embodiment, interlayer dielectric 22 is by be poly (arylene ether) film 23 of organic low dielectric constant dielectric film (below be called " PAE film ") and the SiO that forms on PAE film 23 ₂ Film 24 constitutes.SiO ₂Film 24 is also as the diaphragm among the CMP.In addition, in this embodiment, use PAE film 23 and SiO ₂Film 24 is as interlayer dielectric 22, but interlayer dielectric 22 is not limited to this composition, but, for example can also use the interlayer dielectric of in first embodiment, describing 1.

When after forming interlayer dielectric 22 on the wafer W, the live width that forms each by photoetching technique and reactive ion etching (RIE) in interlayer dielectric 22 is 0.3 μ m or littler narrow wiring groove 22A and the live width of each the wide wiring groove 22B greater than 0.3 μ m, shown in Figure 10 B.

After in interlayer dielectric 22, forming narrow wiring groove 22A and wide wiring groove 22B, on interlayer dielectric 22, form barrier metal film 25, shown in Figure 10 C.Barrier metal film 25 constitutes by being selected from one or more following metals: 2A family, 4A family, 5A family, 6A family and 2B family, and described metal can form reactant with the metal as the main component of hereinafter electroplating film 27.Belong in 2A family, 4A family, 5A family, 6A family and the 2B family, and the example that can form the metal of reactant with the metal as the main component of electroplating film 27 is to be selected from one or more following metals: Mg, Ti, V, Zn, Zr, Hf and W.Wherein, preferred Ti.

When after forming barrier metal film 25 on the interlayer dielectric 22, on barrier metal film 25, form seed crystal film 26, shown in Figure 10 C.Seed crystal film 26 formed directly contact, and its main component is and the identical metal of metal as the main component of electroplating film 27 with barrier metal film 25.

When after forming seed crystal film 26 on the barrier metal film 25, electroplating solution is supplied on the surface of seed crystal film 26, and provide electric current to seed crystal film 26 simultaneously, thereby form electroplating film (first metal film) 27, shown in Figure 10 D by metallide.In this embodiment, electroplating film 27 is formed the part of imbedding whole each narrow wiring groove 22A and each wide wiring groove 22B.As the metal example of the main component of electroplating film 27 are at least a among Cu, Ag and the Au.

When after forming electroplating film 27 on the seed crystal film 26, form sputtered film (second metal film) 28 on the electroplating film 27 by for example sputtering at, shown in Figure 10 E.Sputtered film 28 is formed in the other parts of imbedding among each wide wiring groove 22B.The main component of sputtered film 28 is and the identical metal of metal as the main component of electroplating film 27, and its impurity concentration is lower than the impurity concentration of electroplating film 27.

When after forming sputtered film 28 on the electroplating film 27, the heat treatment wafer W, with the crystal of growth seed crystal film 26, electroplating film 27 and sputtered film 28, thus the wiring membrane 29 of formation shown in Figure 10 F.

After forming wiring membrane 29, polish by for example CMP, thereby that removes barrier metal film 25 on the interlayer dielectric 22 and wiring membrane 29 does not need part, and stays barrier metal film 25 and wiring membrane 29 in narrow wiring groove 22A and wide wiring groove 22B, shown in Figure 10 G.Thereby form the ground floor wiring, its live width with each is wide wiring (second wiring) 29B that is wider than 0.3 μ m that shows of 0.3 μ m or littler narrow wiring (first wiring) 29A and each.

After forming narrow wiring 29A and wide wiring 29B, on interlayer dielectric 22, form successively as the stopper film of RIE and the SiCN film 31 and the interlayer dielectric 32 of Cu nonproliferation film, shown in Figure 10 H.Interlayer dielectric 32 is made of following film: SiCO film 33, and it is inorganic insulating film with low dielectric constant; PAE film 34, it is the organic low dielectric constant dielectric film that forms on SiCO film 33; And the SiO that on PAE film 34, forms ₂Film 35.SiO ₂Film 35 also is used as diaphragm in CMP.

When after forming SiCN film 31 films such as grade on the interlayer dielectric 22,, in interlayer dielectric 32, form via hole 32A, narrow wiring groove 32B and wide wiring groove 32C, shown in Figure 10 I by photoetching technique and reactive ion etching (RIE).

Then, shown in Figure 10 J, on interlayer dielectric 32, form barrier metal film 36.Barrier metal film 36 is made of the metal identical with barrier metal film 25.

When after forming barrier metal film 36 on the interlayer dielectric 32, on barrier metal film 36, form seed crystal film 37, shown in Figure 10 J.Seed crystal film 37 formed directly contact, and its main component is and the identical metal of metal as the main component of hereinafter electroplating film 38 with barrier metal film 36.

When after forming seed crystal film 37 on the barrier metal film 36, electroplating solution is supplied on the surface of seed crystal film 37, and simultaneously, provide electric current, thereby form electroplating film (first metal film) 38, shown in Figure 10 K by metallide to seed crystal film 37.In this embodiment, electroplating film 38 is formed the part of imbedding whole each via hole 32A, whole each narrow wiring groove 32B and each wide wiring groove 32C.As the example of the metal of the main component of electroplating film 38 be and the identical metal of metal as the main component of electroplating film 27.

When after forming electroplating film 38 on the seed crystal film 37, form sputtered film (second metal film) 39 on the electroplating film 38 by for example sputtering at, shown in Figure 10 L.Sputtered film 39 is formed the other parts of imbedding each wide wiring groove 32C.The main component of sputtered film 39 is and the identical metal of metal as the main component of electroplating film 38, and its impurity concentration is lower than the impurity concentration in the electroplating film 38.

When after forming sputtered film 39 on the electroplating film 38, the heat treatment wafer W, with the crystal of growth seed crystal film 37, electroplating film 38 and sputtered film 39, thus the wiring membrane 40 of formation shown in Figure 10 M.

After forming wiring membrane 40, polish by for example CMP, thereby remove the barrier metal film 36 on the interlayer dielectric 32 and the unwanted part of wiring membrane 40, and stay barrier metal film 36 and wiring membrane 40 in via hole 32A, narrow wiring groove 32B and wide wiring groove 32C, shown in Figure 10 N.Thereby, forms and to pass through second wiring that stopple 40A is connected with the ground floor wiring, and its live width with each is 0.3 μ m or lower narrow wiring (first wiring) 40B and the wiring of each wide wiring (second connects up) 40C greater than 0.3 μ m.If desired, repeat these technology, thereby realize forming the 3rd layer and more high-rise wiring.

If have defective under the stopple excessively in dual-damascene structure, will reduce output, and owing to micro-interstices reduces deelectric transferred ability.The method of describing in above-mentioned first embodiment can address these problems, and still the wiring width and the degree of depth have in the multifarious actual graphical therein, on the other hand, may have the figure of the reliability reduction of anti-stress migration (SM).

Have and be, if the impurity concentration in the wiring is too low, not only in the heat treatment after forming sputtered film, also in the back technology of heat treatment etc., metallic atom in the wiring moves by diffusion, this may cause the variation of the particle size of metallic particles, and described back technology is used to recover the defect level of the gate insulating film of MOSFET (mos field effect transistor).This is because low impurity concentration has reduced the factor that the diffusion that suppresses metallic atom is moved in the wiring.This is considered to cause reducing the reliability of anti-stress migration (SM).This phenomenon takes place in the wide wiring of low impurity concentration especially easily.

On the other hand, in this embodiment, barrier metal film 25 is selected from following a kind of metal and constitutes by belonging to: 2A family, 4A family, 5A family, 6A family and 2B family, and described metal can form reactant with the metal of the main component of electroplating film 27, thereby, thereby on the interface between wide wiring 29B and the barrier metal film 25, form the atom level diffusion layer that comprises as the reactant of the metal of the main component of the wide 29B of wiring and the metal that in barrier metal film 25, comprises as the metal and the metal that in barrier metal film 25, comprises counterdiffusion mutually of the main component of wide wiring 29B.Specifically be that for example, when the main component of wide wiring 29B is Cu, and barrier metal film 25 is made of Ti, then forms the diffusion layer 30 of the reactant that comprises Cu and Ti on the interface between wide wiring 29B and the barrier metal film 25, shown in Figure 11 A.Formation comprises that the diffusion layer 30 of this reactant has increased the viscosity between wide wiring 29B and the barrier metal film 25, thereby the diffusion that prevents the metallic atom on the interface between wide wiring 29B and the barrier metal film 25 is moved.Therefore,, also can prevent the reduction of the reliability of anti-stress migration even when the impurity concentration among the wide wiring 29B is low, thus in wiring, can realize simultaneously preventing anti-stress migration reliability reduction and reduce defective.On the other hand, when the wide main component that connects up 29B is Cu, and barrier metal film is when being made of the metal Ta that can not form reactant with the metal as the main component of electroplating film 27, the diffusion layer that on the interface between wide wiring 29B and the barrier metal film 101, does not have to form the reactant that comprises Cu and Ta, shown in Figure 11 B, thereby can not obtain above-mentioned effect.

Except between wide wiring 29B and barrier metal film 25, also between narrow wiring 29A and the barrier metal film 25, crossing between stopple 32A and the barrier metal film 36, at the aforesaid diffusion layer that comprises this reactant of formation between narrow wiring 32B and the barrier metal film 36 and between wide wiring 32C and barrier metal film 36, thereby can obtain effect same as described above therein.

In this embodiment, each of the barrier metal film of using 25,36 is made of such metal, described metal belongs in 2A family, 4A family, 5A family, 6A family and the 2B family, and the reactant that can form with metal as the main component of electroplating

film

27,38, but can use other film to replace barrier metal film, as long as it comprises such metal and directly contacts with

seed crystal film

26,27.

As long as

barrier metal film

25,36 comprises such metal, described metal belongs in 2A family, 4A family, 5A family, 6A family and the 2B family, and the reactant that can form with the metal as the main component of electroplating

film

27,38, they can comprise other metal that can not form reactant with the metal as the main component of electroplating film 27,38.The metal example that can not form reactant with the metal as the main component of electroplating

film

27,38 is Ta, TaN etc.

And, contact with seed crystal film 26 as long as barrier metal film 25 formed directly, or barrier metal film 36 formed directly contact with seed crystal film 37, can form other barrier metal film between interlayer dielectric 22 and the barrier metal film 25 or between interlayer dielectric 32 and barrier metal film 36.In this case, other barrier metal film can be made of such metal, and described metal can not form reactant with the metal as the main component of electroplating

film

27,38 and sputtered film 28,29.Like this, under the situation that forms ground floor wiring and second layer wiring, form

barrier metal film

25,36, and between interlayer dielectric 22,32 and

wide wiring

29B, 40C, form another barrier metal film in

wide wiring

29B, 40C side in

interlayer dielectric

22,32 sides.

Should be noted that the invention is not restricted to the embodiments described and content, but, do not departing under the spirit of the present invention, can carry out suitable variation to structure, material and the layout etc. of parts.For example, in first and second embodiment, described wiring does not have sandwich construction, but can have sandwich construction as the 3rd embodiment, and perhaps opposite, the wiring in the 3rd embodiment does not need to have sandwich construction.

Claims

1. method of making semiconductor device comprises:

Have in its surface by electro-plating method and form first metal film on the substrate of first groove part and second groove part, with described first metal film is imbedded described first and second groove parts to small part;

On described first metal film, form second metal film by the film deposition method that is different from described electro-plating method, described second metal film contains as the metal of main component and comprises impurity, described metal is the main component of described first metal film, described impurity is at least a material in sulphur, chlorine, oxygen, carbon and the nitrogen, and the concentration of described impurity is lower than the concentration of the impurity that comprises in described first metal film;

Described first and second metal films of heat treatment; And

After described heat treatment, remove described first and second metal films the part in imbedding described first and second grooves,

Wherein, described semiconductor device comprises:

Described substrate;

Dielectric film forms on described substrate and has at same lip-deep described first groove part and described second groove part;

First wiring is embedded in described first groove part and has 0.3 μ m or littler live width; And

Second wiring is embedded in described second groove part and has live width greater than 0.3 μ m, and comprises concentration is lower than the impurity concentration that comprises in described first wiring impurity.

2. the method for manufacturing semiconductor device as claimed in claim 1 wherein forms described first metal film in the part of imbedding described groove part, and described second metal film is formed in the other parts of imbedding described groove part.

3. the method for manufacturing semiconductor device as claimed in claim 1, wherein said film deposition method are a kind of in sputter and the chemical vapour deposition (CVD).

4. the method for manufacturing semiconductor device as claimed in claim 1, wherein the concentration of the composition that concentration is the highest in the impurity component that comprises in described second metal film is 1.00 * 10 ¹⁷Atom/cm ³Or it is lower.

5. the method for manufacturing semiconductor device as claimed in claim 1, the main component of wherein said first metal film are a kind of in copper, silver and the gold.

6. the method for manufacturing semiconductor device as claimed in claim 1 also comprised before forming described first metal film:

At least form the film comprise one or more metals on the inner surface of described groove part, described metal belongs to one of 2A family, 4A family, 5A family, 6A family and 2B family, and can form reactant with the metal as the main component of described first metal film; And

Form the seed crystal film, its main component is the metal as the main component of described first metal film, thereby described seed crystal film is directly contacted with the described film that forms on the inner surface of described groove part,

Wherein when electric current being offered described seed crystal film, form the described step of described first metal film.

7. the method for manufacturing semiconductor device as claimed in claim 6, wherein belong to one of 2A family, 4A family, 5A family, 6A family and 2B family, and the described metal that can form reactant with the metal as the main component of described first metal film is magnesium, titanium, vanadium, zinc, zirconium, hafnium and tungsten.

8. the method for manufacturing semiconductor device as claimed in claim 6, the main component of wherein said first metal film is a copper, and be selected from and belong to one of 2A family, 4A family, 5A family, 6A family and 2B family, and one or more metals that can form with the metal as the main component of described first metal film in the described metal of reactant are titaniums.

9. the semiconductor device made of the method for a manufacturing semiconductor device according to claim 1 comprises:

Substrate;

Dielectric film forms on described substrate and has first groove part and at same lip-deep second groove part;

10. semiconductor device as claimed in claim 9, wherein the impurity concentration in described first wiring is 5 * 10 ¹⁸Atom/cm ³To 1 * 10 ¹⁹Atom/cm ³, and the impurity concentration in described second wiring is less than 5 * 10 ¹⁸Atom/cm ³

11. semiconductor device as claimed in claim 9, the live width of wherein said first wiring is more than or equal to 0.05 μ m and smaller or equal to 0.3 μ m, and the live width of described second wiring is greater than 0.3 μ m and smaller or equal to 10 μ m.

12. semiconductor device as claimed in claim 9, wherein said first wiring and described second main component that connects up are a kind of in copper, silver and the gold.

13. semiconductor device as claimed in claim 9, wherein said impurity are to have following at least a material: sulphur, chlorine, oxygen, carbon and nitrogen.

14. semiconductor device as claimed in claim 9 also comprises:

The film that comprises at least a or multiple metal, described metal is selected from and belongs to one of 2A family, 4A family, 5A family, 6A family and 2B family, and can form the metal of reactant with the main component of described second wiring, and described film is inserted between the inner surface and described second wiring of described second groove part; And

Diffusion layer, be arranged on the interface between described second wiring and the described film, the diffuseing to form mutually of the described metal that comprises in main component by described second wiring and the described film, and comprise the reactant of the described metal that comprises in the main component of described second wiring and the described film.

15. semiconductor device as claimed in claim 14 wherein belongs to one of 2A family, 4A family, 5A family, 6A family and 2B family, and can be selected from magnesium, titanium, vanadium, zinc, zirconium, hafnium and tungsten with the described metal of the described second main component formation reactant that connects up.

16. semiconductor device as claimed in claim 14, the main component of wherein said second wiring is a copper, and be selected from and belong to one of 2A family, 4A family, 5A family, 6A family and 2B family, and one or more metals that can form with the main component of described second wiring in the described metal of reactant are titaniums.