CN112687610B - Interconnect structure and method of forming the same - Google Patents
Interconnect structure and method of forming the same Download PDFInfo
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- CN112687610B CN112687610B CN201910991909.0A CN201910991909A CN112687610B CN 112687610 B CN112687610 B CN 112687610B CN 201910991909 A CN201910991909 A CN 201910991909A CN 112687610 B CN112687610 B CN 112687610B
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Abstract
The application discloses a forming method of an interconnection structure, which comprises the following steps: forming a dielectric layer on the semiconductor substrate, wherein an opening penetrating through the dielectric layer is formed in the dielectric layer; forming a seed crystal layer on the side wall and the bottom of the opening; performing reductive plasma treatment on the surface of the seed crystal layer; then, forming a controlled oxidation layer on the surface of the seed crystal layer; carrying out infiltration treatment on the semiconductor substrate in an electroplating solution, and removing the controlled oxide layer in the process of carrying out the infiltration treatment on the semiconductor substrate; and then, electroplating the opening by using the electroplating solution to form an electroplating layer on the seed crystal layer. The forming method of the interconnection structure disclosed by the application improves the performance of the interconnection structure.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to an interconnect structure and a method for forming the same.
Background
The conventional semiconductor metal wire is made of aluminum metal, but as the feature size of devices in integrated circuit chips is continuously reduced, the current density in the metal wire is continuously increased, the required response time is continuously reduced, and the conventional aluminum interconnection line cannot meet the requirement. Copper interconnect technology has replaced aluminum interconnect technology after process sizes are less than 20 nanometers. Compared with aluminum, the lower resistivity of the metal copper can reduce the resistance capacitance delay of the interconnection line, improve electromigration and improve the reliability of the device.
However, as the semiconductor process is developed to be less than 7 nm, the process technology has a bottleneck at the 7 nm node due to the insufficient conductive rate of copper as the conductive wire material. Under the advanced processes of 10 nm, 7 nm and the like, cobalt is used as a lead material, so that the aims of stronger conductivity, lower power consumption and smaller volume of a chip can be achieved.
There is also a need for improved methods of forming interconnect structures that eliminate the problems of the prior art.
Disclosure of Invention
The following presents a simplified summary of the application in order to provide a basic understanding of some aspects of the application. It should be understood that this section is not intended to identify key or critical elements of the application, nor is it intended to be limiting as to the scope of the application. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
In view of the above-mentioned shortcomings of the prior art, the present application provides an interconnect structure and a method for forming the same that avoids void defects between an electroplated layer and a seed layer.
The application provides a forming method of an interconnection structure, which comprises the following steps: providing a substrate; forming a dielectric layer on the substrate, wherein an opening penetrating through the dielectric layer is formed in the dielectric layer; forming seed crystal layers on the side wall and the bottom of the opening; performing reduction treatment on the surface of the seed crystal layer; forming a controlled oxidation layer on the surface of the seed crystal layer after the reducing treatment; performing immersion treatment on the substrate in an electroplating solution to remove the controlled oxide layer; after the immersion treatment, a main plating treatment is performed in the plating solution to form a plating layer on a seed layer in the opening, the main plating treatment being continuous with the immersion treatment.
Optionally, the material of the seed layer comprises cobalt; the material of the electroplated layer comprises cobalt.
Optionally, the thickness of the controlled oxidation layer is 0.5 nm to 2.5 nm.
Optionally, the reductive treatment comprises a reductive plasma treatment.
Optionally, the forming method of the interconnect structure further includes: providing an electroplating complete machine device, wherein the electroplating complete machine device comprises an electroplating main machine table, a first plasma processing machine table and a transmission device, the electroplating main machine table comprises an electroplating bath and a first mechanical arm positioned above the electroplating bath, and the electroplating bath is provided with the electroplating solution; the reductive treatment is carried out in a first plasma treatment machine; after the reductive treatment is carried out, taking the substrate out of the first plasma treatment machine platform by adopting the transmission device, and transmitting the substrate to the first mechanical arm; the step of forming the controlled oxidation layer comprises: the first robot arm operates the substrate to rotate in an air environment to form the controlled oxidation layer on the surface of the seed layer, the rotation lasting for a first predetermined time.
Optionally, the first predetermined time is 2 minutes to 20 minutes.
Optionally, in the process of forming the controlled oxide layer, the rotation is constant speed rotation, and the rotation speed is 6 to 12 revolutions per minute.
Optionally, during the formation of the controlled oxidation layer, the first robot arm steers the substrate to rotate around a central axis of the substrate.
Optionally, the time from the end of the plasma treatment to the start of the step of forming the controlled oxide layer is a second predetermined time, and the second predetermined time is 1 second to 3 seconds; and the time from the end of the step of forming the controlled oxide layer to the start of the soaking treatment is a third preset time, and the third preset time is 1-3 seconds.
Optionally, the forming method of the interconnect structure further includes: providing a plasma gas phase chemical deposition machine; the steps of reducing treatment and forming a controlled oxide layer are carried out in the same plasma gas-phase chemical deposition machine; in the process of carrying out reductive treatment, introducing reductive gas into the plasma gas-phase chemical deposition machine; and in the process of forming the controlled oxide layer, introducing oxidizing gas into the plasma gas phase chemical deposition machine.
Optionally, the time of the soaking treatment is 0.8 seconds to 1.5 seconds.
Optionally, the reducing gas used for the reducing treatment includes hydrogen.
Optionally, in the immersion treatment process, the electroplating solution is not electrified.
Optionally, the aperture of the opening is smaller than or equal to 28 nm.
Optionally, the substrate has a bottom connection layer therein, and the bottom connection layer includes a metal layer or a semiconductor layer; the opening is located on the bottom layer connecting layer, and the electroplated layer is located on the bottom layer connecting layer.
Optionally, the bottom connection layer is a semiconductor layer; the forming method of the interconnection structure further comprises the following steps: forming a metal silicide at the bottom of the opening before forming the seed layer.
Optionally, the method for forming an interconnect structure further includes: forming a barrier layer on sidewalls of the opening before forming the seed layer.
The invention also provides an interconnect structure formed by any of the above methods.
The technical scheme of the invention has the following beneficial effects:
in the forming method of the interconnection structure, the surface of the seed crystal layer is subjected to reducing treatment, the reducing treatment is used for removing natural oxides on the surface of the seed crystal layer before the substrate is immersed in the electroplating solution, and the phenomenon that the surface of the seed crystal layer is damaged due to the fact that the natural oxides with poor thickness uniformity are corroded in the electroplating solution is avoided. And forming a controlled oxidation layer on the surface of the seed crystal layer to serve as a protective layer, wherein the thickness uniformity of the controlled oxidation layer is better because the controlled oxidation layer is controlled in the forming process. The controlled oxidation layer is capable of protecting the seed layer from corrosion during immersion of the substrate in the electroplating solution until the substrate is fully immersed in the electroplating solution. And then, carrying out immersion treatment on the substrate in an electroplating solution to remove the controlled oxidation layer, thereby providing the seed crystal layer exposed in the electroplating solution for the main electroplating treatment. Because the main electroplating treatment is continuous with the soaking treatment, namely the main electroplating treatment is carried out immediately after the soaking treatment, the seed crystal layer can not be corroded by the electroplating solution before the electroplated layer is formed, and the defect of forming a cavity between the electroplated layer and the seed crystal layer is avoided. In summary, the performance of the interconnect structure is improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application.
FIGS. 1-4 are schematic diagrams of a process for forming an interconnect structure;
fig. 5 is a flowchart of a method for forming an interconnect structure according to an embodiment of the present disclosure.
Fig. 6 to 16 are schematic views illustrating a process of forming an interconnect structure according to an embodiment of the present disclosure.
Detailed Description
As mentioned in the background, the performance of prior art interconnect structures is yet to be improved.
A method of forming an interconnect structure, comprising: referring to fig. 1, a substrate 10 is provided; forming a dielectric layer 11 on a substrate 10, wherein an opening 12 penetrating through the dielectric layer is formed in the dielectric layer 11; forming a seed layer 13 on the sidewall and bottom of the opening 12; referring to fig. 2, the surface of the seed layer 13 is subjected to a reducing plasma treatment; thereafter, referring to fig. 3, the substrate 10 is completely placed in the plating solution; thereafter, a main plating process is performed in the plating solution to form a plating layer 14 on the seed layer 13 in the opening 12 (refer to fig. 4).
A seed layer 13 is formed in the deposition chamber. The seed layer 13 is taken out from the deposition chamber and exposed to the air environment until the next process step is performed, a native oxide layer is formed on the surface of the seed layer 13, and usually, the period of time is uncontrollable, long or short, so that the thickness of the native oxide layer corresponding to different wafers is uncontrollable and the thickness uniformity is poor. Before the substrate 10 is completely placed in the electroplating solution, natural oxide on the surface of the seed crystal layer 13 is removed by reducing plasma treatment, so that the phenomenon that the surface of the seed crystal layer 13 is damaged due to the fact that the natural oxide with poor thickness uniformity is corroded in the electroplating solution is avoided.
In the above method, the stage for the reducing plasma treatment and the stage for the main plating treatment are integrated, and thus, it is possible to control the step of completely placing the substrate 10 in the plating solution to be performed in a very short time after the reducing plasma treatment, and thus, no natural oxide is formed on the surface of the seed layer 13 after the reducing plasma treatment.
The substrate 10 is placed completely in the electroplating solution by: contacting a part of the edge of the substrate 10 with the surface of the electroplating solution, wherein the angle between the normal direction of the surface of the substrate 10 and the surface of the electroplating solution is an acute angle; the center of gravity of the substrate 10 is gradually lowered and the angle between the normal direction of the surface of the substrate 10 and the surface of the plating solution is changed from an acute angle to a right angle until the substrate 10 is completely placed in the plating solution. The purpose of this process is to avoid the generation of bubbles during the complete exposure of the substrate 10 to the electroplating solution, however, this process takes some time. In the case where the material of the seed layer 13 and the plating layer 14 is cobalt, no current flows through the plating solution during the process of completely placing the substrate 10 in the plating solution because: cobalt is active and when the substrate is partially exposed to the surface of the plating solution by applying a current, cobalt is plated on the surface of the seed layer in the substrate region, which affects the thickness uniformity of the plating layer in each region of the substrate.
Based on this, the surface of the seed layer 13 is exposed during the process of completely placing the substrate 10 in the electroplating solution, the surface of the seed layer 13 is easily corroded by the acid in the electroplating solution, resulting in the formation of voids on the surface of the seed layer 13, and after the formation of the plating layer 14, many voids exist between the plating layer 14 and the seed layer 120, resulting in poor performance of the interconnect structure.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming an interconnect structure, and with reference to fig. 5, the method includes the following steps:
step S1: providing a substrate;
step S2: forming a dielectric layer on the substrate, wherein an opening penetrating through the dielectric layer is formed in the dielectric layer;
and step S3: forming seed crystal layers on the side wall and the bottom of the opening;
and step S4: performing reduction treatment on the surface of the seed crystal layer;
step S5: forming a controlled oxidation layer on the surface of the seed crystal layer after the reducing treatment;
step S6: after the substrate is completely placed in an electroplating solution, carrying out infiltration treatment on the substrate to remove the controlled oxidation layer;
step S7: after the immersion treatment, a main plating treatment is performed in the plating solution to form a plating layer on a seed layer in the opening, the main plating treatment being continuous with the immersion treatment.
The above steps will be described in detail with reference to fig. 6 to 16.
As shown in fig. 6, a substrate 100 is provided.
The substrate 100 has a bottom connection layer 101 therein, and the bottom connection layer 101 is exposed on the surface of the substrate 100.
In this embodiment, the bottom connection layer 101 is a semiconductor layer. In this embodiment, a transistor is further formed in the substrate 100, and the semiconductor layer is a source region or a drain region of the transistor.
In other embodiments, the bottom connection layer 101 is a metal layer, and the material of the metal layer includes cobalt.
The material of the substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as a III-V compound such as gallium arsenide. The material of the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The material of the substrate 100 may also be a silicon germanium compound. The substrate 100 may also be a Silicon On Insulator (SOI) structure or a Silicon epitaxial layer structure.
As shown in fig. 7, a dielectric layer 200 is formed on a substrate 100, and an opening 202 is formed in the dielectric layer 200 to penetrate through the dielectric layer 200.
In one embodiment, the aperture of the opening 202 is equal to or less than 28 nanometers.
In this embodiment, the bottom of the opening 202 exposes the bottom connection layer 101. The dielectric layer 200 may be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or the like. In the present embodiment, the dielectric layer 200 may be silicon oxide (SiO) 2 ). The dielectric layer 200 may have a thickness of 100 nm to 4000 nm. The dielectric layer 200 may be formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. For example, the dielectric layer 200 may have a thickness of 800 to 900 nm.
The opening 202 may be formed by spin-coating a photoresist on the surface of the dielectric layer 200, forming an opening pattern in the photoresist after exposure and development processes, then etching to form the opening 202, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
As shown in fig. 8, a metal silicide 700 is formed at the bottom of the opening 202.
When the underlying connection layer 101 is a semiconductor layer, a metal silicide 700 is formed at the bottom of the opening 202, and the metal silicide 700 can be used to reduce the contact resistance between the underlying connection layer 101 and a subsequent plating layer.
The metal silicide 700 may be cobalt silicide, nickel silicide, titanium silicide.
The metal silicide 700 may be formed by: a metal film (e.g., cobalt, nickel, titanium) is first deposited on the surface of the bottom connection layer 101, and then annealed (e.g., rapid thermal annealing) is performed, so that the metal film and the bottom connection layer 101 react to form a metal silicide.
When the bottom connection layer 101 is a metal layer, no metal silicide is formed at the bottom of the opening 202.
As shown in fig. 9, a barrier layer 300 is formed on the sidewalls of the opening 202.
In this embodiment, the barrier layer 300 is first formed on the bottom of the sidewall of the opening 202 and on the dielectric layer 200, and then the barrier layer 300 on the dielectric layer 200 is removed, and the barrier layer 300 on the sidewall and the bottom of the opening 202 is remained.
In other embodiments, the barrier layer 300 is first formed on the bottom of the sidewall of the opening 202 and on the dielectric layer 200, and then the barrier layer 300 on the dielectric layer 200 and on the bottom of the opening 202 is removed, and the barrier layer 300 on the sidewall of the opening 202 is remained.
The barrier layer 300 functions to prevent metal atoms (e.g., cobalt atoms) in the seed layer and the plating layer from diffusing into the dielectric layer 200 and the semiconductor substrate 100, thereby causing contamination, resulting in degradation of device performance, while also reducing RC delay time due to parasitic resistance and parasitic capacitance. The barrier layer 300 also provides better adhesion between the seed layer and the dielectric layer 200.
The material of barrier layer 300 may be one or more of tantalum, tantalum nitride, titanium nitride, and tungsten nitride. The barrier layer 300 may have a single-layer structure or a two-layer stacked structure. In the present embodiment, the material of the barrier layer 300 is titanium nitride. The barrier layer 300 may be formed by physical Vapor Deposition, chemical Vapor Deposition, or Metal-Organic Chemical Vapor Deposition (MOCVD). For example, evaporation, e-beam evaporation, plasma jet deposition, and sputtering may be selected to form the barrier layer 300. For example, the thickness of the barrier layer 300 may be 20 to 30 angstroms.
As shown in fig. 10, a seed layer 400 is formed on the sidewalls and bottom of the opening 202.
The seed layer 400 may have a single-layer structure or a multi-layer structure including small-grain layers and large-grain layers having different grain sizes. When the cobalt seed layer having a multi-layer structure is selected, the small grain layer is under the large grain layer, which can improve the adhesion between the seed layer 400 and the barrier layer 300.
The material of the seed layer 400 is cobalt, and the material of the subsequent plating layer is cobalt.
When the aperture of the opening 202 is 28 nm or less, and when the material of the seed layer 400 is cobalt and the material of the subsequent plating layer is cobalt, in the case where the aperture of the opening 202 is small, the electron mean free path of cobalt is large, so that the total resistance of the seed layer and the plating layer is small.
In other embodiments, when the aperture of the opening 202 is greater than 28 nm, such as greater than 50 nm, the aperture of the opening 202 is larger, and the materials of the seed layer and the subsequent electroplated layer are selected to be copper, so that the total resistance of the seed layer and the electroplated layer is smaller.
In this embodiment, the method for forming the seed layer 400 is pvd, and the deposition process of the barrier layer 300 in the previous step can be sequentially performed in the same pvd apparatus. In some embodiments, the seed layer 400 may also be formed by chemical vapor deposition and atomic layer deposition. For example, the seed layer 400 may be 40 to 100 angstroms, such as 50 angstroms, 70 angstroms, 90 angstroms thick.
In this embodiment, the seed layer 400 is located on the surface of the barrier layer 300.
Fig. 11 illustrates a native oxide 402 formed via native oxidation at the surface of the seed layer 400.
In this embodiment, the seed layer 400 may be exposed to air before entering the electroplating solution, and thus the surface thereof may be oxidized naturally to form a native oxide 402. The thickness of the native oxide depends on the length of time the seed layer 400 is exposed to air and the degree of oxidation, and thus is generally unpredictable and uncontrollable, and the native oxide 402 may vary in thickness from wafer to wafer. In order to avoid the damage of the surface of the seed layer 13 caused by etching the native oxide with a less uniform thickness in the electroplating solution, the native oxide 402 with a uniform and controllable thickness is removed before the substrate 10 is completely placed in the electroplating solution, and then the controlled oxide layer with a uniform and controllable thickness is formed again.
As shown in fig. 12, the native oxide 402 formed by native oxidation on the surface of the seed layer 400 is removed.
In the present embodiment, the surface of the seed layer 400 is subjected to a reducing treatment (e.g., hydrogen plasma) to remove a native oxide formed on the surface of the seed layer 400 by a native oxidation reaction.
In one embodiment, the reductive treatment performed on the surface of the seed layer 400 is a reductive plasma treatment.
As shown in fig. 13, after the reductive plasma treatment is performed, a controlled oxidation layer 500 is formed on the surface of the seed layer 400.
The controlled oxidation layer is formed on the surface of the seed layer 400 as a protective layer, and since the controlled oxidation layer is controlled during the formation process, the thickness uniformity of the controlled oxidation layer is better. During the subsequent process of immersing the substrate in the electroplating solution, the controlled oxidation layer can protect the seed crystal layer from being corroded until the substrate is completely immersed in the electroplating solution.
In order to provide good protection for the controlled oxide layer 500, the thickness of the controlled oxide layer 500 needs to be strictly controlled, too thin the controlled oxide layer 500 will affect the protection effect on the seed layer 400, and too thick the controlled oxide layer 500 will prolong the process flow, because it takes a certain time to form and remove the controlled oxide layer 500. Therefore, it is desirable to provide a method for forming a controlled oxide layer 500 that is controllable.
In this embodiment, the method further includes: an electroplating complete machine device is provided, the electroplating complete machine device comprises an electroplating main machine table 20 (shown in fig. 14), a first plasma processing machine table and a transmission device, the electroplating main machine table 20 comprises an electroplating bath 20A and a first mechanical arm 20B positioned above the electroplating bath 20A, and the electroplating bath 20A is provided with an electroplating solution 20D. In fig. 14, the substrate has not yet entered the plating bath 20A.
The plating main stand 20 further includes: a control part 20C, the control part 20C comprising a lifting arm 20C1 and a cross arm 20C2, one end of the cross arm 20C2 is connected to the lifting arm 20C1 and can perform up-and-down translation along the lifting arm 20C 1.
The first robot arm 20B includes a driving portion 20B1 and a holding portion 20B2 connected to each other, wherein one end of the driving portion 20B1 is rotatably connected to the crossbar 20C2, the other end of the driving portion 20B1 is connected to the holding portion 20B2, the driving portion 20B1 is capable of driving the holding portion 20B2 to move up and down and driving the holding portion 20B2 to rotate about a central axis of the holding portion 20B2, and driving the holding portion 20B2 to perform a tilting motion with respect to the driving portion 20B 1. The clamping portion 20B2 is provided with a metal ring 20B21 for fixing a workpiece (e.g., a substrate or a wafer) to be plated.
The reductive plasma treatment is performed in a first plasma treatment station. After the reductive plasma treatment, the substrate is taken out of the first plasma treatment station by the transfer device and transferred to the first robot 20B.
The step of forming the controlled oxidation layer comprises: and the first mechanical arm controls the substrate to rotate in the air environment for a first preset time, so that the controlled oxidation layer is formed on the surface of the seed crystal layer.
The first predetermined time is 2 minutes to 20 minutes. During the formation of the controlled oxidation layer, the substrate is rotated at a uniform speed in an air environment, and the rotation speed is 6 to 12 revolutions per minute.
During the formation of the controlled oxide layer, the first robot arm 20B manipulates the substrate to rotate about the central axis of the substrate.
The controlled oxidation layer may have a thickness of 0.5 nm to 2.5 nm, such as 1 nm to 2 nm. In some embodiments of the present application, the controlled oxidation layer has a thickness of 1 to 2 nanometers.
In some embodiments of the present application, the step of forming the controlled oxidation layer 500 on the surface of the seed layer 400 may include: after the substrate is transferred to the first robot after being taken out of the first plasma processing apparatus by using the transfer device, the surface of the seed layer 400 is flushed with an oxidizing gas (e.g., a gas containing oxygen) to form a controlled oxidation layer 500 on the surface of the seed layer 400. In some embodiments, the gas may be flushed at an angle perpendicular to the surface of the substrate 100, or at a specific angle (e.g., 90%, 80%, 70%, 60%, etc.) relative to the surface of the substrate 100. In some embodiments, the gas used for flushing may be ordinary air, water vapor, or a mixture of oxygen and an inert gas. In order to properly oxidize the surface of the seed layer 400, the oxygen content of the gas for rinsing may be 15% to 25%.
The time for transferring the substrate to the first robot after the substrate is taken out of the first plasma processing machine by using the transfer device is controlled, and the step for forming the controlled oxidation layer 500 is performed immediately after the substrate is transferred to the first robot after the substrate is taken out of the first plasma processing machine, so that the thickness of the controlled oxidation layer 500 is uniform, and the thickness uniformity of the controlled oxidation layer 500 corresponding to each wafer is good.
In the above case, the end time of the plasma treatment to the start time after the step of forming the controlled oxide layer is a second predetermined time, which is 1 second to 3 seconds, that is, the time for transferring the substrate from the first plasma treatment stage to the first robot arm is 1 second to 3 seconds.
In other embodiments, a plasma vapor chemical deposition station is provided, and the steps of reducing plasma treatment and forming the controlled oxide layer are performed sequentially in the same plasma vapor chemical deposition station. And in the process of carrying out reductive plasma treatment, introducing reductive gas into the plasma vapor phase chemical deposition machine, and in the process of forming the controlled oxidation layer, introducing oxidizing gas into the plasma vapor phase chemical deposition machine.
As shown in fig. 15, after the substrate 100 is completely immersed in the electroplating solution, the substrate 100 is subjected to a wetting process to remove the controlled oxidation layer 500.
In this embodiment, when the material of the seed layer 400 is cobalt, the electroplating solution is not electrified during the immersion treatment.
In this embodiment, the thickness of the controlled oxide layer is 0.5 nm to 2.5 nm, and the time of the wetting treatment is 0.8 seconds to 1.5 seconds.
Due to the controlled oxide 500, the controlled oxide layer can protect the seed layer from corrosion during immersion of the substrate in the electroplating solution until the substrate is completely immersed in the electroplating solution, thereby preventing void defects from occurring in the seed layer 400 when contacting the electroplating solution.
The time from the end of the step of forming the controlled oxide layer 500 to the start of the wetting process is a third predetermined time, and the third predetermined time is 1 second to 3 seconds. That is, after the end time of the step of forming the controlled oxidation layer 500, the process of completely immersing the substrate 100 in the plating solution from the outside of the plating tank is 1 to 3 seconds.
The method of placing the substrate 100 completely in the electroplating solution is: contacting a part of the edge of the substrate 100 with the surface of the plating solution, wherein an angle between the normal direction of the surface of the substrate 100 and the surface of the plating solution is an acute angle; the center of gravity of the substrate 100 is gradually lowered and the angle between the normal direction of the surface of the substrate 100 and the surface of the plating solution is changed from an acute angle to a right angle until the substrate 100 is completely placed in the plating solution. The purpose of this process is to avoid the generation of bubbles during the complete exposure of the substrate 100 to the electroplating solution.
The controlled oxidation layer 500 is removed by performing a wetting process, so that the seed layer 400 exposed in the electroplating solution is provided for the main electroplating process, and the uniformity of the thickness of the controlled oxidation layer 500 is good, so that the controlled oxidation layer 500 at each position of the seed layer 400 can be completely removed at the end of the step of removing the controlled oxidation layer 500, the material of the controlled oxidation layer 500 is prevented from remaining on the surface of part of the seed layer 400, and the surface of the seed layer 400 is prevented from being over-etched.
As shown in fig. 16, after the immersion treatment, a main plating treatment is performed in the plating solution to form a plating layer 600 on the seed layer 400 in the opening, the main plating treatment being continuous with the immersion treatment.
In the main plating process, electricity is applied to the plating solution, so that the surface of the seed layer 400 forms the plating layer 600 by the electric field. In some embodiments, both the metal ring and the substrate 100 remain rotated during the main plating process.
Because the main electroplating treatment is continuous with the soaking treatment, namely the main electroplating treatment is carried out immediately after the soaking treatment is carried out, the seed crystal layer can not be corroded by the electroplating solution before the electroplated layer is formed, and the defect of a hollow hole formed between the electroplated layer and the seed crystal layer is avoided.
Correspondingly, the embodiment also provides an interconnection structure formed by adopting the method.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
Claims (18)
1. A method of forming an interconnect structure, comprising:
providing a substrate;
forming a dielectric layer on the substrate, wherein an opening penetrating through the dielectric layer is formed in the dielectric layer;
seed crystal layers are formed on the side walls and the bottoms of the openings, and natural oxides are formed on the surfaces of the seed crystal layers;
performing reduction treatment on the surface of the seed crystal layer to remove the natural oxide;
forming a controlled oxidation layer on the surface of the seed layer after the reducing treatment, the forming of the controlled oxidation layer including: operating the substrate to rotate at a constant speed in an air environment;
after the substrate is completely placed in an electroplating solution, carrying out infiltration treatment on the substrate to remove the controlled oxidation layer;
after the immersion treatment, a main plating treatment is performed in the plating solution to form a plating layer on a seed layer in the opening, the main plating treatment being continuous with the immersion treatment.
2. The method of claim 1, wherein a material of the seed layer comprises cobalt; the material of the electroplated layer comprises cobalt.
3. The method of claim 1, wherein the controlled oxidation layer has a thickness of 0.5 nm to 2.5 nm.
4. The method of claim 1, wherein the reducing process comprises a reducing plasma process.
5. The method of forming an interconnect structure of claim 4, further comprising: providing an electroplating complete machine device, wherein the electroplating complete machine device comprises an electroplating main machine table, a first plasma processing machine table and a transmission device, the electroplating main machine table comprises an electroplating bath and a first mechanical arm positioned above the electroplating bath, and the electroplating bath is provided with the electroplating solution; the reductive treatment is carried out in the first plasma treatment machine; after the reductive treatment is carried out, taking the substrate out of the first plasma treatment machine platform by adopting the transmission device, and transmitting the substrate to the first mechanical arm;
the step of forming the controlled oxidation layer comprises: the first mechanical arm operates the substrate to rotate in an air environment, so that the controlled oxidation layer is formed on the surface of the seed crystal layer, and the rotation lasts for a first preset time.
6. The method for forming an interconnect structure according to claim 5, wherein the first predetermined time is 2 minutes to 20 minutes.
7. The method of claim 5, wherein the rotation is a constant speed rotation having a speed of 6 to 12 revolutions per minute.
8. The method of claim 5, wherein the first robot arm maneuvers the substrate to rotate about a central axis of the substrate during the formation of the controlled oxidation layer.
9. The method of claim 5, wherein an end time of the plasma treatment to a start time of the step of forming the controlled oxide layer is a second predetermined time, and the second predetermined time is 1 second to 3 seconds; and the time from the end of the step of forming the controlled oxide layer to the start of the soaking treatment is a third preset time, and the third preset time is 1-3 seconds.
10. The method of forming an interconnect structure according to claim 4, further comprising: providing a plasma vapor chemical deposition machine; the steps of reducing treatment and forming the controlled oxide layer are carried out in the same plasma gas phase chemical deposition machine;
in the reductive treatment process, introducing reductive gas into the plasma gas-phase chemical deposition machine; and in the process of forming the controlled oxidation layer, introducing oxidizing gas into the plasma gas phase chemical deposition machine.
11. The method of claim 1, wherein the wetting process is performed for a time of 0.8 seconds to 1.5 seconds.
12. The method of claim 1, wherein the reducing gas used in the reducing process comprises hydrogen.
13. The method of claim 1, wherein the plating solution is not energized during the immersion process.
14. The method of claim 1, wherein the opening has an aperture of 28 nm or less.
15. The method of claim 1, wherein the substrate has a bottom connection layer therein, the bottom connection layer comprising a metal layer or a semiconductor layer; the opening is located on the bottom layer connecting layer, and the electroplated layer is located on the bottom layer connecting layer.
16. The method of forming an interconnect structure according to claim 15, wherein the bottom connection layer is a semiconductor layer; the forming method of the interconnection structure further comprises the following steps: forming a metal silicide at the bottom of the opening before forming the seed layer.
17. The method of forming an interconnect structure of claim 1, further comprising: forming a barrier layer on sidewalls of the opening before forming the seed layer.
18. An interconnect structure formed by the method of any of claims 1 to 17.
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| CN1547245A (en) * | 2003-12-16 | 2004-11-17 | 上海华虹（集团）有限公司 | Preprocessing technique for removing oxide film from surface of copper seed crystal and reinforcing copper layer adhesion |
| CN101989570A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Forming method of contact hole structure |
| CN106158727A (en) * | 2015-03-30 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Copper metallization technology |
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| US6423200B1 (en) * | 1999-09-30 | 2002-07-23 | Lam Research Corporation | Copper interconnect seed layer treatment methods and apparatuses for treating the same |
| US8648465B2 (en) * | 2011-09-28 | 2014-02-11 | International Business Machines Corporation | Semiconductor interconnect structure having enhanced performance and reliability |
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| CN1547245A (en) * | 2003-12-16 | 2004-11-17 | 上海华虹（集团）有限公司 | Preprocessing technique for removing oxide film from surface of copper seed crystal and reinforcing copper layer adhesion |
| CN101989570A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Forming method of contact hole structure |
| CN106158727A (en) * | 2015-03-30 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Copper metallization technology |
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