CN116759383B - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

Info

Publication number
CN116759383B
CN116759383B CN202311034967.7A CN202311034967A CN116759383B CN 116759383 B CN116759383 B CN 116759383B CN 202311034967 A CN202311034967 A CN 202311034967A CN 116759383 B CN116759383 B CN 116759383B
Authority
CN
China
Prior art keywords
layer
dielectric layer
stop layer
stop
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202311034967.7A
Other languages
Chinese (zh)
Other versions
CN116759383A (en
Inventor
汪志文
陈杨
詹朝翔
林成芝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nexchip Semiconductor Corp
Original Assignee
Nexchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nexchip Semiconductor Corp filed Critical Nexchip Semiconductor Corp
Priority to CN202311034967.7A priority Critical patent/CN116759383B/en
Publication of CN116759383A publication Critical patent/CN116759383A/en
Application granted granted Critical
Publication of CN116759383B publication Critical patent/CN116759383B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Element Separation (AREA)

Abstract

The application relates to a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein a first stop layer, a first dielectric layer, an isolation layer, a second dielectric layer, a second stop layer, a third dielectric layer and a barrier layer are sequentially laminated along the thickness direction of the substrate; the first stop layer is adjacent to the substrate; removing part of the barrier layer and part of the third dielectric layer to form a reference groove exposing part of the second stop layer; etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction through the reference groove to form a target groove exposing part of the substrate; forming a metal filling layer, wherein the metal filling layer fills the target groove and covers the top surface of the barrier layer; removing the part of the metal filling layer higher than the second stopping layer, the blocking layer and the third dielectric layer, wherein the rest of the metal filling layer forms a metal plug; and removing the second stop layer. The accuracy of the semiconductor structure is improved.

Description

Semiconductor structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.
Background
The first metal connecting layer is a metal layer of the first connecting metal plug and is used for locally connecting and leading out the front-stage device. The first metal connection layer is the last gate before the external signal of the integrated circuit is transmitted into the device through the metal wiring, and the first metal connection layer is also the process with the minimum feature size in the back-end process, so that the etching process of the first metal connection layer is required to be more strict.
The conventional first metal connection layer can cause side wall etching due to too high depth ratio of the groove in the process, critical dimension is larger, grinding is stopped according to time determination in the mechanical grinding process, grinding height inaccuracy can be caused, and the integration level and accuracy of the device are reduced.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor structure and a method for fabricating the same that can avoid over-etching of the sidewalls and accurately polish the sidewalls.
To achieve the above and other objects, according to various embodiments of the present application, an aspect of the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein a first stop layer, a first dielectric layer, an isolation layer, a second dielectric layer, a second stop layer, a third dielectric layer and a barrier layer are sequentially laminated along the thickness direction of the substrate; the first stop layer is adjacent to the substrate; removing part of the barrier layer and part of the third dielectric layer to form a reference groove exposing part of the second stop layer; etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction through the reference groove to form a target groove exposing part of the substrate; forming a metal filling layer, wherein the metal filling layer fills the target groove and covers the top surface of the barrier layer; removing the part of the metal filling layer higher than the second stopping layer, the blocking layer and the third dielectric layer, wherein the rest of the metal filling layer forms a metal plug; and removing the second stop layer.
In the method for manufacturing the semiconductor structure in the above embodiment, the second stop layer is used as the etching stop layer, the target trench is formed in two steps, the part of the barrier layer and the part of the third dielectric layer on the second stop layer are removed first to form the reference trench, the width of the target trench is determined, the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer are etched along the thickness direction through the reference trench to form the target trench, after the width of the target trench is determined by the first etching, the directional etching is performed in the thickness direction to avoid the side wall etching, so that the width of the target trench is ensured not to be enlarged, and the product accuracy is improved; after the metal filling layer is formed, the second stopping layer is used as a chemical mechanical polishing stopping layer, only the part, the blocking layer and the third dielectric layer, which are higher than the second stopping layer, of the metal filling layer are removed, the rest of the metal filling layer forms a metal plug, excessive polishing or insufficient polishing of the metal plug is avoided, and the product yield is improved through accurate polishing. Therefore, the second stop layer of the embodiment can be used as an etching stop layer, so that the side wall etching of the target groove is avoided through two-step etching, and can also be used as a chemical mechanical polishing stop layer, so that excessive polishing or insufficient polishing of the metal plug is avoided, the accuracy of the semiconductor structure is improved, and the yield of a final product is improved.
In some embodiments, the width of the target trench is related to the width of the reference trench, which defines the width of the target trench, such that the overall width of the target trench is uniform, improving the accuracy of the semiconductor structure.
In some embodiments, the etch selectivity of the isolation layer to the second dielectric layer is greater than 1; the etching selection ratio of the isolation layer to the first dielectric layer is greater than 1; the thickness of the isolation layer is larger than that of the second dielectric layer/the first dielectric layer; forming a target trench, comprising: and etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction by adopting a dry etching process through the reference groove so as to form a target groove. The etching selectivity ratio of the isolation layer to the second dielectric layer on the upper layer of the isolation layer is larger than 1, and the thickness of the isolation layer is larger than that of the second dielectric layer, so that the etching efficiency is higher when the isolation layer is etched, the isolation layer has a steep etching section, and side wall etching of the isolation layer is avoided; and because the etching selection ratio of the isolation layer to the first dielectric layer below the isolation layer is larger than 1, and the thickness of the isolation layer is larger than that of the first dielectric layer, when the isolation layer is etched to the first dielectric layer, the etching rate can be greatly reduced, so that the isolation layer can be fully etched, and the over-etching can be avoided.
In some embodiments, forming the target trench further comprises: etching the second stop layer, the second dielectric layer, the isolation layer and the first dielectric layer along the thickness direction by adopting a dry etching process through the reference groove so as to form an intermediate groove exposing part of the first stop layer; and removing part of the first stop layer through the middle groove to form a target groove exposing part of the substrate, so that over etching of the substrate is avoided.
In some embodiments, forming the target trench further comprises: and removing part of the first stop layer by adopting a wet etching process through the middle groove to form a target groove exposing part of the substrate, wherein the wet etching can be performed without etching residues, and the cleanliness of the etched substrate is ensured.
In some embodiments, removing the portion of the metal fill layer above the second stop layer, the barrier layer, and the third dielectric layer includes: and removing the part of the metal filling layer higher than the second stop layer, the barrier layer and the third dielectric layer by adopting a chemical mechanical polishing process, and forming a metal plug by the residual metal filling layer. The second stop layer is used as a chemical mechanical polishing stop layer, so that the metal filling layer is ensured not to be sunken due to excessive polishing or the metal plug is ensured to be too high due to insufficient abrasion, the high precision of the metal plug is ensured, the precise polishing is achieved, and the product yield is improved.
In some embodiments, removing the second stop layer includes: and removing the second stop layer by adopting a wet etching process, so that the top surface of the metal plug is higher than the top surface of the second dielectric layer, and the etching cost is reduced.
In some embodiments, the materials and thicknesses of the first dielectric layer and the second dielectric layer are the same, so that the etching selection ratio of the isolation layer to the first dielectric layer and the second dielectric layer adjacent to the isolation layer is the same, and the accuracy in etching the second dielectric layer, the isolation layer and the first dielectric layer is further ensured.
In some embodiments, the material of the first stop layer comprises polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron nitride silicon carbide, or combinations thereof; the material of the isolation layer comprises fluorine-silicon glass, carbon doped silicon oxide, silicon-based high polymer material, inorganic porous material, organic porous material or the combination thereof; the material of the second stop layer comprises polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron carbon silicon nitride, or combinations thereof; the material of the barrier layer comprises titanium nitride, tantalum nitride, tungsten nitride, titanium tungsten or a combination thereof; the material of the metal filling layer comprises copper, tungsten, copper alloy, tungsten alloy or a combination thereof.
In another aspect, the present application provides a semiconductor structure, including a substrate and a metal plug, where a first stop layer, a first dielectric layer, an isolation layer, and a second dielectric layer are sequentially stacked along a thickness direction of the substrate; the first stop layer is adjacent to the substrate; the metal plug penetrates through the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction; wherein the bottom surface of the metal plug contacts the top surface of the connection substrate.
In the semiconductor structure of the above embodiment, the method for manufacturing a semiconductor structure is adopted, the second stop layer is used as the etching stop layer, the target trench is formed in two steps, the first step is to remove part of the barrier layer and part of the third dielectric layer on the second stop layer, form the reference trench, determine the width of the target trench, the second step is to etch the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction through the reference trench, form the target trench, after the width of the target trench is determined by the first step, the second step is to etch with directivity along the thickness direction, so as to avoid side wall etching, thereby ensuring that the width of the target trench is not expanded, and improving the product accuracy; after the metal filling layer is formed, the second stopping layer is used as a chemical mechanical polishing stopping layer, only the part, the blocking layer and the third dielectric layer, which are higher than the second stopping layer, of the metal filling layer are removed, the rest of the metal filling layer forms a metal plug, excessive polishing or insufficient polishing of the metal plug is avoided, and the product yield is improved through accurate polishing. Therefore, the second stop layer of the embodiment can be used as an etching stop layer, so that the side wall etching of the target groove is avoided through two-step etching, and can also be used as a chemical mechanical polishing stop layer, so that excessive polishing or insufficient polishing of the metal plug is avoided, the accuracy of the semiconductor structure is improved, and the yield of a final product is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a first embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a second embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a third embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a fourth embodiment of the present application;
fig. 6 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a fifth embodiment of the present application;
fig. 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor structure according to a sixth embodiment of the present application;
fig. 8 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a seventh embodiment of the present application.
Reference numerals illustrate:
10. a substrate; 11. a first stop layer; 12. a first dielectric layer; 13. an isolation layer; 14. a second dielectric layer; 15. a second stop layer; 16. a third dielectric layer; 17. a barrier layer; 211. a reference trench; 21. a middle groove; 20. a target trench; 31. a metal filling layer; 30. a metal plug; 100. a semiconductor structure.
Description of the embodiments
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that, the illustrations provided in the present embodiment are only schematic illustrations of the basic concept of the present application, and only the components related to the present application are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
After the traditional first metal connecting layer is formed, the film layers with different selection ratios are required to be etched together, but the side wall etching can be generated due to the excessively high depth-to-width ratio in the deep trench etching step, the critical dimension (Critical Dimension, CD) is larger, and the integration level of the chip is reduced; meanwhile, in the step of chemical mechanical polishing, the conventional technology only controls the polishing on the low dielectric layer to a certain height by time according to the design requirement, which can cause excessive polishing or insufficient polishing and reduce the quality of the semiconductor structure.
Referring to fig. 1, the present application provides a method for preparing a semiconductor structure, which includes:
step S102: providing a substrate, wherein a first stop layer, a first dielectric layer, an isolation layer, a second dielectric layer, a second stop layer, a third dielectric layer and a barrier layer are sequentially laminated along the thickness direction of the substrate; the first stop layer is adjacent to the substrate;
step S104: removing part of the barrier layer and part of the third dielectric layer to form a reference groove exposing part of the second stop layer;
step S106: etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction through the reference groove to form a target groove exposing part of the substrate;
step S108: forming a metal filling layer, wherein the metal filling layer fills the target groove and covers the top surface of the barrier layer;
step S110: removing the part of the metal filling layer higher than the second stopping layer, the blocking layer and the third dielectric layer, wherein the rest of the metal filling layer forms a metal plug;
step S112: and removing the second stop layer.
As an example, please continue to refer to fig. 1, in this embodiment, the second stop layer is used as an etching stop layer, and a target trench is formed in two steps, wherein a part of the barrier layer and a part of the third dielectric layer above the second stop layer are removed first to form a reference trench, the width of the target trench is determined, the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer are etched along the thickness direction through the reference trench to form the target trench, after the width of the target trench is determined by the first etching, the second etching is performed with directivity along the thickness direction, so that the side wall etching is avoided, the width of the target trench is ensured not to be enlarged, and the product accuracy is improved; after the metal filling layer is formed, the second stopping layer is used as a chemical mechanical polishing stopping layer, only the part, the blocking layer and the third dielectric layer, which are higher than the second stopping layer, of the metal filling layer are removed, the rest of the metal filling layer forms a metal plug, excessive polishing or insufficient polishing of the metal plug is avoided, and the product yield is improved through accurate polishing. Therefore, the second stop layer of the embodiment can be used as an etching stop layer, so that the side wall etching of the target groove is avoided through two-step etching, and can also be used as a chemical mechanical polishing stop layer, so that excessive polishing or insufficient polishing of the metal plug is avoided, the accuracy of the semiconductor structure is improved, and the yield of a final product is improved.
As an example, referring to fig. 2, in step S102, a first stop layer 11, a first Dielectric layer 12, an isolation layer 13, a second Dielectric layer 14, a second stop layer 15, a third Dielectric layer 16, and a barrier layer 17 sequentially stacked along a thickness direction of the substrate 10 may be formed by a deposition process, where the thickness of the second stop layer is related to the depth of the target trench, and the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high-density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process, and a Spin-on Dielectric (SOD) process.
As an example, with continued reference to fig. 2, the substrate 10 in step S102 may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate should not limit the scope of the present disclosure.
As an example, referring to fig. 3, in step S104, a photoresist material layer (not shown) may be coated on the surface of the barrier layer 17, and a patterned photoresist layer is formed through a series of steps such as exposure, development, etc., where the patterned photoresist layer has an opening pattern defining the position and shape of the reference trench 211, and the patterned photoresist layer defines the width of the reference trench 211 as a preset critical dimension; the barrier layer 17 and the third dielectric layer 16 are etched using an etching process with the patterned photoresist layer as a mask to form the reference trench 211. The etching process may include, but is not limited to, a dry etching process and/or a wet etching process. The dry etching process may include, but is not limited to, one or more of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), and high-concentration plasma etching (HDP).
In some embodiments, referring to fig. 4-5, the etching selectivity of the isolation layer 13 to the second dielectric layer 14 is greater than 1; the etching selection ratio of the isolation layer 13 to the first dielectric layer 12 is greater than 1; the thickness of the isolation layer 13 is larger than that of the second dielectric layer 14 or the first dielectric layer 12; forming the target trench 20 in step S106 includes:
step S1061: the second stop layer 15, the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11 are etched in the thickness direction through the reference trench 211 by a dry etching process to form a target trench 20.
As an example, in step S1061, the etching gas may be activated by using a high-frequency glow discharge reaction to activate active particles, such as atoms or radicals, and these active particles diffuse to the portions to be etched to react with the second stop layer 15, the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11, so that the second stop layer 15, the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11 become volatile products to be removed, thereby achieving the purpose of etching the second stop layer 15, the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11 to form the target trench 20.
In some embodiments, please continue with fig. 4-5, the forming of the target trench 20 in step S106 further includes:
step S10611: etching the second stop layer 15, the second dielectric layer 14, the isolation layer 13 and the first dielectric layer 12 in the thickness direction by using a dry etching process through the reference trench 211 to form an intermediate trench 21 exposing a portion of the first stop layer 11;
step S10612: a portion of the first stop layer 11 is removed via the intermediate trench 21 to form a target trench 20 exposing a portion of the substrate 10.
As an example, please continue to refer to fig. 4-5, in step S10611, the second stop layer 15 is removed by a wet etching process, and then the second dielectric layer 14, the isolation layer 13 and the first dielectric layer 12 are etched by a dry etching process along the thickness direction, because the etching selectivity of the isolation layer 13 and the second dielectric layer 14 on the upper layer of the isolation layer 13 is greater than 1 due to the selected etching gas, and the thickness of the isolation layer 13 is greater than the thickness of the second dielectric layer 14, the etching efficiency is higher when the isolation layer 13 is etched, so that the isolation layer 13 has a steep etching profile, and the sidewall etching of the isolation layer 13 is avoided; and because the etching gas is selected to cause the etching selection ratio of the isolation layer 13 and the first dielectric layer 12 below the isolation layer 13 to be more than 1, and the thickness of the isolation layer 13 is more than that of the first dielectric layer 12, when the first dielectric layer 12 is etched, the etching rate can be greatly reduced, so that the isolation layer 13 can be fully etched, and the over-etching can be avoided.
In some embodiments, referring to fig. 4-5, the forming of the target trench 20 in step S106 further includes:
step S106121: a wet etching process is performed through the intermediate trench 21 to remove a portion of the first stop layer 11 to form a target trench 20 exposing a portion of the substrate 10.
As an example, referring to fig. 4 to 5, in step S10613, only the first stopping layer 11 may be removed, or the first stopping layer 11 and a portion of the substrate 10 may be removed by over-etching, so as to avoid incomplete etching.
In some embodiments, referring to fig. 5, the width of the target trench 20 is related to the width of the reference trench 211. The width of the reference trench 211 is a preset critical dimension, and the width of the reference trench 211 defines the width of the target trench 20 as well as the preset critical dimension, and since the etching selection ratio of the isolation layer 13 to the first dielectric layer 12 and the second dielectric layer 14 adjacent to the isolation layer 13 is greater than 1 in the formation process of the target trench 20, the isolation layer 13 is ensured not to generate side wall etching, so that the whole width of the target trench 20 is uniformly the preset critical dimension, and the expansion of the width of the target trench 20 due to the side wall etching is avoided, thereby improving the precision of the critical dimension, the integration level of the semiconductor structure 100 and the final yield of products.
As an example, referring to fig. 6, in step S108, a deposition process may be used to form the metal filling layer 31, where the metal filling layer 31 fills the target trench 20 and covers the top surface of the barrier layer 17, and the deposition process may include, but is not limited to, one or more of CVD, ALD, HDP, SOD and the like.
In some embodiments, referring to fig. 7, in step S110, removing the portion of the metal filling layer 31 higher than the second stop layer 15, the barrier layer 17 and the third dielectric layer 16 includes:
step S1101: the part of the metal filling layer 31 higher than the second stop layer 15, the barrier layer 17 and the third dielectric layer 16 are removed by adopting a chemical mechanical polishing process, and the remaining metal filling layer 31 forms a metal plug 30.
As an example, please continue to refer to fig. 7, the second stop layer 15 is used as a chemical mechanical polishing stop layer, the barrier layer 17 and the rotating polishing pad are disposed opposite to each other, and a polishing solution containing abrasive grains and chemical additives is provided on the polishing pad, when the top surface of the barrier layer 17 contacts the polishing pad, the chemical additives in the polishing solution will cause hydrolysis reaction at the contact portion, and then the polishing solution is mixed with the mechanical polishing assisted by the abrasive grains, so that the portion of the metal filling layer 31 higher than the second stop layer 15, the barrier layer 17 and the third dielectric layer 16 are removed, and the metal plug 30 can form a flat surface under the repeated actions of the chemical reaction and the mechanical polishing. In this embodiment, the second stop layer 15 is used as a chemical mechanical polishing stop layer, so as to ensure that the metal filling layer 31 will not be recessed due to excessive polishing, or the metal plug 30 will be too high due to insufficient wear, so as to ensure high accuracy of the metal plug 30, achieve accurate polishing, and improve the product yield.
In some embodiments, referring to fig. 8, removing the second stop layer 15 in step S112 includes:
step S1121: the second stop layer 15 is removed by a wet etching process such that the top surface of the metal plug 30 is higher than the top surface of the second dielectric layer 14.
As an example, please continue to refer to fig. 8, the second stop layer 15 is removed in step S1121 to avoid the second stop layer 15 affecting the subsequent process.
In some embodiments, please continue to refer to fig. 8, the materials and thicknesses of the first dielectric layer 12 and the second dielectric layer 14 are the same, so that the etching selectivity of the isolation layer 13 and the first dielectric layer 12 and the second dielectric layer 14 adjacent to the isolation layer is the same, and the accuracy of etching the second dielectric layer 14, the isolation layer 13 and the first dielectric layer 12 is further ensured.
In some embodiments, referring to fig. 8, the material of the first stopping layer 11 includes polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron carbon silicon nitride, or combinations thereof, for example, the material of the first stopping layer 11 may be silicon carbonitride; the material of the isolation layer 13 includes fluorosilicone glass, carbon doped silicon oxide, silicon-based polymer material, inorganic porous material, organic porous material, or a combination thereof, the material of the isolation layer 13 is a low dielectric constant material for reducing RC delay, for example, the material of the isolation layer 13 may be a low dielectric constant material based on chemical vapor deposition carbon doped silicon oxide, black Diamond material (Black Diamond 2, bd2); the material of the second stop layer 15 includes polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron carbon silicon nitride, or combinations thereof, for example, the material of the second stop layer 15 is silicon nitride; the material of the barrier layer 17 comprises titanium nitride, tantalum nitride, tungsten nitride, titanium tungsten or combinations thereof, for example, the material of the barrier layer 17 is titanium nitride; the material of the metal filling layer 31 includes copper, tungsten, a copper alloy, a tungsten alloy, or a combination thereof, for example, the material of the metal filling layer 31 is copper.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps in FIG. 1 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
Referring to fig. 8, in still another aspect of the present application, a semiconductor structure 100 is provided, which includes a substrate 10 and a metal plug 30, wherein a first stop layer 11, a first dielectric layer 12, an isolation layer 13 and a second dielectric layer 14 are sequentially stacked along a thickness direction of the substrate 10; the first stop layer 11 is adjacent to the substrate 10; the metal plug 30 penetrates through the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11 in the thickness direction; wherein the bottom surface of the metal plug 30 contacts the top surface of the connection substrate 10.
As an example, please continue to refer to fig. 8, the present embodiment is made by adopting the preparation method of the semiconductor structure, the second stop layer 15 is used as an etching stop layer, the target trench is formed in two steps, the first step firstly removes part of the barrier layer 17 and part of the third dielectric layer 16 on the second stop layer 15 to form the reference trench 211, the width of the target trench 20 is determined, the second step etches the second stop layer 15, the second dielectric layer 14, the isolation layer 13, the first dielectric layer 12 and the first stop layer 11 along the thickness direction via the reference trench 211 to form the target trench 20, after the width of the target trench 20 is determined by the first step of etching, the second step of etching is performed to the thickness direction again, so as to avoid the side wall etching, thereby ensuring that the width of the target trench 20 cannot be enlarged and improving the product accuracy; after forming the metal filling layer 31, the second stopping layer 15 is used as a chemical mechanical polishing stopping layer, only the part of the metal filling layer 31 higher than the second stopping layer 15, the barrier layer 17 and the third dielectric layer 16 are removed, and the remaining metal filling layer 31 forms the metal plug 30, so that excessive polishing or insufficient polishing of the metal plug 30 is avoided, and the product yield is improved through precise polishing. Therefore, the second stop layer 15 of the present embodiment can be used as an etching stop layer to avoid the side wall etching of the target trench 20 by two-step etching, and can also be used as a chemical mechanical polishing stop layer to avoid excessive polishing or insufficient polishing of the metal plug 30, thereby improving the accuracy of the semiconductor structure 100 and the yield of the final product.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the disclosure. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a first stop layer, a first dielectric layer, an isolation layer, a second dielectric layer, a second stop layer, a third dielectric layer and a barrier layer are sequentially laminated on the substrate along the thickness direction of the substrate; the first stop layer is adjacent to the substrate;
removing part of the barrier layer and part of the third dielectric layer to form a reference groove exposing part of the second stop layer;
etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction through the reference trench to form a target trench exposing a part of the substrate;
forming a metal filling layer, wherein the metal filling layer fills the target groove and covers the top surface of the barrier layer;
removing the part of the metal filling layer higher than the second stop layer, the barrier layer and the third dielectric layer, wherein the rest of the metal filling layer forms a metal plug;
removing the second stop layer;
wherein the etching selection ratio of the isolation layer to the second dielectric layer is greater than 1; the etching selection ratio of the isolation layer to the first dielectric layer is greater than 1; the thickness of the isolation layer is larger than that of the second dielectric layer or the first dielectric layer; forming the target trench, comprising:
and etching the second stop layer, the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer along the thickness direction by adopting a dry etching process through the reference groove so as to form the target groove.
2. The method of manufacturing a semiconductor structure of claim 1, wherein a width of the target trench is related to a width of the reference trench.
3. The method of manufacturing a semiconductor structure of claim 1, wherein a thickness of the second stop layer is related to a depth of the target trench.
4. The method of fabricating a semiconductor structure of claim 3, wherein forming the target trench further comprises:
etching the second stop layer, the second dielectric layer, the isolation layer and the first dielectric layer along the thickness direction by adopting a dry etching process through the reference groove so as to form an intermediate groove exposing part of the first stop layer;
a portion of the first stop layer is removed via the intermediate trench to form a target trench exposing a portion of the substrate.
5. The method of fabricating a semiconductor structure of claim 4, wherein forming the target trench further comprises:
and removing part of the first stop layer through the intermediate groove by adopting a wet etching process so as to form a target groove exposing part of the substrate.
6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein the removing the portion of the metal filling layer higher than the second stop layer, the barrier layer and the third dielectric layer comprises:
and removing the part of the metal filling layer higher than the second stop layer, the barrier layer and the third dielectric layer by adopting a chemical mechanical polishing process, wherein the rest of the metal filling layer forms the metal plug.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the removing the second stop layer comprises:
and removing the second stop layer by adopting a wet etching process, so that the top surface of the metal plug is higher than the top surface of the second dielectric layer.
8. The method of manufacturing a semiconductor structure according to any one of claims 3-5, wherein the first dielectric layer and the second dielectric layer are the same in material and thickness.
9. The method of manufacturing a semiconductor structure according to any one of claims 1-5, comprising at least one of the following features:
the material of the first stop layer comprises polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron carbon silicon nitride or combinations thereof;
the material of the isolation layer comprises fluorine-silicon glass, carbon doped silicon oxide, silicon-based high polymer material, inorganic porous material, organic porous material or combination thereof;
the material of the second stop layer comprises polysilicon, aluminum oxide, amorphous silicon, ethyl silicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, boron carbon silicon nitride or combinations thereof;
the material of the barrier layer comprises titanium nitride, tantalum nitride, tungsten nitride, titanium tungsten or a combination thereof;
the material of the metal filling layer comprises copper, tungsten, copper alloy, tungsten alloy or a combination thereof.
10. A semiconductor structure prepared by the method of any one of claims 1-9, comprising:
a substrate, on which a first stop layer, a first dielectric layer, an isolation layer and a second dielectric layer are formed, which are sequentially laminated along the thickness direction of the substrate; the first stop layer is adjacent to the substrate;
a metal plug penetrating through the second dielectric layer, the isolation layer, the first dielectric layer and the first stop layer in the thickness direction; wherein, the bottom surface contact of metal plug connects the top surface of substrate.
CN202311034967.7A 2023-08-17 2023-08-17 Semiconductor structure and preparation method thereof Active CN116759383B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311034967.7A CN116759383B (en) 2023-08-17 2023-08-17 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311034967.7A CN116759383B (en) 2023-08-17 2023-08-17 Semiconductor structure and preparation method thereof

Publications (2)

Publication Number Publication Date
CN116759383A CN116759383A (en) 2023-09-15
CN116759383B true CN116759383B (en) 2023-11-03

Family

ID=87951833

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311034967.7A Active CN116759383B (en) 2023-08-17 2023-08-17 Semiconductor structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116759383B (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444574B1 (en) * 2001-09-06 2002-09-03 Powerchip Semiconductor Corp. Method for forming stepped contact hole for semiconductor devices
KR100790245B1 (en) * 2006-12-07 2008-01-02 동부일렉트로닉스 주식회사 Method for forming metal wire in semiconductr device
CN103107125A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
CN106206283A (en) * 2016-07-27 2016-12-07 上海华虹宏力半导体制造有限公司 Groove etching method and the first metal layer manufacture method
CN109545774A (en) * 2018-11-21 2019-03-29 德淮半导体有限公司 Semiconductor devices and forming method thereof
CN110931423A (en) * 2018-09-20 2020-03-27 芯恩（青岛）集成电路有限公司 Semiconductor interconnection structure and preparation method thereof
CN110943070A (en) * 2018-09-21 2020-03-31 长鑫存储技术有限公司 Semiconductor structure, semiconductor structure preparation method and application thereof
WO2022012336A1 (en) * 2020-07-14 2022-01-20 长鑫存储技术有限公司 Semiconductor structure manufacturing method
CN114078752A (en) * 2020-08-21 2022-02-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
WO2022205675A1 (en) * 2021-03-31 2022-10-06 长鑫存储技术有限公司 Method for preparing semiconductor structure, and semiconductor structure
CN115483159A (en) * 2021-05-31 2022-12-16 长鑫存储技术有限公司 Method for manufacturing semiconductor structure
CN115632039A (en) * 2022-10-13 2023-01-20 杭州富芯半导体有限公司 Method for manufacturing semiconductor structure
CN116314007A (en) * 2021-12-06 2023-06-23 芯恩（青岛）集成电路有限公司 Method for preparing semiconductor device with dual damascene structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927413B2 (en) * 2012-11-12 2015-01-06 Taiwan Semiconductor Manufacturing, Ltd. Semiconductor structure and semiconductor fabricating process for the same

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444574B1 (en) * 2001-09-06 2002-09-03 Powerchip Semiconductor Corp. Method for forming stepped contact hole for semiconductor devices
KR100790245B1 (en) * 2006-12-07 2008-01-02 동부일렉트로닉스 주식회사 Method for forming metal wire in semiconductr device
CN103107125A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
CN106206283A (en) * 2016-07-27 2016-12-07 上海华虹宏力半导体制造有限公司 Groove etching method and the first metal layer manufacture method
CN110931423A (en) * 2018-09-20 2020-03-27 芯恩（青岛）集成电路有限公司 Semiconductor interconnection structure and preparation method thereof
CN110943070A (en) * 2018-09-21 2020-03-31 长鑫存储技术有限公司 Semiconductor structure, semiconductor structure preparation method and application thereof
CN109545774A (en) * 2018-11-21 2019-03-29 德淮半导体有限公司 Semiconductor devices and forming method thereof
WO2022012336A1 (en) * 2020-07-14 2022-01-20 长鑫存储技术有限公司 Semiconductor structure manufacturing method
CN114078752A (en) * 2020-08-21 2022-02-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
WO2022205675A1 (en) * 2021-03-31 2022-10-06 长鑫存储技术有限公司 Method for preparing semiconductor structure, and semiconductor structure
CN115483159A (en) * 2021-05-31 2022-12-16 长鑫存储技术有限公司 Method for manufacturing semiconductor structure
CN116314007A (en) * 2021-12-06 2023-06-23 芯恩（青岛）集成电路有限公司 Method for preparing semiconductor device with dual damascene structure
CN115632039A (en) * 2022-10-13 2023-01-20 杭州富芯半导体有限公司 Method for manufacturing semiconductor structure

Also Published As

Publication number Publication date
CN116759383A (en) 2023-09-15

Similar Documents

Publication Publication Date Title
KR100279016B1 (en) Method of Planarizing Non-Conformal Device Layers in Semiconductor Manufacturing
US10937694B2 (en) Chamferless via structures
CN102412140B (en) Non-uniformity reduction in semiconductor planarization
US20020065023A1 (en) Multilayered CMP stop for flat planarization
US7678696B2 (en) Method of making through wafer vias
TWI699865B (en) Middle of line structures
KR20200123058A (en) Structures and methods for noise isolation in semiconductor devices
CN113035770B (en) Semiconductor structure and manufacturing method thereof
US10276378B1 (en) Method of forming funnel-like opening for semiconductor device structure
US7786017B1 (en) Utilizing inverse reactive ion etching lag in double patterning contact formation
CN110323181B (en) Method for manufacturing semiconductor device
US20090072400A1 (en) Contact forming in two portions and contact so formed
CN109119470B (en) Boundary spacer structure and integration
CN116759383B (en) Semiconductor structure and preparation method thereof
CN110071091B (en) Contact structure
US20090098702A1 (en) Method to Form CMOS Circuits Using Optimized Sidewalls
US11929280B2 (en) Contact window structure and method for forming contact window structure
CN112397519B (en) Semiconductor device and preparation method thereof
US11776845B2 (en) Semiconductor arrangement and method of making
CN114256136B (en) Contact window structure, metal plug, forming method of metal plug and semiconductor structure
US11488820B2 (en) Method of fabricating layered structure
US10930549B2 (en) Cap structure
US6559028B1 (en) Method of topography management in semiconductor formation
US6489193B1 (en) Process for device isolation
CN114256134A (en) Contact window structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant