CN105529328B - DRAM device and forming method thereof - Google Patents
DRAM device and forming method thereof Download PDFInfo
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- CN105529328B CN105529328B CN201410513692.XA CN201410513692A CN105529328B CN 105529328 B CN105529328 B CN 105529328B CN 201410513692 A CN201410513692 A CN 201410513692A CN 105529328 B CN105529328 B CN 105529328B
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Abstract
The present invention provides a kind of DRAM device and forming method thereof, and wherein the forming method of DRAM device includes：Substrate is provided；Form first grid and second grid；Source electrode or the drain electrode of the logic transistor and channel transistor are formed, dielectric layer is formed and capacitor is collectively formed with the source electrode or drain electrode with channel transistor in metal layer, dielectric layer.DRAM device includes：Substrate, channel transistor, capacitor and logic transistor, transistor source perhaps drain on be sequentially formed with dielectric layer and metal layer source electrode or drain electrode, the dielectric layer and the metal layer for constituting capacitor.The beneficial effects of the present invention are, cross the capacitor for forming dielectric layer and metal layer on the source electrode of channel transistor or drain electrode to form memory device, it does not need specially to form deep trench in the substrate as the prior art to form capacitor, manufacturing process is simplified, manufacture difficulty and more preferable with the compatibility of conventionally fabricated process is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of DRAM device and forming method thereof.
Background technique
With the continuous development of semiconductor industry, the ground of the occupied ever more important of semiconductor devices with store function
Position.By taking dynamic random access memory (Dynamic Random Access Memory, DRAM) as an example, burying in DRAM classification
Enter formula DRAM (embedded DRAM, eDRAM) because it is with higher service speed and integrated level, is gradually used
In market.
But since the production process of eDRAM device is more many and diverse and production work with existing conventional semiconductor devices
Skill poor compatibility needs to expend more manpower and material resources when making this kind of devices.On the other hand, even if eDRAM device
Performance is promoted compared to traditional memory device, and with the development of the market demand, there is still a need for further for the performance of eDRAM device
It improves.
Therefore, how to simplify the production process of eDRAM device, and promote the performance of eDRAM device, become art technology
Personnel's one of the technical problems that are urgent to solve.
Summary of the invention
Problems solved by the invention is by providing a kind of DRAM device and forming method thereof, to simplify the system of DRAM device
Make process and promotes the performance of DRAM device.
To solve the above problems, the present invention provides a kind of forming method of DRAM device, including：
Substrate is provided, the substrate includes memory device area and at least one logic device area；
First grid and second grid are respectively formed in the logic device area of the substrate and memory device area；
Second grid in the substrate of the first grid two sides in the logic device area and memory device area respectively
Two sides substrate in formed recess, the encapsulant layer in the recess, to be respectively formed the logic transistor and channel
The source electrode of transistor or drain electrode；
Dielectric layer and metal layer, the dielectric are sequentially formed on the source electrode of the channel transistor or drain electrode
Layer, the source electrode of metal layer and the channel transistor or drain electrode are for constituting capacitor.
Optionally, the step of providing substrate include：
Semiconductor base is provided；
Insulating layer is formed on the semiconductor base；
It is formed on the insulating layer semiconductor layer.
Optionally, it forms first grid and the step of second grid includes：
The first grid and second grid are respectively the first pseudo- grid and the second pseudo- grid；
After the step of being respectively formed source electrode or the drain electrode of the logic transistor and channel transistor, the formation side
Method further includes：
The described first pseudo- grid and the second pseudo- grid are removed, and form the first gold medal in the position of the described first pseudo- grid and the second pseudo- grid
Belong to grid and the second metal gates.
Optionally, the pseudo- grid of removal first and the step of the second pseudo- grid, include：
The dielectric layer for covering the first grid and second grid is formed over the substrate；
Planarizing the dielectric layer exposes the first grid and second grid from the dielectric layer；
The part dielectric layer is removed, to expose one of the source electrode and drain electrode of the channel transistor；
Etching is to remove the first grid and second grid, to form the first opening and second in the dielectric layer
Opening；
The step of forming first metal gates and the second metal gates include：
In the source electrode or drain surface of first opening, the second open bottom and the channel transistor of the exposing
Formed dielectric substance, wherein positioned at first opening, the second open bottom dielectric substance be respectively the first grid and
The dielectric substance of the gate dielectric layer of second grid, source electrode or drain surface in the memory device area of the exposing is
The dielectric layer of the capacitor；
Metal material layer is formed in first opening, the second opening and on the dielectric layer, wherein being located at the
Metal material layer in one opening, the second opening forms first metal gates and the second metal gates, is located at the electricity and is situated between
Metal material layer on matter layer forms the metal layer of the capacitor.
Optionally, the dielectric substance is high K dielectric material.
Optionally, the step of formation metal material layer includes：
It is described first opening, second opening in and expose channel transistor source electrode or drain surface form gold
Belong to material layer, planarize the metal material layer, makes surface and the first grid and second of the metal layer of the capacitor
The surface of grid flushes.
Optionally, after the step of substrate is provided, form first grid and the step of second grid before, the formation
Method further includes：The forming method further includes：
The part for being located at logic device area and memory device area to the substrate is doped.
Optionally, the step of part for being located at logic device area and memory device area to substrate is doped include：
It is gradually reduced the doping concentration of Doped ions in the substrate from substrate surface to substrate center.
Optionally, in the step of forming source electrode or the drain electrode of the logic transistor and channel transistor,
The material layer filled in the recess is metal.
Optionally, the step of forming source electrode or the drain electrode of the logic transistor and channel transistor further include：To gold
Category is made annealing treatment.
Optionally, the metal layer of the capacitor is tungsten or aluminum metal layer.
Optionally, the thickness of the dielectric layer of the capacitor is in the range of 1.5 nanometers~3 nanometers.
In addition, also a kind of DRAM device of the present invention, including：
Substrate, the substrate include memory device area and at least one logic device area；
Channel transistor and capacitor in the memory device area of the substrate and it is located at the logic device area
In logic transistor, wherein the source electrode and drain electrode of the channel transistor and logic transistor is located in the substrate, institute
The grid for stating logic transistor and channel transistor is metal gates；
Dielectric layer and metal layer, the channel transistor are sequentially formed in the channel transistor source electrode or drain electrode
Source electrode or drain electrode, the dielectric layer and the metal layer for constituting capacitor.
Optionally, the material of the source electrode and drain electrode of the logic transistor and channel transistor is metal or contains
The material of metal.
Optionally, the metal layer of the capacitor is tungsten metal layer or aluminum metal layer.
Optionally, the thickness of the dielectric layer of the capacitor is in the range of 1.5 nanometers~3 nanometers.
Optionally, the gate surface of the layer on surface of metal of the capacitor and the logic transistor and channel transistor
It flushes.
Compared with prior art, technical solution of the present invention has the following advantages that：
The present invention forms logic transistor (logic in the logic device area of substrate and memory device area
Transistor) and channel transistor (pass transistor), and on the source electrode of the channel transistor or drain electrode according to
Secondary formation dielectric layer and metal layer, the dielectric layer, the source electrode of metal layer and the channel transistor or drain electrode are altogether
With capacitor is formed, the capacitor and the channel transistor are collectively formed memory device, are initially formed capacitor with the prior art
The mode of device is compared, production process of the invention by formed on the source electrode of channel transistor or drain electrode dielectric layer and
Metal layer forms the capacitor of memory device, that is to say, that the source electrode of the channel transistor or drain electrode be also used as capacitor
A part of device, the present invention do not need as the prior art it is special form deep trench in the substrate to form capacitor, due to
Device size is smaller and smaller, and the also larger therefore of the invention method of difficulty of the prior art when forming deep trench is in certain journey
Manufacture difficulty is reduced on degree.
In addition, the present invention more compatible conventional process on production process compared with the existing technology, because the prior art exists
Deep trench is just needed to form after forming substrate, that is to say, that in actual operation, is needed to break old process and is additionally added together
The step of making deep trench.In contrast, the present invention does not need and increases step outside, and it is brilliant only need to make logic according to old process
Then body pipe and channel transistor form dielectric layer on the source electrode of channel transistor or drain electrode and metal layer can
The capacitor for forming memory device, it is more preferable with the compatibility of old process.
Further, it when channel transistor or logic transistor turn off, since electric field strength and distance are inversely proportional, and mixes
The more big then electric field strength of miscellaneous area's surface distance is smaller, and then is not easy to be depleted with the biggish carrier of doped region surface distance；
The present invention is gradually reduced doping concentration from substrate surface to substrate center, and reduces with channel region upper surface apart from biggish
The quantity of carrier can be such that the carrier in doped region is depleted as best one can in this way, and then reduce the road transistor to be formed
And the probability to leak electricity when logic transistor shutdown.
Further, make the doping type for the source electrode and drain electrode to be formed identical as the doping type of substrate, and then formed without knot
Channel transistor and without knot logic transistor, compared with the existing technology in PN junction transistor, it is of the invention without knot channel crystal
Pipe is with logic transistor due to consistent with substrate doping type, and doping is relatively more easy, and nodeless mesh body pipe can inhibit short
Channelling effect still can work under several nano-scales, this is conducive to the performance for promoting device.
It further, is respectively the first grid and the in the dielectric substance for being located at the first opening, the second open bottom
The dielectric substance of the gate dielectric layer of two grids, source electrode or drain surface in the memory device area of the exposing is institute
The dielectric layer of capacitor is stated, is just capable of forming the dielectric layer of capacitor while forming the gate dielectric layer of grid in this way；
Then, metal material layer is formed in first opening, the second opening and on the dielectric layer, is opened wherein being located at first
Metal material layer in mouth, the second opening forms the first grid and second grid, the metal on the dielectric layer
Material layer forms the metal layer of the capacitor, is capable of forming the metal layer of capacitor while forming grid in this way, is not necessarily to
Processing step is additionally set like that the prior art and forms capacitor, that is to say, that conventional production process will not be broken, had
Preferable compatibility.
Detailed description of the invention
Fig. 1 to Figure 10 is the structural schematic diagram of each step in one embodiment of forming method of DRAM device of the present invention.
Specific embodiment
In the prior art make eDRAM device process it is comparatively laborious, reason first is that due to eDRAM device need exist
Capacitor arrangement is added in transistor, and is that etching forms a deep trench on substrate by the way of in the prior art
(deep trench), then sequentially forms semiconductor layer, dielectric layer and semiconductor layer in deep trench, described so partly to lead
Body layer, dielectric layer and semiconductor layer just form the capacitor；After the capacitors are formed, patrolling for eDRAM device is re-formed
Collect part and storage section, such as grid, source-drain electrode.But the normal flow path difference of this method and existing manufacture semiconductor
It is not larger, it is in the prior art because old process is usually to carry out according to substrate-grid-source-drain electrode key step
Manufacturing method means to additionally increase the process for forming capacitor after the step of forming substrate, that is to say, that existing
The process and conventional flowsheet poor compatibility of eDRAM device are formed, this, which will lead to entire manufacture craft, becomes complicated and cumbersome,
Production progress is also affected.
On the other hand, since the capacitor for making eDRAM device in the prior art needs to form deep trench, in semiconductor device
Under the trend that part characteristic size is gradually reduced, forms deep trench and cover the difficulty of a variety of materials layer also more in deep trench
Increase, not only technology difficulty increases, and the effect of covering a variety of materials layer may be also not ideal enough, this can be to a certain extent to device
Part makes yield, the performance of device itself impacts.
For this purpose, the present invention provides a kind of forming method of DRAM device, include the following steps：
Substrate is provided, the substrate includes memory device area and at least one logic device area；In patrolling for the substrate
It collects in device region and memory device area and is respectively formed first grid and second grid；Respectively in the logic device area
Recess is formed in the substrate of the two sides of the substrate of first pseudo- grid two sides and the second pseudo- grid in memory device area, described recessed
Encapsulant layer in falling into, to form source electrode or the drain electrode of the logic transistor and channel transistor；Remove the first grid
Pole and second grid；The first metal gates and the second gold medal are respectively formed in the position of the first grid and second grid
Belong to grid, and then is respectively formed logic transistor and channel transistor in the logic device area of substrate and memory device area；
Dielectric layer and metal layer, the dielectric layer, metal are sequentially formed on the source electrode of the channel transistor or drain electrode
Layer is constituted with the source electrode of the channel transistor or drain electrode for constituting capacitor, the capacitor and the channel transistor
Memory device.
Through the above steps, production process of the invention is situated between by forming electricity on the source electrode of channel transistor or drain electrode
Matter layer and metal layer form the capacitor of memory device, do not need specially to form zanjon in the substrate as the prior art
Slot forms capacitor, and since device size is smaller and smaller, difficulty of the prior art when forming deep trench is also larger, therefore this
The method of invention reduces manufacture difficulty to a certain extent.Also, the present invention compared with the existing technology on production process more
Add compatible conventional process, because the prior art just needs to form deep trench after forming substrate, that is to say, that in practical operation
In, need to break the step of old process additionally adds production deep trench together.In contrast, the present invention does not need and increases outside
Step only need to make logic transistor and channel transistor according to old process, then in the source electrode of channel transistor or leakage
Dielectric layer and metal layer are formed on extremely can form the capacitor of memory device, more preferable with the compatibility of old process.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the structural schematic diagram of each step in one embodiment of forming method of DRAM device of the present invention.
Channel transistor without junction type (junctionless) of the present embodiment to form planar structure and patrolling without junction type
For volume transistor.
Referring initially to Fig. 1, substrate is provided, the substrate includes memory device area 20 and at least one logic device area
10, memory device area 20 and logic device area 10 are respectively used to form memory device and logic crystal in subsequent steps
Pipe.
In the present embodiment, the substrate is the lining of silicon on insulated substrate (Silicon On Insulator, SOI)
Bottom, specifically, the step of substrate is provided include it is following step by step：
Semiconductor base 100 is provided；In the present embodiment, the semiconductor base 100 is silicon base；
Insulating layer 110 is formed on the semiconductor base 100；In the present embodiment, the insulating layer 110 can be two
Silica material；
Semiconductor layer 120 is formed on the semiconductor base 100；The semiconductor layer 120 is used in subsequent step shape
At memory device and logic transistor.
In the present embodiment, the material of the semiconductor layer 120 is silicon.
It should be noted that semiconductor layer 120 in the present embodiment Fig. 1 is separated, it is formed in breaking part
Such as the other structures such as isolation structure.But the present invention is not construed as limiting to whether the semiconductor layer 120 has to be off.
In the present embodiment, it after forming semiconductor layer 120, is formed before logic transistor and channel transistor, also
The part for being located at logic device area 10 and memory device area 20 to the substrate is doped, and is specifically partly led to described
Body floor 120 is located at logic device area 10 and the part in memory device area 20 is doped, and then forms doped region.
The present embodiment carries out N-shaped ion for forming N-shaped flush type DRAM device, therefore to the semiconductor layer 120
Doping.
The doping concentration of the substrate Doped ions is gradually reduced from substrate surface to substrate center when carrying out adulterated,
More specifically, it is gradually reduced the doping concentration of Doped ions in semiconductor layer 120 from substrate surface to substrate center, in this way
Be conducive to the shutdown of the logic transistor being subsequently formed and channel transistor, and then reduce electric leakage degree.The reason is that logical
When road transistor or logic transistor turn off, since electric field strength and distance are inversely proportional, with doped region surface distance more it is big then
Electric field strength is smaller, and then is not easy to be depleted with the biggish carrier of doped region surface distance；The present invention make doping concentration from
Substrate (in the present embodiment be semiconductor layer 120) surface is gradually reduced to substrate center, and reduce with channel region upper surface away from
Quantity from biggish carrier can be such that the carrier in doped region is depleted as best one can in this way, and then reduce to be formed
The probability that road transistor and logic transistor leak electricity when turning off.
Then referring to Fig. 2, the first grid is respectively formed in the logic device area 10 of the substrate and memory device area 20
Pole and second grid.
The present embodiment forms the channel transistor and logic transistor using rear grid technique.Specifically, first in logic
Respective grid oxide layer 131 is respectively formed on device region and the semiconductor layer in memory device area 20 120, then on grid oxide layer 131
It is respectively formed the pseudo- grid 130a of the first puppet grid 130b and second.
Specifically, the pseudo- grid 130a of the first puppet grid 130b and second can be while described using polysilicon as material
Grid oxide layer 131 can be using silica as material.It is herein the prior art, the present invention does not repeat this, while also not
It is limited in any way.
Furthermore it should be noted that forming a pseudo- grid in the present embodiment in the memory device area 20, that is to say, that
It only include a grid in the channel transistor formed in the next steps.But in other embodiments of the invention, described
Channel transistor is also possible to two or more grids, is also formed in memory device area 20 in this step accordingly corresponding
The pseudo- grid 130a of first puppet grid 130b of quantity and second.
In addition, the present invention is also not construed as limiting the gate shapes of the channel transistor, the shape of the grid can be with
Three face rings around the semiconductor layer 120 Ω grid (Omega gate) or loopful around the semiconductor layer 120 column
Shape grid (cylindrical gate), this is not limited by the present invention.Correspondingly, this step is in forming memory device area 20
Pseudo- grid when can also form corresponding shape.
Lining referring next to Fig. 3, in the grid two sides being formed in the logic device area 10 and memory device area 20
Bottom was respectively formed before the step of source electrode and drain electrode, and the present embodiment is first being located at the logic device area 10 and storage
The side wall of the pseudo- grid 130a of the first puppet grid 130b and second in device region 20 forms side wall 132, and the side wall 132 can subtract
The influence of the source electrode, drain electrode grid 130a pseudo- to the first puppet grid 130b and second that are subsequently formed less, also helps in subsequent step
Except the pseudo- grid 130a of the first puppet grid 130b and second.
Specifically, in the present embodiment, the side wall 132 can be formed by the way of chemical vapor deposition, it is this
The gradient coating performance for the side wall 132 that mode is formed is preferable.
It should be noted that in the present embodiment, being also formed with side wall 122 in the side wall of the semiconductor layer 120, still
This will not influence implementation of the invention.
After forming the side wall 122,132, in the logic device area 10 and memory device area 20 first
It is respectively formed source electrode or drain electrode (on the semiconductor layer 120 namely in the present embodiment) in the substrate of the two sides of pseudo- grid 130b,
And recess is formed (on the semiconductor layer 120 namely in the present embodiment) in the substrate of the second puppet two sides grid 130a, described
Encapsulant layer in recess, to be respectively formed source electrode or the drain electrode of the logic transistor and channel transistor.
In the present embodiment, it is silicon semiconductor layer by semiconductor layer 120 in this present embodiment, metal silicide can be formed
The source electrode and drain electrode of material.
The source and drain of metal silicide materials is highly advantageous to the contact resistance reduced between the conductive plunger that is subsequently formed, and
Without reducing the contact between source-drain electrode and conductive plunger as being additionally formed one layer of suicide contact layer in the prior art
Resistance.In addition, the resistance between the source-drain electrode of metal silicide materials can also become smaller to a certain extent, it means that same
Under the cut-in voltage of sample, firing current becomes larger, this is conducive to improve logic transistor and channel transistor to a certain extent
Performance, for example, improving the electric leakage degree etc. of logic transistor and channel transistor when off under working condition.
Specifically, with reference to Fig. 4, the step of the present embodiment forms source electrode or the drain electrode of the metal silicide materials packet
It includes：
The substrate of the first puppet two sides grid 130b in the logic device area 10 and in memory device area 20 second
Recess 40 is formed in the substrate of the two sides of pseudo- grid 130a；The position of the recess 40 is the logic transistor being subsequently formed and channel
The position of the respective source-drain electrode of transistor.
In the present embodiment, the recess 40 can be formed by the way of etching；Simultaneously as in the first pseudo- grid
130b, the second pseudo- grid 130a side wall are formed with side wall 132, and the side wall 132 can be used as the described first pseudo- grid 130b, the second puppet
The etching stop layer of grid 130a.
After this, with reference to Fig. 5, metal 140a, 140b, 150a, 150b, the metal are filled in the recess 40
140a, 140b, 150a, 150b with part of semiconductor layer 120 for reacting to form the metal silicide material in the next steps
The source-drain electrode of material；
In the present embodiment, described metal 140a, 140b, 150a, 150b can be aluminium, tungsten, copper or titanium etc., these gold
Category can be reacted with the semiconductor layer 120 of silicon materials in the present embodiment to form the source-drain electrode of metal silicide materials.
With reference to Fig. 6, described metal 140a, 140b, 150a, 150b and semiconductor layer 120 are made annealing treatment, so that
Described metal 140a, 140b, 150a, 150b and part of semiconductor layer 120 be changed into metal silicide materials source electrode 141a,
151a and drain electrode 141b, 151b.The source electrode 151a and drain electrode 151b is the source-drain electrode for the logic transistor being subsequently formed,
The source electrode 141a and drain electrode 141b is the source-drain electrode for the channel transistor being subsequently formed.
Since the source-drain electrode of formation is the source-drain electrode of metal silicide materials, there is no p-types to mix between source electrode, drain electrode
It is miscellaneous, n-type doping point, thus logic transistor and channel transistor that the present embodiment is formed be logic transistor without junction type and
Without junction type channel transistor.
Forming the channel transistor without junction type and the logic transistor without junction type is advantageous in that, further due to device
It reduces, so that the area of source-drain electrode and channel region reduces, the control when forming traditional PN junction transistor, to source-drain electrode doping
Difficulty processed increases, and realizes that the PN junction between source electrode, drain electrode and channel region becomes more and more difficult.Source electrode in the present embodiment,
Drain electrode is consistent with channel region doping type to be conducive to reduce doping difficulty, while can also inhibit short-channel effect, several
It still can work under nano-scale.
After forming described source electrode 141a, 151a and drain electrode 141b, 151b, remove the first puppet grid 130b and
Second pseudo- grid 130a, to provide condition to be subsequently formed first grid and second grid.
Refering to what is shown in Fig. 7, in the present embodiment, it includes following for removing the first puppet grid 130b and the second puppet grid 130a
Step：
The dielectric layer 200 for covering the pseudo- grid 130a of the first puppet grid 130b and second is formed over the substrate
The dielectric layer 200 is planarized, makes the first puppet grid 130b and the second puppet grid 130a from the dielectric layer 200
Expose, in order to remove the pseudo- grid 130a of the first puppet grid 130b and second in subsequent step.
In the specific implementation, the dielectric layer 200 can be planarized, and by the way of chemical mechanical grinding to detect
The polycrystalline silicon material of the pseudo- grid 130a of the first puppet grid 130b and second is grinding stop signal, is being ground to the first pseudo- grid
Stop grinding when the puppet grid 130a of 130b and second, so reach it is above-mentioned make the first puppet grid 130b and the second puppet grid 130a from
The purpose exposed in dielectric layer 200.
With continued reference to Fig. 7, make the first puppet grid 130b and the second puppet grid 130a from 200 exposing of dielectric layer
Afterwards, the present embodiment also remove certain media floor 200 with expose the source electrode and drain electrode 140 in the memory device area 20 wherein it
One (in the present embodiment expose source electrode 140a), the purpose of this step are to expose the source electrode 140a so as to be subsequently formed electricity
The step of container provides condition, forms capacitor will be illustrated in further part.
It, in the present embodiment, also will be from dielectric layer due to being also formed with side wall 122 in the side wall of the semiconductor layer 120
The side wall 122 of 200 120 side walls of semiconductor layer exposed removes (side wall of the semiconductor layer 120 on the right side of Fig. 7) together,
In this way when being subsequently formed the capacitor, semiconductor layer 120 of this part can also dielectric layer, metal layer with formation
It is formed together capacitor, that is to say, that the capacitor of formation is not only the source electrode or drain electrode and dielectric of channel transistor
The capacitor that layer, metal layer are collectively formed further includes the capacitor that semiconductor layer 120 and dielectric layer, metal layer are formed, in this way
The capacitance of capacitor can be increased.
But the source electrode 140a due to channel transistor and dielectric layer, metal layer can form capacitor, thus
Whether the present invention is to must remove the side wall 122 of 120 side wall of semiconductor layer and be not construed as limiting.
With reference to Fig. 8, etching is to remove the pseudo- grid 130a of the first puppet grid 130b and second, with the shape in the dielectric layer
At the first opening 50 and the second opening 51.
In addition, will also be located in the grid oxide layer 131 below the pseudo- grid 130a of the first puppet grid 130b and second in the present embodiment
Removal, and then condition is provided to be subsequently formed grid.
It in the present embodiment, further include following step before being respectively formed grid in the first opening 50 and the second opening 51
Suddenly：
With reference to Fig. 9, in 50, second 51 bottoms of opening of the first opening and the source electrode of the channel transistor of the exposing
Or drain surface forms dielectric substance, wherein the dielectric substance difference positioned at the first 51 bottoms of the 50, second opening of opening
Gate dielectric layer 144 for the first grid and second grid that are subsequently formed, in the memory device area 20 of the exposing, from institute
The source electrode for stating the exposing of dielectric layer 200 or drain electrode are (as it was noted above, be the dielectric material on the surface source electrode 140a) in the present embodiment
Material is the dielectric layer 170 of the capacitor.
It specifically, can be first in first the 50, second opening 51 of opening, the source electrode of 200 surface of dielectric layer and exposing
Dielectric substance is formed on 140a, then etch away sections dielectric substance, only retain and above-mentioned be located at the first opening 50, second
Be open 51 bottoms and exposing the surface source electrode 140a dielectric substance.
Wherein, the dielectric substance positioned at the first 51 bottoms of the 50, second opening of opening is respectively the first grid and the
The gate dielectric layer 144 of two grids, source electrode or drain electrode in the memory device area 20 of the exposing (are source in the present embodiment
Pole 141a) surface dielectric substance be the capacitor dielectric layer 170.Forming first opening 50, the in this way
The dielectric layer 170 of capacitor is also formed while gate dielectric layer 144 in two openings 51, does not need specially to be arranged additional
Step forms the dielectric layer of capacitor, it is only necessary to change mask pattern when etching removal part dielectric substance,
Simpler convenience compared with the existing technology.
In the present embodiment, the thickness of the dielectric layer 170 of the capacitor is in the range of 1.5 nanometers~3 nanometers, but
It is this numberical range is only that the present embodiment is used, specific thickness should be adjusted according to the actual situation.In general, electricity is situated between
The thickness of matter layer 170 is smaller to be more conducive to increase the capacitance for forming capacitor.
In the present embodiment, the dielectric substance can be formed using hafnium, on the one hand, the dielectric of hafnium
Material means that the gate dielectric layer 144 to be formed is also hafnium, this can increase the logic transistor being subsequently formed and channel is brilliant
The grid-control ability of grid in body pipe；On the other hand, the dielectric substance of hafnium means that the dielectric layer of capacitor is also high
K material, according to the capacitance principle directly proportional to k value, this can increase the capacitance to form capacitor.
Specifically, in the present embodiment, the high-k dielectrics material can use such as LaO, AlO, BaZrO, HfZrO,
HfZrON、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、(BaSr)TiO3(BST)、Al2O3、Si3N4,
Or nitrogen oxides, as material, this is not limited by the present invention.
In conjunction with reference Figure 10, in the position of the pseudo- grid 130a of the first puppet grid 130b and second, that is, described first is opened
First grid 133 and second grid 134 are formed in mouth 50 and the second opening 51, to be respectively formed the channel transistor and logic
Transistor.
In the present embodiment, the first grid 133 and second grid of semiconductor material or metal material can be formed
134。
Specifically, metal can be formed in 50, second opening 51 of the first opening and on the dielectric layer 170
Material layer, wherein the metal material layer in first the 50, second opening 51 of opening forms the first grid 133 and second
Grid 134, and then be respectively formed the logic transistor in the logic device area of substrate 10 and memory device area 20 and lead to
Road transistor.Meanwhile the metal material layer on the dielectric layer 170 forms the metal layer 160 of the capacitor；It is described
The source electrode 141a of 170 lower section of metal layer 160, dielectric layer 170 and dielectric layer collectively forms the capacitor of memory device.
The capacitor and the channel transistor collectively constitute the memory device in the DRAM device.
170 He of source electrode 141a and dielectric layer since capacitor is by metal silicide materials, that is, containing metal
Metal layer 160 forms, and then constitutes the capacitor of MIM (metal-insulator-metal) structure.
The present embodiment can form the capacitor while forming the grid of the logic transistor and channel transistor
The metal layer 160 of device specially increases several steps compared with the existing technology and is formed without additionally increasing the step of forming capacitor
The mode of capacitor, the present invention are easier.
Specifically, the gold of the first grid 133, second grid 134 and capacitor can be formed in the following manner
Belong to layer 160：
It is described first opening 50, second opening 51 in, dielectric layer 200 and expose channel transistor source electrode or
Person's drain electrode (being source electrode 140a in the present embodiment) surface forms metal material layer, then planarizes the metal material layer, makes institute
The surface for stating the metal layer of capacitor is flushed with the surface of the first grid and second grid (with reference to shown in Figure 10), in this way may be used
To remove the metal material layer of redundance, remaining metal material layer just forms the first grid 133, second grid 134
And metal layer 160.
In the present embodiment, the metal layer of the capacitor is tungsten metal layer or aluminum metal layer.But the present invention is to this
It is not construed as limiting.
After this, the present embodiment further includes the dielectric layer 200 that removal is formed on logic transistor and channel transistor,
Then the components such as conductive plunger are formed on the source-drain electrode on logic transistor and channel transistor.As it was noted above, by institute
It states and is formed with metal silicide layer 141,151 on source-drain electrode, the metal silicide layer 141,151 can reduce source-drain electrode and lead
Contact resistance between electric plug.
In addition, the present invention also provides another embodiment of the forming method, the difference of the present embodiment and a upper embodiment
The step of being, being respectively formed source electrode or the drain electrode of the logic transistor and channel transistor includes：
The substrate of the first puppet two sides grid 130b in the logic device area and the second pseudo- grid in memory device area
Recess is formed in the substrate of the two sides of 130a；
After this, metal is filled in the recess, to form the source electrode of the logic transistor and channel transistor
Or drain electrode, that is to say, that the material of the source electrode or drain electrode of the logic transistor and channel transistor is metal.
It specifically, can be using selective chemical vapor deposition (selective CVD), described recessed in the present embodiment
Metal is filled in falling into.Since during the deposition process, pre-reaction material is less than in the reaction rate of non-growth surface in growing surface
The reaction rate of (side wall of recess and bottom), the in this way property of can choose the material layer is formed in the valley.So this
Kind generation type can deposit forming material layer in the case where not forming mask, and have preferable stepcoverage performance.
Further, it is possible to using Metalorganic chemical vapor deposition (Metal Organic Chemical Vapor
Deposition, MOCVD) mode metal is filled in the recess, the step coverage of this mode is more preferable, can be compared with
Good is covered in the recess.
It in the present embodiment, can be using aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, tantalum carbide or alloy material etc.
Form source electrode or the drain electrode of metal.But this is not limited by the present invention, the source of the logic transistor and channel transistor
The material of pole or drain electrode is also possible to semiconductor material.
In addition, with reference to Figure 10, being wrapped described in the DRAM device in the present embodiment the present invention also provides a kind of DRAM device
It includes：
Substrate, the substrate include memory device area 20 and at least one logic device area 10；
Channel transistor and capacitor in the memory device area 20 of the substrate and it is located at the logical device
Logic transistor in area 10；
The source electrode and drain electrode of the channel transistor and logic transistor is located in the substrate, the logic transistor
And the grid of channel transistor is metal gates；
Dielectric layer 170 and metal layer 160, the channel are sequentially formed in the channel transistor source electrode or drain electrode
The source electrode of transistor or drain electrode (being source electrode 140a in the present embodiment), the dielectric layer 170 and the metal layer 160 are used
In composition capacitor.
In the present embodiment, source electrode 150a, 140a of the logic transistor and channel transistor and drain electrode 150b,
140b is metal or the source electrode and drain electrode containing metal, and p-type doping, n-type doping are not present between such source electrode, drain electrode
Point, so logic transistor and channel transistor that the present embodiment is formed are logic transistor without junction type and without junction type channel
Transistor.Due to further reducing for device, so that the area of source and drain and channel region reduces, traditional PN junction crystal is being formed
Guan Shi increases the control difficulty of source electrode, drain implants, realizes that the PN junction between source electrode, drain electrode and channel region becomes more next
It is more difficult.Source electrode, drain electrode in the present embodiment are consistent with channel region doping type to be conducive to reduce doping difficulty, while may be used also
To inhibit short-channel effect, still can work under several nano-scales.
In the present embodiment, the grid 133,134 of the logic transistor and channel transistor is metal gates, in this way
It can be formed with the metal layer 160 for forming capacitor in same step, this is conducive to simplify formation process.
In the present embodiment, the metal layer for constituting the capacitor is tungsten metal layer or aluminum metal layer.
In the present embodiment, the thickness of the dielectric layer 170 of the capacitor is in the range of 1.5 nanometers~3 nanometers.But
It is this numberical range is only that the present embodiment is used, specific thickness should be adjusted according to the actual situation.In general, electricity is situated between
The thickness of matter layer 170 is smaller, and the capacitance of the capacitor is bigger.
In the present embodiment, the surface of the metal layer 160 of the capacitor and the logic transistor and channel crystal
The surface of the grid 133,134 of pipe flushes.
Furthermore it should be noted that DRAM device of the invention can be, but not limited to obtain using above-mentioned forming method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of DRAM device, which is characterized in that including：
Substrate is provided, the substrate includes memory device area and at least one logic device area；
First grid and second grid are respectively formed in the logic device area of the substrate and memory device area；
Two of second grid in the substrate of the first grid two sides in the logic device area and memory device area respectively
Recess, the encapsulant layer in the recess, to be respectively formed the logic transistor and channel crystal are formed in the substrate of side
The source electrode of pipe or drain electrode；
Sequentially form dielectric layer and metal layer on the source electrode of the channel transistor or drain electrode, the dielectric layer,
The source electrode or drain electrode of metal layer and the channel transistor are for constituting capacitor；
Wherein, it forms first grid and the step of second grid includes：
The first grid and second grid are respectively the first pseudo- grid and the second pseudo- grid；
After the step of being respectively formed source electrode or the drain electrode of the logic transistor and channel transistor, the forming method is also
Including：
The described first pseudo- grid and the second pseudo- grid are removed, and form the first metal gate in the position of the described first pseudo- grid and the second pseudo- grid
Pole and the second metal gates；
The step of pseudo- grid of removal first and the second pseudo- grid includes：
The dielectric layer for covering the first grid and second grid is formed over the substrate；
Planarizing the dielectric layer exposes the first grid and second grid from the dielectric layer；
The part dielectric layer is removed, to expose one of the source electrode and drain electrode of the channel transistor；
Etching is opened with removing the first grid and second grid with forming the first opening and second in the dielectric layer
Mouthful；
The step of forming first metal gates and the second metal gates include：
It is formed in first opening, the source electrode of the second open bottom and the channel transistor of the exposing or drain surface
Dielectric substance, wherein the dielectric substance positioned at the first opening, the second open bottom is respectively the first grid and second
The dielectric substance of the gate dielectric layer of grid, source electrode or drain surface in the memory device area of the exposing is described
The dielectric layer of capacitor；
Metal material layer is formed in first opening, the second opening and on the dielectric layer, is opened wherein being located at first
Metal material layer in mouth, the second opening forms first metal gates and the second metal gates, is located at the dielectric layer
On metal material layer form the metal layer of the capacitor.
2. forming method as described in claim 1, which is characterized in that provide substrate the step of include：
Semiconductor base is provided；
Insulating layer is formed on the semiconductor base；
It is formed on the insulating layer semiconductor layer.
3. forming method as described in claim 1, which is characterized in that the dielectric substance is high K dielectric material.
4. forming method as described in claim 1, which is characterized in that formed metal material layer the step of include：Described
One opening, second opening in and expose channel transistor source electrode or drain surface formed metal material layer, planarization
The metal material layer flushes the surface of the metal layer of the capacitor and the surface of the first grid and second grid.
5. forming method as described in claim 1, which is characterized in that provide substrate the step of after, formed first grid with
And before the step of second grid, the forming method further includes：The forming method further includes：
The part for being located at logic device area and memory device area to the substrate is doped.
6. forming method as claimed in claim 5, which is characterized in that be located at logic device area and memory device area to substrate
Part the step of being doped include：
It is gradually reduced the doping concentration of Doped ions in the substrate from substrate surface to substrate center.
7. forming method as described in claim 1, which is characterized in that form the source of the logic transistor and channel transistor
In the step of pole or drain electrode,
The material layer filled in the recess is metal.
8. forming method as claimed in claim 7, which is characterized in that form the source of the logic transistor and channel transistor
Pole or drain electrode the step of further include：Metal is made annealing treatment.
9. forming method as described in claim 1, which is characterized in that the metal layer of the capacitor is tungsten or aluminum metal
Layer.
10. forming method as described in claim 1, which is characterized in that the thickness of the dielectric layer of the capacitor is received 1.5
Rice~3 nanometers in the range of.
11. a kind of DRAM device, which is characterized in that formed using the forming method of DRAM device as described in claim 1
The DRAM device, the DRAM device include：
Substrate, the substrate include memory device area and at least one logic device area；
Channel transistor and capacitor in the memory device area of the substrate and in the logic device area
Logic transistor, wherein the source electrode and drain electrode of the channel transistor and logic transistor is located in the substrate, described to patrol
The grid for collecting transistor and channel transistor is metal gates；
Dielectric layer and metal layer, the source of the channel transistor are sequentially formed in the channel transistor source electrode or drain electrode
Pole or drain electrode, the dielectric layer and the metal layer are for constituting capacitor；
Wherein, it forms first grid and the step of second grid includes：
The first grid and second grid are respectively the first pseudo- grid and the second pseudo- grid；
After the step of being respectively formed source electrode or the drain electrode of the logic transistor and channel transistor, the forming method is also
Including：
The described first pseudo- grid and the second pseudo- grid are removed, and form the first metal gate in the position of the described first pseudo- grid and the second pseudo- grid
Pole and the second metal gates；
The step of pseudo- grid of removal first and the second pseudo- grid includes：
The dielectric layer for covering the first grid and second grid is formed over the substrate；
Planarizing the dielectric layer exposes the first grid and second grid from the dielectric layer；
The part dielectric layer is removed, to expose one of the source electrode and drain electrode of the channel transistor；
Etching is opened with removing the first grid and second grid with forming the first opening and second in the dielectric layer
Mouthful；
The step of forming first metal gates and the second metal gates include：
It is formed in first opening, the source electrode of the second open bottom and the channel transistor of the exposing or drain surface
Dielectric substance, wherein the dielectric substance positioned at the first opening, the second open bottom is respectively the first grid and second
The dielectric substance of the gate dielectric layer of grid, source electrode or drain surface in the memory device area of the exposing is described
The dielectric layer of capacitor；
Metal material layer is formed in first opening, the second opening and on the dielectric layer, is opened wherein being located at first
Metal material layer in mouth, the second opening forms first metal gates and the second metal gates, is located at the dielectric layer
On metal material layer form the metal layer of the capacitor.
12. DRAM device as claimed in claim 11, which is characterized in that the source of the logic transistor and channel transistor
The material of pole and drain electrode is metal or the material containing metal.
13. DRAM device as claimed in claim 11, which is characterized in that the metal layer of the capacitor be tungsten metal layer or
Aluminum metal layer.
14. DRAM device as claimed in claim 11, which is characterized in that the thickness of the dielectric layer of the capacitor is 1.5
Nanometer~3 nanometers in the range of.
15. DRAM device as claimed in claim 11, which is characterized in that the layer on surface of metal of the capacitor and the logic
The gate surface of transistor and channel transistor flushes.
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