CN105529328A - DRAM device and manufacturing method thereof - Google Patents
DRAM device and manufacturing method thereof Download PDFInfo
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- CN105529328A CN105529328A CN201410513692.XA CN201410513692A CN105529328A CN 105529328 A CN105529328 A CN 105529328A CN 201410513692 A CN201410513692 A CN 201410513692A CN 105529328 A CN105529328 A CN 105529328A
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Abstract
The invention provides a DRAM device and a manufacturing method thereof. The manufacturing method of the DRAM device comprises steps that, a substrate is provided; a first grid electrode and a second grid electrode are formed; source electrodes or drain electrodes of a logic transistor and a channel transistor are formed, a dielectric layer and a metal layer are formed, and the dielectric layer and the source electrode or the drain electrode of the channel transistor commonly form a capacitor. The DRAM device comprises the substrate, the channel transistor, the capacitor and the logic transistor, wherein the dielectric layer and the metal layer are sequentially arranged on the source electrode or the drain electrode of the transistor, and the source electrode or the drain electrode, the dielectric layer and the metal layer are used for forming the capacitor. The method and the device are advantaged in that, the dielectric layer and the metal layer are formed on the source electrode or the drain electrode of the channel transistor for forming the capacitor, a problem that a special deep trench for forming a capacitor is formed in a substrate in the prior art can be solved, the manufacturing process is simplified, manufacturing complexity is reduced, and compatibility with the routine manufacturing flow can be better.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of DRAM device and forming method thereof.
Background technology
Along with the development of semiconductor industry, have the semiconductor device of memory function occupy the status of ever more important.With dynamic random access memory (DynamicRandomAccessMemory, DRAM) be example, flush type DRAM (embeddedDRAM, eDRAM) in DRAM classification has higher service speed and integrated level because of it, is applied to market gradually.
But, the production process due to eDRAM device comparatively numerous and diverse and with the production technology poor compatibility of existing conventional semiconductor devices, need to expend more manpower and materials when making this class device.On the other hand, promote to some extent even if the performance of eDRAM device compares traditional memory device, along with the development of the market demand, the performance of eDRAM device still needs further raising.
Therefore, how to simplify the Making programme of eDRAM device, and promote the performance of eDRAM device, become one of those skilled in the art's technical problem urgently to be resolved hurrily.
Summary of the invention
The problem that the present invention solves is by providing a kind of DRAM device and forming method thereof, to simplify the Making programme of DRAM device and to promote the performance of DRAM device.
For solving the problem, the invention provides a kind of formation method of DRAM device, comprising:
There is provided substrate, described substrate comprises memory device district and at least one logic device area;
First grid and second grid is formed respectively in the logic device area and memory device district of described substrate;
The substrate of the first grid both sides respectively in described logic device area, and form depression in the substrate of the both sides of second grid in memory device district, encapsulant layer in described depression, to form source electrode or the drain electrode of described logic transistor and channel transistor respectively;
The source electrode or drain electrode of described channel transistor form dielectric layer and metal level successively, the source electrode of described dielectric layer, metal level and described channel transistor or drain for forming capacitor.
Optionally, the step of substrate is provided to comprise:
Semiconductor base is provided;
Described semiconductor base forms insulating barrier;
Described insulating barrier forms semiconductor layer.
Optionally, the step forming first grid and second grid comprises:
Described first grid and second grid are respectively the first pseudo-grid and the second pseudo-grid;
After forming the source electrode of described logic transistor and channel transistor or the step of drain electrode respectively, described formation method also comprises:
Remove described first pseudo-grid and the second pseudo-grid, and form the first metal gates and the second metal gates in the position of described first pseudo-grid and the second pseudo-grid.
Optionally, the step removing the first pseudo-grid and the second pseudo-grid comprises:
Form the dielectric layer covering described first grid and second grid over the substrate;
Dielectric layer described in planarization makes described first grid and second grid expose from described dielectric layer;
Remove the described dielectric layer of part, to expose the source electrode of described channel transistor and one of them of drain electrode;
Etch to remove described first grid and second grid, to form the first opening and the second opening in described dielectric layer;
The step forming described first metal gates and the second metal gates comprises:
Described first opening, the second open bottom and described in the source electrode of channel transistor that exposes or drain surface form dielectric substance, wherein, be positioned at the first opening, gate dielectric layer that the dielectric substance of the second open bottom is respectively described first grid and second grid, the source electrode in the memory device district of exposing described in being arranged in or the dielectric substance of drain surface are the dielectric layer of described capacitor;
Metal material layer is formed in described first opening, the second opening and on described dielectric layer, wherein be arranged in the first opening, the metal material layer of the second opening forms described first metal gates and the second metal gates, the metal material layer be positioned on described dielectric layer forms the metal level of described capacitor.
Optionally, described dielectric substance is high K dielectric material.
Optionally, the step forming metal material layer comprises:
In described first opening, the second opening and the source electrode of the channel transistor exposed or drain surface form metal material layer, metal material layer described in planarization, makes the surface of the metal level of described capacitor flush with the surface of described first grid and second grid.
Optionally, after providing the step of substrate, before forming the step of first grid and second grid, described formation method also comprises: described formation method also comprises:
The part described substrate being positioned to logic device area and memory device district is adulterated.
Optionally, the step that the part being positioned at logic device area and memory device district to substrate is adulterated comprises:
The doping content of Doped ions in described substrate is reduced gradually from substrate surface to substrate center.
Optionally, formed in the source electrode of described logic transistor and channel transistor or the step of drain electrode,
The material layer of filling in described depression is metal.
Optionally, the step of the source electrode or drain electrode that form described logic transistor and channel transistor also comprises: carry out annealing in process to metal.
Optionally, the metal level of described capacitor is tungsten or aluminum metal layer.
Optionally, the thickness of the dielectric layer of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers.
In addition, the present invention is a kind of DRAM device also, comprising:
Substrate, described substrate comprises memory device district and at least one logic device area;
Be arranged in the channel transistor in the memory device district of described substrate and capacitor and be arranged in the logic transistor of described logic device area, wherein, the source electrode of described channel transistor and logic transistor and drain electrode are arranged in described substrate, and the grid of described logic transistor and channel transistor is metal gates;
Described channel transistor source electrode or drain electrode are formed with dielectric layer and metal level successively, and the source electrode of described channel transistor or drain electrode, described dielectric layer and described metal level are for forming capacitor.
Optionally, the source electrode of described logic transistor and channel transistor and the material of drain electrode are metal or the material containing metal.
Optionally, the metal level of described capacitor is tungsten metal level or aluminum metal layer.
Optionally, the thickness of the dielectric layer of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers.
Optionally, the layer on surface of metal of described capacitor flushes with the gate surface of described logic transistor and channel transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present invention forms logic transistor (logictransistor) and channel transistor (passtransistor) in the logic device area and memory device district of substrate, and dielectric layer and metal level is formed successively on the source electrode or drain electrode of described channel transistor, described dielectric layer, the source electrode of metal level and described channel transistor or drain and jointly form capacitor, described capacitor and described channel transistor form memory device jointly, compared with the mode forming capacitor with prior art, Making programme of the present invention by forming the capacitor that dielectric layer and metal level form memory device on the source electrode or drain electrode of channel transistor, that is, the source electrode of described channel transistor or drain electrode are also as a part for capacitor, the present invention do not need as prior art special in the substrate formed deep trench to form capacitor, because device size is more and more less, the difficulty of prior art when forming deep trench is also larger, therefore method of the present invention reduces manufacture difficulty to a certain extent.
In addition, the present invention is relative to prior art compatible conventional flow process more on Making programme, because prior art just needs to form deep trench after formation substrate, that is, in practical operation, the flow process that needs to break the normal procedure additionally adds the step of one making deep trench.By contrast, the present invention does not need and increases step outward, conveniently flow process is only needed to make logic transistor and channel transistor, then on the source electrode or drain electrode of channel transistor, the capacitor that dielectric layer and metal level just can form memory device is formed, better with the compatibility of old process.
Further, when channel transistor or logic transistor turn off, because electric field strength and distance are inversely proportional to, less with the larger then electric field strength of doped region surface distance, and then the charge carrier larger with doped region surface distance is not easy depleted; The present invention makes doping content reduce gradually from substrate surface to substrate center, and decrease the quantity of the charge carrier larger with channel region upper surface distance, the charge carrier in doped region can be made so depleted as best one can, and then reduce the probability that electric leakage occurs when the road transistor of formation and logic transistor turn off.
Further, make the source electrode of formation identical with the doping type of substrate with the doping type of drain electrode, and then formed without knot channel transistor with without knot logic transistor, relative to PN junction transistor of the prior art, of the present invention without tying channel transistor with logic transistor due to consistent with substrate doping type, doping is relatively easier, and nodeless mesh body pipe can suppress short-channel effect, still can work under several nano-scale, this is conducive to the performance of boost device.
Further, at the gate dielectric layer being positioned at the first opening, the dielectric substance of the second open bottom is respectively described first grid and second grid, the source electrode in the memory device district of exposing described in being arranged in or the dielectric substance of drain surface are the dielectric layer of described capacitor, just can form the dielectric layer of capacitor like this while the gate dielectric layer forming grid; Then, metal material layer is formed in described first opening, the second opening and on described dielectric layer, wherein be arranged in the first opening, the metal material layer of the second opening forms described first grid and second grid, the metal material layer be positioned on described dielectric layer forms the metal level of described capacitor, the metal level of capacitor can be formed like this while forming grid, without the need to forming capacitor to the extra like that processing step that arranges of prior art, that is can not off the beaten track Making programme, there is good compatibility.
Accompanying drawing explanation
Fig. 1 to Figure 10 is the structural representation of each step in formation method one embodiment of DRAM device of the present invention.
Embodiment
The process making eDRAM device is in the prior art more loaded down with trivial details, one of reason is because eDRAM device needs to add capacitor arrangement in the transistor, and the mode adopted in prior art etches formation deep trench (deeptrench) on substrate, then in deep trench, form semiconductor layer, dielectric layer and semiconductor layer successively, described like this semiconductor layer, dielectric layer and semiconductor layer just form described capacitor; After the capacitors are formed, then form logical gate and the storage area of eDRAM device, such as grid, source-drain electrode.But the old process difference of this method and existing manufacture semiconductor is larger, because old process is generally carry out according to the key step of substrate-grid-source-drain electrode, manufacture method of the prior art means additionally after the step forming substrate will increase the operation forming capacitor, that is, the process of existing formation eDRAM device and conventional flowsheet poor compatibility, this can cause whole manufacture craft to become complicated and loaded down with trivial details, and making progress is also affected.
On the other hand, because the capacitor making eDRAM device in prior art needs to form deep trench, under the trend that feature sizes of semiconductor devices reduces gradually, form deep trench and the difficulty covering various material layer in deep trench also more increases, not only technology difficulty increases, the effect covering various material layer may be also not ideal enough, and this can impact the performance of element manufacturing yield, device itself to a certain extent.
For this reason, the invention provides a kind of formation method of DRAM device, comprise the following steps:
There is provided substrate, described substrate comprises memory device district and at least one logic device area; First grid and second grid is formed respectively in the logic device area and memory device district of described substrate; The substrate of the respectively in described logic device area first pseudo-grid both sides, and form depression in the substrate of the both sides of the second pseudo-grid in memory device district, encapsulant layer in described depression, to form source electrode or the drain electrode of described logic transistor and channel transistor; Remove described first grid and second grid; Form the first metal gates and the second metal gates respectively in the position of described first grid and second grid, and then form logic transistor and channel transistor respectively in the logic device area and memory device district of substrate; The source electrode or drain electrode of described channel transistor form dielectric layer and metal level successively, the source electrode of described dielectric layer, metal level and described channel transistor or drain for forming capacitor, described capacitor and described channel transistor form memory device.
Pass through above-mentioned steps, Making programme of the present invention by forming the capacitor that dielectric layer and metal level form memory device on the source electrode or drain electrode of channel transistor, do not need as prior art special in the substrate formed deep trench to form capacitor, because device size is more and more less, the difficulty of prior art when forming deep trench is also comparatively large, and therefore method of the present invention reduces manufacture difficulty to a certain extent.And, the present invention is relative to prior art compatible conventional flow process more on Making programme, because prior art just needs to form deep trench after formation substrate, that is, in practical operation, the flow process that needs to break the normal procedure additionally adds the step of one making deep trench.By contrast, the present invention does not need and increases step outward, conveniently flow process is only needed to make logic transistor and channel transistor, then on the source electrode or drain electrode of channel transistor, the capacitor that dielectric layer and metal level just can form memory device is formed, better with the compatibility of old process.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 1 to Figure 10 is the structural representation of each step in formation method one embodiment of DRAM device of the present invention.
The present embodiment for formed planar structure without the channel transistor of junction type (junctionless) and the logic transistor without junction type.
First with reference to figure 1, provide substrate, described substrate comprises memory device district 20 and at least one logic device area 10, and memory device district 20 and logic device area 10 are respectively used to form memory device and logic transistor in subsequent steps.
In the present embodiment, described substrate is the substrate of silicon on insulated substrate (SiliconOnInsulator, SOI), specifically, provides the step of substrate to comprise step by step following:
Semiconductor base 100 is provided; In the present embodiment, described semiconductor base 100 is silicon base;
Described semiconductor base 100 forms insulating barrier 110; In the present embodiment, described insulating barrier 110 can be earth silicon material;
Described semiconductor base 100 forms semiconductor layer 120; Described semiconductor layer 120 is for forming memory device and logic transistor at subsequent step.
In the present embodiment, the material of described semiconductor layer 120 is silicon.
It should be noted that the semiconductor layer 120 in the present embodiment Fig. 1 separated may be formed with other structures such as such as isolation structure at breaking part.But whether the present invention must disconnect described semiconductor layer 120 is not construed as limiting.
In the present embodiment, after formation semiconductor layer 120, before forming logic transistor and channel transistor, also the part that described substrate is positioned at logic device area 10 and memory device district 20 is adulterated, specifically the part that described semiconductor layer 120 is positioned at logic device area 10 and memory device district 20 is adulterated, and then form doped region.
The present embodiment, to form N-shaped flush type DRAM device, therefore carries out N-shaped ion doping to described semiconductor layer 120.
The doping content of described substrate Doped ions is made to reduce gradually from substrate surface to substrate center when carrying out adulterated, more particularly, the doping content of Doped ions in semiconductor layer 120 is reduced gradually from substrate surface to substrate center, be conducive to the logic transistor of follow-up formation and the shutoff of channel transistor like this, and then reduce electric leakage degree.Its reason is, when channel transistor or logic transistor turn off, because electric field strength and distance are inversely proportional to, less with the larger then electric field strength of doped region surface distance, and then the charge carrier larger with doped region surface distance is not easy depleted; The present invention makes doping content reduce gradually from substrate (being semiconductor layer 120 the present embodiment) surface to substrate center, and decrease the quantity of the charge carrier larger with channel region upper surface distance, the charge carrier in doped region can be made so depleted as best one can, and then reduce the probability that electric leakage occurs when the road transistor of formation and logic transistor turn off.
Then with reference to figure 2, in the logic device area 10 and memory device district 20 of described substrate, first grid and second grid is formed respectively.
After the present embodiment adopts, grid technique forms described channel transistor and logic transistor.Specifically, first on the semiconductor layer 120 in logic device area and memory device district 20, form respective grid oxide layer 131 respectively, on grid oxide layer 131, then form the first pseudo-grid 130b and the second pseudo-grid 130a respectively.
Concrete, described first pseudo-grid 130b and the second pseudo-grid 130a can adopt polysilicon as material, and described grid oxide layer 131 can adopt silicon dioxide as material simultaneously.Be prior art, the present invention does not repeat this herein, is not also limited in any way simultaneously.
In addition it should be noted that, in described memory device district 20, form pseudo-grid in the present embodiment, that is, in the channel transistor formed in subsequent step, only comprise a grid.But in other embodiments of the invention, described channel transistor also can be two or more grids, in memory device district 20, also form the first pseudo-grid 130b and the second pseudo-grid 130a of respective numbers accordingly in this step.
In addition, the gate shapes of the present invention to described channel transistor is also not construed as limiting, the shape of described grid can also be three Ω grids (Omegagate) around described semiconductor layer 120, or loopful is around the cylindricality grid (cylindricalgate) of described semiconductor layer 120, the present invention is not construed as limiting this.Accordingly, this step also can form corresponding shape when forming the pseudo-grid in memory device district 20.
Then with reference to figure 3, before the substrate place being formed in the grid both sides in described logic device area 10 and memory device district 20 forms the step of source electrode and drain electrode respectively, the present embodiment first forms side wall 132 at the sidewall of the described first pseudo-grid 130b laid respectively in described logic device area 10 and memory device district 20 and the second pseudo-grid 130a, described side wall 132 can reduce follow-up formation source electrode, drain on the impact of the first pseudo-grid 130b and the second pseudo-grid 130a, also help in subsequent step and remove described first pseudo-grid 130b and the second pseudo-grid 130a.
Specifically, in the present embodiment, the mode of chemical vapour deposition (CVD) can be adopted to form described side wall 132, and the gradient coating performance of the side wall 132 that this mode is formed is better.
It should be noted that, in the present embodiment, be also formed with side wall 122 at the sidewall of described semiconductor layer 120, but this can't affect enforcement of the present invention.
After the described side wall 122,132 of formation, in the substrate of the both sides of the in described logic device area 10 and memory device district 20 first pseudo-grid 130b, (on the semiconductor layer 120 namely in the present embodiment) forms source electrode or drain electrode respectively, and (on the semiconductor layer 120 namely in the present embodiment) forms depression in the substrate of the second pseudo-grid 130a both sides, encapsulant layer in described depression, to form source electrode or the drain electrode of described logic transistor and channel transistor respectively.
In the present embodiment, because semiconductor layer in the present embodiment 120 is silicon semiconductor layer, source electrode and the drain electrode of metal silicide materials can be formed.
The source-drain electrode of metal silicide materials is conducive to reducing the contact resistance between the conductive plunger of follow-up formation, and additionally forms one deck suicide contact layer in the prior art without the need to picture and reduce contact resistance between source-drain electrode and conductive plunger.In addition, resistance between the source-drain electrode of metal silicide materials also can diminish to a certain extent, this means under same cut-in voltage, firing current becomes large, this is conducive to the performance improving logic transistor and channel transistor to a certain extent, such as, the logic transistor under operating state and the electric leakage degree etc. of channel transistor when turning off is improved.
Specifically, with reference to figure 4, the step of source electrode or drain electrode that the present embodiment forms described metal silicide materials comprises:
The substrate of the in described logic device area 10 first pseudo-grid 130b both sides, and form depression 40 in the substrate of the both sides of the second pseudo-grid 130a in memory device district 20; The position of described depression 40 is the position of the logic transistor of follow-up formation and channel transistor source-drain electrode separately.
In the present embodiment, the mode of etching can be adopted to form described depression 40; Meanwhile, owing to being formed with side wall 132 at the first pseudo-grid 130b, the second pseudo-grid 130a sidewall, described side wall 132 can as the etching stop layer of described first pseudo-grid 130b, the second pseudo-grid 130a.
After this, with reference to figure 5, in described depression 40, fill metal 140a, 140b, 150a, 150b, described metal 140a, 140b, 150a, 150b be used for react with part of semiconductor layer 120 in subsequent step formed described metal silicide materials source-drain electrode;
In the present embodiment, described metal 140a, 140b, 150a, 150b can be aluminium, tungsten, copper or titanium etc., and these metals can react with the semiconductor layer 120 of silicon materials in the present embodiment the source-drain electrode forming metal silicide materials.
With reference to figure 6, annealing in process is carried out to described metal 140a, 140b, 150a, 150b and semiconductor layer 120, with make described metal 140a, 140b, 150a, 150b and part of semiconductor layer 120 change into metal silicide materials source electrode 141a, 151a and drain 141b, 151b.Described source electrode 151a and drain electrode 151b is the source-drain electrode of the logic transistor of follow-up formation, and described source electrode 141a and drain electrode 141b is the source-drain electrode of the channel transistor of follow-up formation.
Because the source-drain electrode formed is the source-drain electrode of metal silicide materials, source electrode, drain electrode between do not exist p-type doping, N-shaped doping point, so the present embodiment formation logic transistor and channel transistor be without the logic transistor of junction type with without junction type channel transistor.
The benefit forming the channel transistor without junction type and the logic transistor without junction type is, due to reducing further of device, the area of source-drain electrode and channel region is reduced, when forming traditional PN junction transistor, the control difficulty of source-drain electrode doping is increased, realizes source electrode, PN junction between drain electrode and channel region becomes more and more difficult.Source electrode in the present embodiment, be conducive to consistent with channel region doping type of drain electrode reduce doping difficulty, can also suppress short-channel effect simultaneously, still can work under several nano-scale.
After formation described source electrode 141a, 151a and drain electrode 141b, 151b, remove described first pseudo-grid 130b and the second pseudo-grid 130a, think that follow-up formation first grid and second grid provide condition.
Shown in figure 7, in the present embodiment, remove described first pseudo-grid 130b and the second pseudo-grid 130a to comprise the following steps:
Form the dielectric layer 200 covering described first pseudo-grid 130b and the second pseudo-grid 130a over the substrate
Dielectric layer 200 described in planarization, makes described first pseudo-grid 130b and the second pseudo-grid 130a expose from described dielectric layer 200, so that remove described first pseudo-grid 130b and the second pseudo-grid 130a in subsequent step.
In the specific implementation, dielectric layer 200 described in the mode planarization that can adopt cmp, and to detect that the polycrystalline silicon material of described first pseudo-grid 130b and the second pseudo-grid 130a is for grinding stop signal, stop grinding when being ground to the first pseudo-grid 130b and the second pseudo-grid 130a, and then reach the above-mentioned object that the first pseudo-grid 130b and the second pseudo-grid 130a is exposed from dielectric layer 200.
Continue with reference to figure 7, make described first pseudo-grid 130b and the second pseudo-grid 130a from after described dielectric layer 200 exposes, the present embodiment also removes part dielectric layer 200 to expose source electrode in described memory device district 20 and drain electrode 140 one of them (exposing source electrode 140a in the present embodiment), the object of this step is to expose described source electrode 140a to provide condition for follow-up formation capacitor, and the step forming capacitor will be described at further part.
Owing to being also formed with side wall 122 at the sidewall of described semiconductor layer 120, in the present embodiment, also the side wall 122 of semiconductor layer 120 sidewall exposed from dielectric layer 200 is together removed (sidewall with reference to the semiconductor layer 120 on the right side of figure 7), like this when the described capacitor of follow-up formation, the semiconductor layer 120 of this part also can with the dielectric layer formed, metal level together forms capacitor, that is, the capacitor formed is not only the source electrode of channel transistor or drain electrode and dielectric layer, the capacitor that metal level is formed jointly, also comprise semiconductor layer 120 and dielectric layer, the capacitor that metal level is formed, the capacitance of capacitor can be increased like this.
But because the source electrode 140a of channel transistor and dielectric layer, metal level can form capacitor, thus the present invention is not construed as limiting the side wall 122 whether must removing described semiconductor layer 120 sidewall.
With reference to figure 8, etch to remove described first pseudo-grid 130b and the second pseudo-grid 130a, to form the first opening 50 and the second opening 51 in described dielectric layer.
In addition, also the grid oxide layer 131 be positioned at below the first pseudo-grid 130b and the second pseudo-grid 130a is also removed in the present embodiment, and then provide condition for follow-up formation grid.
In the present embodiment, form grid respectively in the first opening 50 and the second opening 51 before, further comprising the steps of:
With reference to figure 9, bottom described first opening 50, second opening 51 and described in the source electrode of channel transistor that exposes or drain surface form dielectric substance, wherein, the dielectric substance be positioned at bottom the first opening 50, second opening 51 is respectively the first grid of follow-up formation and the gate dielectric layer 144 of second grid, the memory device district 20 of exposing described in being arranged in, the dielectric substance on the source electrode exposed from described dielectric layer 200 or drain electrode (as mentioned before, in the present embodiment being source electrode 140a) surface is the dielectric layer 170 of described capacitor.
Specifically, first can form dielectric substance in the first opening 50, second opening 51, on dielectric layer 200 surface and the source electrode 140a that exposes, then etch away sections dielectric substance, only retains and above-mentioned is positioned at bottom the first opening 50, second opening 51 and the dielectric substance on the source electrode 140a surface of exposing.
Wherein, the dielectric substance be positioned at bottom the first opening 50, second opening 51 is respectively the gate dielectric layer 144 of described first grid and second grid, and the dielectric substance on the source electrode in the memory device district 20 of exposing described in being arranged in or drain electrode (the present embodiment is source electrode 141a) surface is the dielectric layer 170 of described capacitor.The dielectric layer 170 of capacitor is also form like this while forming the gate dielectric layer 144 in described first opening 50, second opening 51, do not need to arrange extra step specially to form the dielectric layer of capacitor, only need mask pattern when changing etching removal part dielectric substance, more simple and convenient relative to prior art.
In the present embodiment, the thickness of the dielectric layer 170 of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers, but this number range is only the present embodiment to be adopted, and concrete thickness should adjust according to actual conditions.In general, the thickness of dielectric layer 170 more little being more conducive to increases the capacitance forming capacitor.
In the present embodiment, hafnium can be adopted to form described dielectric substance, on the one hand, the dielectric substance of hafnium means that the gate dielectric layer 144 of formation is also hafnium, and this can increase the grid-control ability of grid in the logic transistor of follow-up formation and channel transistor; On the other hand, the dielectric substance of hafnium means that the dielectric layer of capacitor is also hafnium, and according to the principle that capacitance is directly proportional to k value, this can increase the capacitance forming capacitor.
Concrete, in the present embodiment, described high-k dielectrics material can adopt as LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, (BaSr) TiO
3(BST), Al
2o
3, Si
3n
4, or nitrogen oxide is as material, and the present invention is not construed as limiting this.
In conjunction with reference to Figure 10, in the position of described first pseudo-grid 130b and the second pseudo-grid 130a, namely form first grid 133 and second grid 134, to form described channel transistor and logic transistor respectively in described first opening 50 and the second opening 51.
In the present embodiment, first grid 133 and the second grid 134 of semi-conducting material or metal material can be formed.
Concrete, and described dielectric layer 170 can form metal material layer in described first opening 50, second opening 51, wherein, the metal material layer being arranged in the first opening 50, second opening 51 forms described first grid 133 and second grid 134, and then forms described logic transistor and channel transistor respectively in the logic device area 10 and memory device district 20 of substrate.Meanwhile, the metal material layer be positioned on described dielectric layer 170 forms the metal level 160 of described capacitor; Source electrode 141a below described metal level 160, dielectric layer 170 and dielectric layer 170 forms the capacitor of memory device jointly.
Described capacitor and described channel transistor form the memory device in described DRAM device jointly.
Because capacitor is by metal silicide materials, namely containing the source electrode 141a of metal, and dielectric layer 170 and metal level 160 form, and then form the capacitor of MIM (metal-insulator-metal) structure.
The present embodiment can form the metal level 160 of described capacitor while the grid forming described logic transistor and channel transistor, without the need to additionally increasing the step forming capacitor, increase relative to prior art the mode that some steps form capacitor specially, the present invention is easier.
Concrete, the metal level 160 of described first grid 133, second grid 134 and capacitor can be formed in the following manner:
In described first opening 50, second opening 51, dielectric layer 200 and the source electrode of channel transistor exposed or drain electrode (being source electrode 140a in the present embodiment) surface form metal material layer, then metal material layer described in planarization, the surface of the metal level of described capacitor is flushed (with reference to shown in Figure 10) with the surface of described first grid and second grid, can remove the metal material layer of redundance like this, remaining metal material layer just forms described first grid 133, second grid 134 and metal level 160.
In the present embodiment, the metal level of described capacitor is tungsten metal level or aluminum metal layer.But the present invention is not construed as limiting this.
After this, the present embodiment also comprises the dielectric layer 200 removed and be formed on logic transistor and channel transistor, and the source-drain electrode then on logic transistor and channel transistor forms the parts such as conductive plunger.As mentioned before, owing to described source-drain electrode being formed with metal silicide layer 141,151, described metal silicide layer 141,151 can reduce the contact resistance between source-drain electrode and conductive plunger.
In addition, the present invention also provides another embodiment of described formation method, and the difference of the present embodiment and a upper embodiment is, the step that the step of the source electrode or drain electrode that form described logic transistor and channel transistor respectively comprises comprises:
The substrate of the in described logic device area first pseudo-grid 130b both sides, and form depression in the substrate of the both sides of the second pseudo-grid 130a in memory device district;
After this, in described depression, fill metal, to form source electrode or the drain electrode of described logic transistor and channel transistor, that is, the source electrode of described logic transistor and channel transistor or the material of drain electrode are metal.
Specifically, selective chemical vapour deposition (selectiveCVD) can be adopted in the present embodiment, in described depression, fill metal.Due in deposition process, pre-reaction material is less than the reaction rate in growing surface (sidewall of depression and bottom) in the reaction rate of non-growth surface, optionally can form described material layer in the valley like this.So this generation type can deposit when not forming mask and form material layer, and has good stepcoverage performance.
Further, Metalorganic chemical vapor deposition (MetalOrganicChemicalVaporDeposition can be adopted, MOCVD) mode fills metal in described depression, and the step coverage of this mode is comparatively better, can be covered in preferably in the middle of described depression.
In the present embodiment, aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material etc. can be adopted to form source electrode or the drain electrode of metal.But the present invention is not construed as limiting this, the source electrode of described logic transistor and channel transistor or the material of drain electrode also can be semi-conducting materials.
In addition, the present invention also provides a kind of DRAM device, with reference to Figure 10, comprises in the present embodiment described in described DRAM device:
Substrate, described substrate comprises memory device district 20 and at least one logic device area 10;
Be arranged in the channel transistor in the memory device district 20 of described substrate and capacitor and be arranged in the logic transistor of described logic device area 10;
The source electrode of described channel transistor and logic transistor and drain electrode are arranged in described substrate, and the grid of described logic transistor and channel transistor is metal gates;
Described channel transistor source electrode or drain electrode are formed with dielectric layer 170 and metal level 160 successively, and the source electrode of described channel transistor or drain electrode (being source electrode 140a in the present embodiment), described dielectric layer 170 and described metal level 160 are for forming capacitor.
In the present embodiment, source electrode 150a, 140a of described logic transistor and channel transistor and drain electrode 150b, 140b are metal or contain source electrode and the drain electrode of metal, such source electrode, drain electrode between do not exist p-type doping, N-shaped doping point, so the present embodiment formation logic transistor and channel transistor be without the logic transistor of junction type with without junction type channel transistor.Due to reducing further of device, the area of source and drain and channel region being reduced, when forming traditional PN junction transistor, the control difficulty of source electrode, drain implants being increased, realize source electrode, PN junction between drain electrode and channel region becomes more and more difficult.Source electrode in the present embodiment, be conducive to consistent with channel region doping type of drain electrode reduce doping difficulty, can also suppress short-channel effect simultaneously, still can work under several nano-scale.
In the present embodiment, the grid 133,134 of described logic transistor and channel transistor is metal gates, can be formed like this with the metal level 160 forming capacitor in same step, and this is conducive to simplifying formation process.
In the present embodiment, be tungsten metal level or aluminum metal layer for forming the metal level of described capacitor.
In the present embodiment, the thickness of the dielectric layer 170 of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers.But this number range is only the present embodiment and adopts, concrete thickness should adjust according to actual conditions.In general, the thickness of dielectric layer 170 is less, and the capacitance of described capacitor is larger.
In the present embodiment, the surface of surface and the described logic transistor of the metal level 160 of described capacitor and the grid 133,134 of channel transistor flushes.
In addition it should be noted that, DRAM device of the present invention can be, but not limited to adopt above-mentioned formation method to obtain.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a formation method for DRAM device, is characterized in that, comprising:
There is provided substrate, described substrate comprises memory device district and at least one logic device area;
First grid and second grid is formed respectively in the logic device area and memory device district of described substrate;
The substrate of the first grid both sides respectively in described logic device area, and form depression in the substrate of the both sides of second grid in memory device district, encapsulant layer in described depression, to form source electrode or the drain electrode of described logic transistor and channel transistor respectively;
The source electrode or drain electrode of described channel transistor form dielectric layer and metal level successively, the source electrode of described dielectric layer, metal level and described channel transistor or drain for forming capacitor.
2. form method as claimed in claim 1, it is characterized in that, provide the step of substrate to comprise:
Semiconductor base is provided;
Described semiconductor base forms insulating barrier;
Described insulating barrier forms semiconductor layer.
3. form method as claimed in claim 1, it is characterized in that, the step forming first grid and second grid comprises:
Described first grid and second grid are respectively the first pseudo-grid and the second pseudo-grid;
After forming the source electrode of described logic transistor and channel transistor or the step of drain electrode respectively, described formation method also comprises:
Remove described first pseudo-grid and the second pseudo-grid, and form the first metal gates and the second metal gates in the position of described first pseudo-grid and the second pseudo-grid.
4. form method as claimed in claim 3, it is characterized in that, the step removing the first pseudo-grid and the second pseudo-grid comprises:
Form the dielectric layer covering described first grid and second grid over the substrate;
Dielectric layer described in planarization makes described first grid and second grid expose from described dielectric layer;
Remove the described dielectric layer of part, to expose the source electrode of described channel transistor and one of them of drain electrode;
Etch to remove described first grid and second grid, to form the first opening and the second opening in described dielectric layer;
The step forming described first metal gates and the second metal gates comprises:
Described first opening, the second open bottom and described in the source electrode of channel transistor that exposes or drain surface form dielectric substance, wherein, be positioned at the first opening, gate dielectric layer that the dielectric substance of the second open bottom is respectively described first grid and second grid, the source electrode in the memory device district of exposing described in being arranged in or the dielectric substance of drain surface are the dielectric layer of described capacitor;
Metal material layer is formed in described first opening, the second opening and on described dielectric layer, wherein be arranged in the first opening, the metal material layer of the second opening forms described first metal gates and the second metal gates, the metal material layer be positioned on described dielectric layer forms the metal level of described capacitor.
5. form method as claimed in claim 4, it is characterized in that, described dielectric substance is high K dielectric material.
6. form method as claimed in claim 3, it is characterized in that, form the step of metal material layer to comprise: in described first opening, the second opening and the source electrode of the channel transistor exposed or drain surface form metal material layer, metal material layer described in planarization, makes the surface of the metal level of described capacitor flush with the surface of described first grid and second grid.
7. form method as claimed in claim 1, it is characterized in that, after providing the step of substrate, before forming the step of first grid and second grid, described formation method also comprises: described formation method also comprises:
The part described substrate being positioned to logic device area and memory device district is adulterated.
8. form method as claimed in claim 7, it is characterized in that, the step that the part being positioned at logic device area and memory device district to substrate is adulterated comprises:
The doping content of Doped ions in described substrate is reduced gradually from substrate surface to substrate center.
9. form method as claimed in claim 1, it is characterized in that, formed in the source electrode of described logic transistor and channel transistor or the step of drain electrode,
The material layer of filling in described depression is metal.
10. form method as claimed in claim 9, it is characterized in that, the step of the source electrode or drain electrode that form described logic transistor and channel transistor also comprises: carry out annealing in process to metal.
11. form method as claimed in claim 1, it is characterized in that, the metal level of described capacitor is tungsten or aluminum metal layer.
12. form method as claimed in claim 1, it is characterized in that, the thickness of the dielectric layer of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers.
13. 1 kinds of DRAM devices, is characterized in that, comprising:
Substrate, described substrate comprises memory device district and at least one logic device area;
Be arranged in the channel transistor in the memory device district of described substrate and capacitor and be arranged in the logic transistor of described logic device area, wherein, the source electrode of described channel transistor and logic transistor and drain electrode are arranged in described substrate, and the grid of described logic transistor and channel transistor is metal gates;
Described channel transistor source electrode or drain electrode are formed with dielectric layer and metal level successively, and the source electrode of described channel transistor or drain electrode, described dielectric layer and described metal level are for forming capacitor.
14. DRAM devices as claimed in claim 13, is characterized in that, the source electrode of described logic transistor and channel transistor and the material of drain electrode are metal or the material containing metal.
15. DRAM devices as claimed in claim 13, is characterized in that, the metal level of described capacitor is tungsten metal level or aluminum metal layer.
16. DRAM devices as claimed in claim 13, is characterized in that, the thickness of the dielectric layer of described capacitor is in the scope of 1.5 nanometer ~ 3 nanometers.
17. DRAM devices as claimed in claim 13, is characterized in that, the layer on surface of metal of described capacitor flushes with the gate surface of described logic transistor and channel transistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106816434A (en) * | 2017-02-24 | 2017-06-09 | 合肥智聚集成电路有限公司 | High K dielectric film layer structure and its application and manufacture method |
| CN107492542A (en) * | 2016-06-10 | 2017-12-19 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor subassembly |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507658A (en) * | 2002-02-14 | 2004-06-23 | ���µ�����ҵ��ʽ���� | Semiconductor device and its manufacturing method |
| US20040191985A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer |
| CN101064272A (en) * | 2006-04-28 | 2007-10-31 | 应用材料股份有限公司 | Plasma etch process using polymerizing etch gases |
-
2014
- 2014-09-29 CN CN201410513692.XA patent/CN105529328B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507658A (en) * | 2002-02-14 | 2004-06-23 | ���µ�����ҵ��ʽ���� | Semiconductor device and its manufacturing method |
| US20040191985A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer |
| CN101064272A (en) * | 2006-04-28 | 2007-10-31 | 应用材料股份有限公司 | Plasma etch process using polymerizing etch gases |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107492542A (en) * | 2016-06-10 | 2017-12-19 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor subassembly |
| CN107492542B (en) * | 2016-06-10 | 2021-02-26 | 台湾积体电路制造股份有限公司 | Semiconductor assembly and its manufacturing method |
| CN106816434A (en) * | 2017-02-24 | 2017-06-09 | 合肥智聚集成电路有限公司 | High K dielectric film layer structure and its application and manufacture method |
| CN106816434B (en) * | 2017-02-24 | 2018-05-22 | 睿力集成电路有限公司 | High K dielectric film layer structure and its application and manufacturing method |
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