CN113437070A

CN113437070A - Semiconductor device and method of forming the same

Info

Publication number: CN113437070A
Application number: CN202110778040.9A
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2021-09-24
Anticipated expiration: 2041-07-09
Also published as: CN113437070B

Abstract

The invention discloses a semiconductor device and a forming method thereof. The bit line is disposed on the substrate. The first contact is disposed on the substrate and spaced apart from the bit line. The first and second spacers are disposed between the bit lines and the first contacts and have a first height and a second height, respectively. The second contacts are respectively arranged above the first contacts, the metal silicide layer is arranged between the first contacts and the second contacts, and the end face of the metal silicide layer is clamped between the second gap wall and the first gap wall. The semiconductor device of the invention can have a plug structure with a more optimized structure, and can improve the electrical connection between the storage node and the lower transistor component.

Description

Semiconductor device and method of forming the same

Technical Field

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor memory device and a method for forming the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For a Dynamic Random Access Memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of a capacitor structure, under the current mainstream development trend, it has gradually replaced a DRAM with a planar gate structure.

Generally, a dram having a recessed gate structure is formed by a large number of memory cells (memory cells) grouped to form an array region for storing information, and each memory cell may be composed of a transistor device and a capacitor device connected in series to receive voltage information from a Word Line (WL) and a Bit Line (BL). In response to product requirements, the density of memory cells in the array region needs to be continuously increased, which results in increasing difficulty and complexity in the related fabrication process and design. Therefore, further improvements are needed in the art to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

An objective of the present invention is to provide a method for forming a semiconductor device, in which a metal silicide layer is additionally disposed between a lower contact and an upper contact through a metal silicide process, so that the metal silicide layer can straddle between spacers on both sides of a bit line. Therefore, the forming method of the invention can form a plug structure with better contact with the substrate, and form a semiconductor device with more optimized structure, so as to improve the electrical connection between the storage node plug and the lower transistor component.

Another object of the present invention is to provide a semiconductor device, which additionally provides a metal silicide layer between the lower contact and the upper contact, so that the metal silicide layer can cross the spacers on both sides of the bit line. Therefore, the semiconductor device of the invention can have a plug structure with a more optimized structure, and the electrical connection between the storage node plug and the lower transistor component can be improved.

To achieve the above objective, one embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. First, a substrate is provided, and a plurality of bit lines are formed on the substrate. Then, a plurality of first contacts are formed on the substrate, and the bit lines and the first contacts are alternately arranged. Then, forming a first spacer on the substrate between each bit line and the first contact, the first spacer being disposed on the substrate and extending upward from a top surface of the substrate by a first height, and forming a second spacer on the first spacer and disposed between the first spacer and the first contact, the second spacer being disposed on the substrate and extending upward from the top surface of the substrate by a second height, the first height being higher than the second height. And then, forming a plurality of second contacts above the first contacts respectively, and forming a metal silicide layer on the substrate, wherein the metal silicide layer is positioned between the first contacts and the second contacts, and the end face of the metal silicide layer is clamped between the second gap walls and the first gap walls.

To achieve the above objective, one embodiment of the present invention provides a semiconductor device including a substrate, a plurality of bit lines, a plurality of first contacts, first spacers, second spacers, a plurality of second contacts, and a metal silicide layer. The bit line is disposed on the substrate. The first contact is disposed on the substrate and spaced apart from the bit line. The first spacers are disposed between the bit lines and the first contacts, the first spacers are disposed on the substrate and extend upward from a top surface of the substrate by a first height, the second spacers are disposed between the first spacers and the first contacts, the second spacers are disposed on the substrate and extend upward from the top surface of the substrate by a second height, and the first height is higher than the second height. The second contacts are respectively arranged above the first contacts. The metal silicide layer is arranged between the first contact and the second contact, wherein the end face of the metal silicide layer is clamped between the second gap wall and the first gap wall.

Drawings

Fig. 1 to 7 are schematic views illustrating steps of a method for forming a semiconductor device according to a first embodiment of the present invention, wherein:

FIG. 1 is a top view of a semiconductor device after bit lines have been formed;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic cross-sectional view of a semiconductor device after an etching process;

FIG. 4 is a schematic cross-sectional view of a semiconductor device after forming a conductive layer;

FIG. 5 is a schematic cross-sectional view of a semiconductor device after forming a silicide layer; and

FIG. 6 is a cross-sectional view of a semiconductor device after formation of a storage node plug; and

FIG. 7 is a cross-sectional view of a semiconductor device after formation of a storage node pad.

FIG. 8 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 200, 300, 400, 500, 600, 700 semiconductor device

101 insulating region

103 active region

105 opening

107 opening

110 substrate

110a top surface

120 word line

130 dielectric layer

131 oxide layer

133 nitride layer

135 oxide layer

160. 162, 164 bit line

160a bit line contact

161 semiconductor layer

163 barrier layer

165 conductive layer

167 a cap layer

170. 370 spacer structure

171 spacer

171a side wall

173 spacer

175 spacer

175a top surface

190. 290, 390, 490, 590, 690, 790 storage node plugs

191 conductive layer

193. 393, 493, 593, 693, 793 contacts

195. 295, 395, 495, 595, 695, 795 contacts

201. 203, 204, 205, 206, 207 metal silicide layer

205a first part

205b second part

206a arc top surface

207a first part

207b second part

210 dielectric layer

220 storage node pad

276 spacer wall

377 spacer

377a shoulder

D1 and D2 directions

h1, h2 height

W1, W2 Width

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below to explain the present invention and its intended effects. Those skilled in the art to which the invention relates will appreciate that the features of the various embodiments can be interchanged, recombined, mixed and modified to achieve other embodiments without departing from the spirit of the invention as defined by the appended claims.

Referring to fig. 1-6, steps of a method for forming a semiconductor device 100 according to a first embodiment of the present invention are illustrated, wherein fig. 1 is a top view of the semiconductor device at a formation stage, and fig. 2-6 are cross-sectional views of the semiconductor device at the formation stage. The semiconductor device 100 of the present embodiment is, for example, a Dynamic Random Access Memory (DRAM) device, which includes at least one transistor element (not shown) and at least one capacitor element (not shown) as a minimum unit cell (memory cell) in a DRAM array and receives voltage information from a bit line 160 and a word line 120.

The semiconductor device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, wherein at least one insulating region 101, such as a Shallow Trench Isolation (STI), is formed in the substrate 110, and a plurality of Active Areas (AA) 103 are defined on the substrate 100. The isolation region 101 is formed by, for example, etching a plurality of trenches (not shown) in the substrate 100, and filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

As shown in fig. 1, a plurality of buried gates (not shown) may also be formed in the substrate 110, for example, the buried gates extend parallel to each other along the same direction D1 and cross the active region 103 to serve as Buried Word Lines (BWLs) 120 of the semiconductor device 100. A plurality of source/drain regions (not shown) may also be formed in the substrate 110 on both sides of the buried gate, so that the buried gate and the source/drain regions may together form a transistor element (not shown) of the semiconductor device 100. A plurality of bit lines 160 may be formed on the substrate 110 and extend parallel to each other along another direction D2 perpendicular to the buried word lines 120 to simultaneously cross the active regions 103 and the buried word lines 120 in the substrate 110. Referring to fig. 2, in the direction D1, each bit line 160 is formed separately on the substrate 110 and includes a semiconductor layer (e.g., comprising polysilicon) 161, a barrier layer 163 (e.g., comprising titanium and/or titanium nitride), a conductive layer 165 (e.g., comprising a low-resistivity metal such as tungsten, aluminum, or copper), and a cap layer 167 (e.g., comprising silicon oxide, silicon nitride, or silicon oxynitride), which are stacked in sequence, but not limited thereto. Note that a portion of the bit lines 162 is formed on the dielectric layer 130 over the substrate 110, wherein the dielectric layer 130 preferably has a composite structure, such as, but not limited to, an oxide-nitride-oxide (ONO) structure including an oxide layer 131-a nitride layer 133-an oxide layer 135; another portion of the bit lines 164 has a Bit Line Contact (BLC) 160a formed thereunder, which may further extend into the substrate 110. The bit lines 162 and the bit lines 164 are alternately disposed, such that each bit line 164 is located between two adjacent bit lines 162, and the bit line contact 160a under the bit line 164 is integrally formed with the semiconductor layer 161 of the bit line 164 and directly contacts the substrate 110, as shown in fig. 2.

As shown in fig. 2, a spacer 171 and a spacer 173 are sequentially formed on the sidewall of each bit line 160. In one embodiment, the

spacers

171 and 173 are formed by different deposition and etching processes, so that the

spacers

171 and 173 can be in the form of strips and comprise different insulating materials. For example, a spacer 171 may be formed by first depositing a silicon nitride (not shown) layer on the bit lines 160 and the substrate 110, covering the top and sidewalls of each bit line 160 and the top surface of the dielectric layer 130, and then performing an etching-back process to partially remove the silicon nitride layer to form the spacer 171 (including silicon nitride); then, a process of forming the spacers 173 is performed to entirely deposit a silicon oxide layer (not shown) covering the top surfaces of the bit lines 160, the spacers 171, and the top surface 110a of the substrate 110, and another process of etching back is performed to partially remove the silicon oxide layer to form the spacers 173 (including silicon oxide, etc.), but not limited thereto. Thus, the

spacers

171, 173 may have top surfaces that are flush with each other. In addition, after the etching back process of the spacer 171 is performed, the underlying dielectric layer 130 may be optionally further patterned, so that the subsequently formed spacer 173 may be directly formed on the top surface 110a of the substrate. It is noted that in the present embodiment, the

spacers

171 and 173 formed on one portion of the bit lines 162 are respectively located on the top surface of the dielectric layer 130 and the top surface 110a of the substrate 110, while the

spacers

171 and 173 formed on the other portion of the bit lines 164 further extend into the substrate 110 and are located on the sidewalls of the bit line contacts 160a, as shown in fig. 2.

Then, an interlayer dielectric (ILD, not shown) layer may be formed on the substrate 110 to at least fill the space between the bit line 160 and the

spacers

171 and 173 and have a flat top surface, and an etching process is performed on the substrate 110 through the bit line 160 and the

spacers

171 and 173 as an etching mask to remove a portion of the ILD layer and the underlying substrate 110 (active region 103) and insulating region 101, so as to define a plurality of openings 105 between the adjacent bit line 160 and the

spacers

171 and 173 as plug openings. Wherein the bottom of each opening 105 is lower than the top surface 110a of the substrate 110, as shown in fig. 2. Next, as shown in fig. 3, another etching process is performed to remove the spacers 173 on the top surface 110a of the substrate 110, and only the spacers 173 protruding into the substrate 110 and located on the sidewalls of the bit line contacts 160a remain. Thus, the opening 105 may be enlarged to the opening 107 to expose a portion of the top surface 110a of the substrate 110.

As shown in fig. 4, deposition and etch-back processes are sequentially performed to form spacers 175 on the sidewalls of each opening 107, on the exposed top surface 110a of the substrate 110 and the remaining spacers 173; then, deposition and planarization (e.g., chemical mechanical polishing) processes are sequentially performed to form a conductive layer 191 in each opening 107, filling the opening 107 and directly contacting the underlying substrate 110 (active region 103) and the insulating region 101. In one embodiment, the spacers 175 preferably comprise a material different from the

spacers

171 and 173, such as silicon oxynitride, silicon hydroxide, etc., to reduce resistance; the conductive layer 191 is preferably formed by an epitaxial growth (epi growth) process, and may include, but is not limited to, polysilicon, silicon-phosphorus (SiP), and the like.

Then, as shown in fig. 5, an etching process is performed through the bit lines 160 and the spacers 171 as an etching mask to remove a portion of the spacers 175 and a portion of the conductive layer 191, and a metal silicide process or a salicide process is performed to simultaneously form a plurality of contacts 193 respectively filling the lower portion of the opening 107 and a metal silicide (silicide) layer 201 on top of each of the contacts 193. In detail, the contacts 193 are spaced apart from the bit lines 160 and isolated from each other by the

spacers

171, 173, and 175, and the bottom of each contact 193 directly contacts the active region 103 and/or the insulating region 101 in the substrate 110. The silicide layer 201 is formed over the contact 193 and the spacer 175 such that the end surfaces on both sides can be clamped on the spacerTop surface 175a of spacer 175 and sidewall 171a of spacer 171 contact spacer 175 (top surface 175a) and spacer 171 (sidewall 171a) simultaneously. In one embodiment, the metal silicide layer 201 includes, for example, titanium silicide (TiSi)_x) Tungsten silicide (WSi)_x) Tantalum silicide (TaSi)_x) Molybdenum silicide (MoSi)_x) Cobalt silicide (CoSi)_x) Or nickel silicide (NiSi)_x) And the like, but not limited thereto.

It should be noted that, since a portion of the conductive layer 191 is consumed during the formation of the metal silicide layer 201, when the portion of the spacers 175 and the conductive layer 191 are etched, the top surface (not shown) of the etched conductive layer 191 is slightly higher than the top surface 175a of the spacers 175. Thus, after the formation of the metal silicide layer 201, the top surface of the contact 193 may be substantially flush with the top surface 175a of the spacer 175, and the metal silicide layer 201 may be located slightly at the interface (interface) between the conductive layer 165 of the bit line 160 and the cap layer 167, as shown in fig. 5. Further, since the lattice structure of the metal silicide layer 201 is larger than that of the conductive layer 191, the volume thereof is slightly expanded to extend onto the top surface 175a of the spacer 175. Thus, the metal silicide layer 201 may directly contact the sidewall 171a of a portion of the spacer 171, the top surface 175a of the spacer 175, and the top surface of the contact 193, and have a relatively large width W2. On the other hand, after the etching process, the

spacers

175 and 171 disposed above the substrate 110 and the spacers 173 disposed in the substrate 110 may together form the spacer structure 170. Wherein the spacers 171 are directly disposed on the sidewalls of each bit line 160 and extend upward from the substrate 110, and the spacers 171 extend upward from the top surface 110a of the substrate 110 by a height h 1; spacers 175 are disposed between the bitlines 160 and the contacts 173 and also extend upward from the substrate 110, the spacers 175 extending upward from the top surface 110a of the substrate 110 to have a height h2, the height h1 being greater than the height h 2; the spacer 173 is located below a portion of the spacer 175 and extends into the substrate 110, as shown in fig. 5.

Subsequently, as shown in fig. 6, another deposition and planarization (e.g., chemical mechanical polishing) process is sequentially performed to form a conductive layer at least filling the opening 107 above the metal silicide layer 201 as a plurality of contacts 195 respectively filling the upper half of the opening 107. In an embodiment, the conductive layer includes, but is not limited to, a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W). The contact 195 is disposed above the metal silicide layer 201, and thus has a maximum width W2 in the direction D1, which is greater than the maximum width W1 of the contact 193 in the direction D1. As such, the contact 193, the metal silicide layer 201, and the contact 195 may collectively form a Storage Node Contact (SNC) 190 of the semiconductor device, which may directly contact the substrate 110 and/or the insulating region 101.

Finally, as shown in fig. 7, a plurality of storage node pads (SN pads) 220 are formed on the dielectric layer 210 on the substrate 110 to be aligned with the storage node plugs 190, respectively. In one embodiment, the storage node pad 220 is also made of a low-resistance metal material such as aluminum, titanium, copper or tungsten, for example, but not limited to, a material different from the contact 195. Preferably, in another embodiment, the storage node pad may be integrally formed with the contact 195 and may comprise the same material. Subsequently, a capacitor structure (not shown) may be further formed over the substrate 110 to directly contact and electrically connect to the underlying storage node pad 220. The capacitor structure includes a capacitor bottom electrode layer (not shown), a capacitor dielectric layer (not shown), and a capacitor top electrode layer (not shown) stacked in sequence, so as to form a plurality of capacitors (not shown) extending vertically as Storage Nodes (SN) of the semiconductor device 100. Thus, the storage node can be electrically connected to the transistor element through the storage node pad 220 and the storage node plug 190, thereby maintaining a good contact relationship between the capacitor structure and the storage node plug 190.

Thus, the semiconductor device 100 according to the first embodiment of the present invention is completed. According to the forming method of the present embodiment, a metal silicide forming process is additionally performed to form a metal silicide layer 201 between the contact 193 and the contact 195. The metal silicide layer 201 spans both the contact 193 and the spacer 175 such that both end surfaces can be sandwiched between the

spacers

171 and 175 to have a width W2 greater than the contact 193. Also, the metal silicide layer 201 may contact the spacers 171 (sidewalls) and the spacers 175 (top surface 175a) at the same time. Thus, the contact 195 disposed above the metal silicide layer 201 can have a larger contact area, so that the storage node plug 190 can have a more stable structure, and the storage node pad 220 and the storage node formed subsequently can be electrically connected to the transistor element through the storage node plug 190, thereby maintaining a good contact relationship between the capacitor structure and the storage node plug 190. In addition, the silicide layer 201 may include titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, nickel silicide, or the like, which may further reduce the resistance of the storage node plug 190, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

In addition, it should be readily apparent to those skilled in the art that other aspects of the semiconductor device and method for forming the same may be made without limitation to the present invention to meet the requirements of actual products. Further embodiments or variations of the method of the semiconductor device of the present invention are described below. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 8, a cross-sectional view of a semiconductor device 200 according to a second embodiment of the present invention is shown. The structure of the semiconductor device 200 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming a substrate 110, word lines 120 (not shown in fig. 8), bit lines 160, and the like, which are not described herein again. The main difference between the present embodiment and the first embodiment is that a spacer 276 is additionally formed on the metal silicide layer 201.

In detail, in the present embodiment, after the metal silicide layer 201 is formed, deposition and etch back processes are performed to form the spacer 276, and then the contact 295 is formed. Thus, the spacers 276 may be disposed above the spacers 175 and the metal silicide layer 201, and are coplanar with the top surfaces of the spacers 171. The spacers 276, the

spacers

175 and 171 disposed above the substrate 110, and the spacers 173 disposed in the substrate 110 may together form the spacer structure 170 of the present embodiment.

Therefore, the semiconductor device 200 in the second embodiment of the present invention also has an additional metal silicide layer 201, and the metal silicide layer 201 spans over the spacer 175, so that two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 to obtain a larger contact area. Thus, a more robust structure of the storage node plug 290 is obtained, and the resistance of the storage node plug 290 is further reduced by the metal silicide layer 201, thereby improving the electrical connection between the storage node plug 290 and the transistor element in the substrate 110.

Referring to fig. 9, a cross-sectional view of a semiconductor device 300 according to a third embodiment of the invention is shown. The structure of the semiconductor device 300 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming the substrate 110, the word lines 120 (not shown in fig. 9), the bit lines 160, and the like, which are not described herein again. The main difference between the present embodiment and the first embodiment is that the spacer structure 370 further includes a spacer 377 covering the spacer 175 and the spacer 171.

In detail, in the present embodiment, after forming the spacers 175 having the height h2 smaller than the spacers 171, deposition and etch-back processes are performed to form the spacers 377, and then the contacts 393, the metal silicide layer 203 and the contacts 395 are formed. Thus, the spacer 377 may be disposed between the spacer 175 and the contact 393 to directly contact the sidewall 171a of the spacer 171 and the top surface 175a and the sidewall of the spacer 175. The portion of the spacer 377 covering the top surface 175a of the spacer 175 may form a shoulder 377a corresponding to the height difference (h2-h1) between the

spacers

171 and 175, and the end surfaces of the metal silicide layer 203 on both sides may be clamped on the shoulder 377a of the spacer 377 and have a width W2 greater than that of the contact 393, as shown in fig. 9. In the present embodiment, the spacers 377 are also disposed above the substrate 110 and extend upward from the top surface 110a of the substrate 110 by the same height h1 as the spacers 171, but the present invention is not limited thereto. In another embodiment, the spacer 377 may have another height (not shown) greater than the height h2 and less than the height h 1.

Thus, the semiconductor device 300 according to the third embodiment of the present invention also has the metal silicide layer 203 additionally disposed, and the metal silicide layer 203 is disposed over the shoulder 377a of the spacer 377, so that both end surfaces can be sandwiched between the spacer 171 and the spacer 175, and can simultaneously contact the spacer 171 (the sidewall 171a) and the spacer 175 (the top surface 175 a). In this manner, the contact 395 disposed above the metal silicide layer 203 may obtain a larger contact area, so that the storage node plug 390 may obtain a more stable structure. In addition, the metal silicide layer 203 can further reduce the resistance of the storage node plug 390, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

Referring to fig. 10, a cross-sectional view of a semiconductor device 400 according to a fourth embodiment of the present invention is shown. The structure of the semiconductor device 400 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming a substrate 110, word lines 120 (not shown in fig. 10), bit lines 160, and the like, which are not described herein again. The main difference between the present embodiment and the first embodiment is that the top surface of the contact 493 is higher than the top surface 175a of the spacer 175, so that the silicide layer 204 formed by the silicide process has an inverted U-shape.

In detail, in the present embodiment, when the portion of the spacer 175 and the conductive layer 191 are etched, a top surface (not shown) of the etched conductive layer 191 is significantly higher than the top surface 175a of the spacer 175. Thus, after the formation of the metal silicide layer 204, the top surface of the contact 493 is higher than the top surface 175a of the spacer 175, so that a recess (not shown) is formed between the top surface of the contact 493 and the top surface 175a of the spacer 175, and then, since the lattice structure of the metal silicide layer 204 is larger than that of the conductive layer 191, the volume is slightly expanded to fill the recess, thereby forming the inverted U shape as shown in fig. 10. With this arrangement, the metal silicide layer 204 can directly contact the sidewall 171a of the spacer 171, the top surface 175a of the spacer 175, and a portion of the sidewall of the contact 493, as shown in fig. 10.

Thus, the semiconductor device 400 in the fourth embodiment of the present invention also has an additional metal silicide layer 204, and the metal silicide layer 204 is disposed over the spacer 175, so that the two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 and fill the recess between the top surface of the contact 493 and the top surface 175a of the spacer 175. Also, the metal silicide layer 204 may contact the spacers 171 (sidewalls 171a) and the spacers 175 (top surfaces 175a) at the same time. As such, the contact 495 disposed above the metal silicide layer 204 may also obtain a larger contact area, so that the storage node plug 490 may obtain a more robust structure. In addition, the metal silicide layer 204 can further reduce the resistance of the storage node plug 490, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

Referring to fig. 11, a cross-sectional view of a semiconductor device 500 according to a fifth embodiment of the invention is shown. The structure of the semiconductor device 500 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming the substrate 110, the word lines 120 (not shown in fig. 11), the bit lines 160, and the like, which are not described herein again. The main difference between the present embodiment and the first embodiment is that the top surface of the contact 593 is lower than the top surface 175a of the spacer 175, so that the silicide layer 205 formed by the silicide process may have a T-shape.

In detail, in the present embodiment, when the portion of the spacer 175 and the conductive layer 191 are etched, a top surface (not shown) of the etched conductive layer 191 is slightly lower than the top surface 175a of the spacer 175. Thus, after the formation of the metal silicide layer 205, the top surface of the contact 593 may be lower than the top surface 175a of the spacer 175, such that there may be a height difference (not shown) between the top surface of the contact 593 and the top surface 175a of the spacer 175, and then, since the lattice structure of the metal silicide layer 205 is larger than that of the conductive layer 191, the volume may slightly expand and extend onto the top surface 175a of the spacer 175, forming the T-shape as shown in fig. 11. With this arrangement, the metal silicide layer 205 may have a first portion 205a and a second portion 205b with different widths, wherein the width of the first portion 205a is equal to the maximum width W1 of the contact 593 in the direction D1, and the width of the second portion 205b is equal to the maximum width W2 of the contact 595 in the direction D1. Moreover, the metal silicide layer 205 may directly contact the sidewall 171a of the spacer 171, the top surface 175a of the spacer 175, and the sidewall, resulting in a more robust structure, as shown in fig. 11.

Thus, the semiconductor device 500 in the fifth embodiment of the present invention also has an additional metal silicide layer 205, and the metal silicide layer 205 is disposed over the spacer 175, so that two side end surfaces can be sandwiched between the spacer 171 and the spacer 175. Moreover, the metal silicide layer 205 has the first portion 205a and the second portion 205b with different widths, and can simultaneously contact the spacer 171 (the sidewall 171a) and the spacer 175 (the top surface 175a), so as to form a more stable structure. As such, the upper contact 595 disposed above the metal silicide layer 205 may also obtain a larger contact area, further improving the structural stability of the storage node plug 590. Meanwhile, the metal silicide layer 205 may further reduce the resistance of the storage node plug 590, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

Referring to fig. 12, a cross-sectional view of a semiconductor device 600 according to a sixth embodiment of the invention is shown. The structure of the semiconductor device 600 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming the substrate 110, the word lines 120 (not shown in fig. 12), the bit lines 160, and the like, which are not described herein again. The main difference between this embodiment and the first embodiment is that the parameter conditions of the metal silicide process are adjusted such that the formed metal silicide layer 206 has an arch bridge shape.

In detail, in the present embodiment, when the portion of the spacer 175 and the conductive layer 191 are etched, the top surface (not shown) of the etched conductive layer 191 is slightly higher than the top surface 175a of the spacer 175, and the parameter conditions (such as the silicidation rate) of the silicidation process are controlled. In this manner, the metal silicide layer 206 having a bridge shape may be formed, and after the metal silicide layer 206 is formed, the top surface of the contact 693 may present a cambered surface, two sides of which may be substantially flush with the top surface 175a of the spacer 175, and the center of which is slightly higher than the top surface 175a of the spacer 175, as shown in fig. 12. Accordingly, the metal silicide layer 206 may also have an arc-shaped top surface 206a with a center higher than the top surface 175a, and further extend onto the top surface 175a of the spacer 175 to form an arch bridge structure as shown in fig. 12. Thus, the end surfaces of the metal silicide layer 206 on both sides can be sandwiched between the spacers 175 to have a width W2 larger than the contact 693, so as to increase the contact area between the metal silicide layer 206 and the upper contact 695, thereby effectively improving the structural stability of the storage node plug 690.

Thus, the semiconductor device 600 in the sixth embodiment of the present invention also has the metal silicide layer 206 additionally disposed, and the metal silicide layer 206 is disposed over the spacer 175, so that the two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 and contact the spacer 171 (the sidewall 171a) and the spacer 175 (the top surface 175 a). Moreover, the arc-shaped top surface 206a of the metal silicide layer 206 can further increase the contact area of the contact 695, reduce the resistance of the storage node plug 690, and obtain a more optimized structure. Thus, the electrical connection between the storage node plug 690 and the transistor element in the substrate 110 may be further improved.

Referring to fig. 13, a cross-sectional view of a semiconductor device 700 according to a seventh embodiment of the invention is shown. The structure of the semiconductor device 700 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, and includes forming the substrate 110, the word lines 120 (not shown in fig. 13), the bit lines 160, and the like, which are not described herein again. The main difference between this embodiment and the first embodiment is that the parameter conditions of the metal silicide process are adjusted such that the formed metal silicide layer 207 may have a step shape.

In detail, in the present embodiment, when the portion of the spacer 175 and the conductive layer 191 are etched, the top surface (not shown) of the etched conductive layer 191 is slightly lower than the top surface 175a of the spacer 175, and the parameters of the silicidation process (such as the silicidation rate) are controlled, so that the silicide layer 207 can be proportionally expanded to the top surface 175a of the spacer 175 during the formation. In this way, the metal silicide layer 207 having a step shape may be formed, which includes the first portion 207a located above the contact 793 and the second portion 207b located above the spacer 175, and the top surfaces of the first portion 207a and the second portion 207b have a significant height difference, as shown in fig. 13. As such, the end surface of the second portion 207b of the metal silicide layer 207 may also be sandwiched between the spacers 175, such that the metal silicide layer 207 may have a width W2 greater than the contact 693 as a whole, thereby increasing the contact area between the metal silicide layer 207 and the contact 795 thereabove and effectively improving the structural stability of the storage node plug 790.

Thus, the semiconductor device 700 in the seventh embodiment of the present invention also has the additionally disposed metal silicide layer 207, and the metal silicide layer 207 spans over the spacer 175, so that the two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 and contact the spacer 171 (the sidewall 171a) and the spacer 175 (the top surface 175 a). In addition, the metal silicide layer 207 having the step shape may further increase the contact area of the contact 795, reduce the resistance of the storage node plug 790 and obtain a more optimized structure. Thus, the electrical connection between the storage node plugs 790 and the transistor elements in the substrate 110 may be further improved.

In general, the semiconductor device of the present invention additionally provides a metal silicide layer between the lower contact and the upper contact through a metal silicide process, such that the metal silicide layer can straddle the spacers on both sides of the bit line. Two side end faces of the metal silicide layer are clamped between the gap walls and have a width larger than that of the lower contact. Therefore, the metal silicide layer and the upper contact can have a larger contact area correspondingly, so that the storage node plug of the semiconductor device can obtain a more stable structure. In addition, the metal silicide layer may include titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, nickel silicide, etc. to further reduce the resistance of the storage node plug and further improve the electrical connection between the storage node plug and the transistor element. Therefore, the semiconductor device of the invention can have more optimized structure and device performance.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of bit lines disposed on the substrate;

a plurality of first contacts disposed on the substrate and spaced apart from the bit lines;

the first clearance wall is arranged between each bit line and the first contact, is arranged on the substrate and extends upwards to a first height from the top surface of the substrate;

a second spacer disposed between the first spacer and the first contact, the second spacer disposed on the substrate and extending upward from the top surface of the substrate by a second height, wherein the first height is higher than the second height;

the plurality of second contacts are respectively arranged above the first contacts; and

and the metal silicide layer is arranged between the first contact and the second contact, wherein the end face of the metal silicide layer is clamped between the second gap wall and the first gap wall.

2. The semiconductor device according to claim 1, wherein a maximum width of the metal silicide layer is larger than a maximum width of the first contact.

3. The semiconductor device according to claim 1, wherein the metal silicide layer directly contacts sidewalls of the first spacers and a top surface of the second spacers.

4. The semiconductor device according to claim 1, wherein a top surface of the first contact is higher than a top surface of the second spacer, and the metal silicide layer directly contacts a sidewall of the first spacer, the top surface of the second spacer, and a portion of the sidewall of the first contact.

5. The semiconductor device according to claim 4, wherein the metal silicide layer has an inverted U-shape.

6. The semiconductor device according to claim 1, wherein a top surface of the first contact is lower than the top surface of the second spacer, and wherein the metal silicide layer directly contacts a sidewall of the first spacer and the top surface and the sidewall of the second spacer.

7. The semiconductor device according to claim 6, wherein the metal silicide layer has a first portion and a second portion which are different in width, the first portion being provided above the second portion and having a larger width.

8. The semiconductor device according to claim 1, wherein the bit lines include a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines are alternately arranged with each other, and the second bit lines directly contact the substrate.

9. The semiconductor device according to claim 8, wherein the first bit line and the second bit line respectively comprise a semiconductor layer, a barrier layer and a conductive layer stacked in sequence.

10. The semiconductor device of claim 8, further comprising third spacers disposed below the second spacers on opposite sides of the second bit line, the third spacers extending within the substrate.

11. The semiconductor device according to claim 1, further comprising a fourth spacer disposed between the second spacer and the first contact, wherein the fourth spacer directly contacts a sidewall of the first spacer and a top surface and a sidewall of the second spacer, a portion of the fourth spacer covering the top surface of the second spacer has a shoulder, and the end surface of the metal silicide layer is sandwiched between the shoulders.

12. The semiconductor device according to claim 11, wherein the fourth spacer has a third height, wherein the third height is higher than the second height and is less than or equal to the first height.

13. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a plurality of bit lines on the substrate;

forming a plurality of first contacts on the substrate, wherein the bit lines and the first contacts are alternately arranged;

forming a first spacer on the substrate, the first spacer being located between each bit line and the first contact, the first spacer being disposed on the substrate and extending upward from a top surface of the substrate by a first height;

forming a second spacer on the first spacer and between the first spacer and the first contact, the second spacer being disposed on the substrate and extending upward from the top surface of the substrate by a second height, the first height being higher than the second height;

forming a plurality of second contacts above the first contacts respectively; and

and forming a metal silicide layer on the substrate, wherein the metal silicide layer is positioned between the first contact and the second contact, and the end face of the metal silicide layer is clamped between the second gap wall and the first gap wall.

14. The method of claim 13, wherein the forming of the bit line further comprises:

forming the first spacer and a third spacer on the sidewall of each bit line, wherein the top surface of the first spacer is flush with the top surface of the third spacer;

removing a portion of the third spacer; and

forming the second spacer on the first spacer, the second spacer being on the remaining portion of the third spacer.

15. The method of claim 13, further comprising:

forming a fourth spacer on the second spacer, the fourth spacer being located between the second spacer and the first contact, the fourth spacer directly contacting a sidewall of the first spacer and a top surface and a sidewall of the second spacer, a portion of the fourth spacer covering the top surface of the second spacer having shoulders, and the end surface of the metal silicide layer being sandwiched between the shoulders.

16. The method of claim 13, wherein the metal silicide layer is formed after the formation of the bit line and the second spacer.

17. The method of claim 16, wherein the forming of the bit line and the second spacer further comprises:

forming a conductive layer between each bit line and the second spacer;

etching the conductive layer; and

and carrying out a metal silicification manufacturing process to form the metal silicide layer and the first contact.

18. The method of claim 17, wherein said metal silicide layer directly contacts sidewalls of said first spacers and said top surface of said second spacers.

19. The method of claim 17, wherein a top surface of said first contact is higher than said top surface of said second spacer, and wherein said metal silicide layer directly contacts sidewalls of said first spacer, said top surface of said second spacer, and a portion of said first site.

20. The method of claim 17, wherein a top surface of said first contact is lower than said top surface of said second spacer, and wherein said metal silicide layer directly contacts sidewalls of said first spacer and said top and sidewalls of said second spacer.