CN116723697A

CN116723697A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN116723697A
Application number: CN202310728614.0A
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-06-19
Filing date: 2023-06-19
Publication date: 2023-09-08

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The gate structure is spaced apart on the substrate. The first dielectric layer is arranged on the substrate and covers the gate structure. The second dielectric layer is arranged on the substrate and covers the first dielectric layer. The conductive layer is disposed on the substrate and on the second dielectric layer. The first insulating structure is arranged in the conductive layer and the second dielectric layer and penetrates through the bottom of the second dielectric layer. Therefore, the wires in the peripheral area can be effectively cut off through the arrangement of the first insulating structure, and short circuit is avoided.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having a gate structure and a method for fabricating the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor devices must meet the requirements of high integration and high density. For the dynamic random access memory (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the dynamic random access memory with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure. In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to store information, and each memory cell may be formed by a transistor element and a capacitor element connected in series to receive voltage information from Word Lines (WL) and Bit Lines (BL). In response to the product requirement, the density of the memory cells in the array region should be continuously increased, which causes the difficulty and complexity of the related manufacturing process and design to be continuously increased. Accordingly, the prior art or structure is further improved to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

An object of the present invention is to provide a semiconductor device and a method for fabricating the same, in which a first insulating structure disposed in and penetrating a conductive layer and a dielectric layer is formed, and the conductive layer is cut off to form a plurality of conductive lines electrically connected to a substrate. Therefore, the structure defect of the first layer of metal interconnection line above the grid structure is effectively improved, and the problems of short circuit and the like caused by incomplete separation among the metal interconnection lines are avoided.

In order to achieve the above object, an embodiment of the present invention provides a semiconductor device, which includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a conductive layer, and a first insulating structure. A plurality of gate structures are spaced apart on the substrate. The first dielectric layer is arranged on the substrate and covers the gate structure. The second dielectric layer is arranged on the substrate and covers the first dielectric layer. The conductive layer is arranged on the substrate and is positioned on the second dielectric layer. The plurality of first insulating structures are arranged in the conducting layer and the second dielectric layer and penetrate through the bottom of the second dielectric layer.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. A substrate is provided, and a plurality of gate structures are formed and arranged on the substrate in a separated manner. And forming a first dielectric layer on the substrate to cover the gate structure. And forming a second dielectric layer on the substrate and covering the first dielectric layer. And forming a conductive layer on the substrate and on the second dielectric layer. And forming a plurality of first insulating structures in the conductive layer and penetrating through the bottoms of the conductive layer and the second dielectric layer.

Drawings

The accompanying drawings provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

Fig. 3 to 9 are schematic views showing a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention, wherein:

fig. 3 is a schematic cross-sectional view of the semiconductor device after forming a gate structure;

fig. 4 is a schematic cross-sectional view of the semiconductor device after formation of a storage node plug;

fig. 5 is a schematic cross-sectional view of the semiconductor device after forming a metal layer;

FIG. 6 is a schematic cross-sectional view of a semiconductor device after forming a storage node pad;

FIG. 7 is a schematic cross-sectional view of a semiconductor device after performing a photolithography process;

FIG. 8 is a schematic cross-sectional view of a semiconductor device after another photolithographic process is performed; and

fig. 9 is a schematic cross-sectional view of the semiconductor device after forming an opening.

Wherein reference numerals are as follows:

10. 30 semiconductor device

100. Substrate and method for manufacturing the same

101. Peripheral region

103. Storage area

111. 113 shallow trench isolation

112. 114, 116 insulating material

122. Gate dielectric layer

123. Dielectric layer

124. Silicon oxide layer

126. Silicon nitride layer

128. Silicon oxide layer

131. Gate structure

132. Semiconductor layer

133. Bit line

133a bit line plug

134. Barrier layer

136. Metal layer

138. Cover layer

141. Gate spacer

142. First spacer

144. Third spacer of second spacer 146

143. Bit line spacing wall

150. A first dielectric layer

152. A second dielectric layer

160. 360 conductive layer

160a, 360b linker fragment

161. Plug-in connector

163. Storage node plug

164. Metal silicide layer

166. Barrier layer

168. Metal layer

170. 370 first insulating structure

172. 174, 176, 372, 374, 376 first insulating structure

178. Storage node bonding pad

180. Insulating layer

272. 274, 276 first opening

378. Insulating layer

380. Second insulating structure

Detailed Description

The following description sets forth the preferred embodiments of the present invention and, together with the accompanying drawings, provides a further understanding of the invention, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the invention pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the invention to accomplish other embodiments.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device 10 according to a first embodiment of the present invention. As shown in fig. 1, the semiconductor device 10 includes a substrate 100, a plurality of gate structures 131, a first dielectric layer 150, a second dielectric layer 152, a conductive layer 160, and a plurality of first insulating structures 170. The substrate 100 may include, but is not limited to, a silicon substrate (silicon substrate), a silicon-containing substrate (silicon-containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or other suitable materials. The gate structures 131 are disposed on the substrate 100 with a separation therebetween, and are covered by the first dielectric layer 150, and the second dielectric layer 152 further covers the first dielectric layer 150. It should be noted that, a conductive layer 160 is further disposed above the second dielectric layer 152 and is entirely covered, and a plurality of first insulating structures 170 are disposed in the conductive layer 160 and the second dielectric layer 152, and each of the first insulating structures 170 penetrates through the bottoms of the conductive layer 160 and the second dielectric layer 152, so as to divide the conductive layer 160 into a plurality of connection segments 160a. In the present embodiment, the connection segments 160a are disposed alternately with the first insulating structures 170 in the horizontal direction to serve as wires (metal lines) electrically connected to the source (not shown), the drain (not shown), or the gate structure 131, respectively, but not limited thereto. Therefore, the first metal interconnection line (M0 interconnect) disposed above the gate structure 131 is effectively isolated by the arrangement of the first insulating structure 170, so as to avoid the problems of short circuit between the first metal interconnection lines due to incomplete isolation.

Preferably, the bottom most surface of each first insulating structure 170 is located on a different plane. The first insulating structure 172 sequentially passes through the conductive layer 160, the second dielectric layer 152 and a portion of the first dielectric layer 150, such that the bottom surface of the first insulating structure 172 is between the top surface and the bottom surface of the first dielectric layer 150, and the first insulating structures 174 and 176 sequentially pass through the conductive layer 160, the second dielectric layer 152 and the first dielectric layer 150 covering the top surface of the gate structure 111, such that the bottom surfaces of the first insulating structures 174 and 176 physically contact the top surface of the third spacer 146 covering the gate structure 131, or further pass through the third spacer 146 to physically contact the top surface of the gate structure 131, so as to effectively isolate each conductive line. In an embodiment, the first dielectric layer 150 and the second dielectric layer 152 include different insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, for example, if the first dielectric layer 150 includes silicon oxynitride, the second dielectric layer 152 includes silicon nitride or silicon carbonitride, but not limited thereto. The first insulating structure 170 is made of an insulating material different from the first dielectric layer 150, such as silicon nitride or silicon carbonitride, and the conductive layer 160 is made of a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), preferably including but not limited to tungsten.

As further shown in fig. 1, the substrate 100 of the semiconductor device 10 further includes a region with relatively low component integration, such as a peripheral region (peripheral region) 101, and another region with relatively high component integration, such as a memory region (cell region) 103, where the memory region 103 and the peripheral region 101 are disposed, for example, but not limited to, adjacently. At least one insulating region, such as shallow trench isolation (shallow trench isolation, STI) 111, 113, is disposed in the peripheral region 101 and the storage region 103 of the substrate 100, and a plurality of active areas (AA, not shown) are defined in the substrate 100. The first insulating structure 170, the second dielectric layer 152, the first dielectric layer 150 and the gate structure 131 are all located in the peripheral region 101 of the substrate 100, and the gate structure 131 is directly disposed on the active region in the peripheral region 101. In one embodiment, the shallow trench isolations 111, 113 in the peripheral region 101 and the storage region 103 have a composite layer structure and a single layer structure, respectively. The shallow trench isolation 111 in the peripheral region 101 has a relatively large extension in the horizontal direction in response to the low integration of the components in the peripheral region 101, and includes an insulating material 112 (e.g., silicon oxide), an insulating material 114 (e.g., silicon nitride), an insulating material 116 (e.g., silicon oxynitride), and the like, which are sequentially stacked. The shallow trench isolation 113 in the storage region 103 has a relatively small extension corresponding to the high integration of the components in the storage region 103, and includes only the insulating material 112 (e.g. silicon oxide), but is not limited thereto. The shallow trench isolation 111, 113 is formed, for example, by performing an etching process to form a plurality of trenches (not shown) in the substrate 100, then filling at least one insulating material layer (not shown) in the trenches, and forming the shallow trench isolation 111, 113 with a surface flush with the top surface of the substrate 100 by a planarization process, but not limited thereto.

In detail, the gate structure 131 includes, for example, a polysilicon gate structure, a metal gate structure, or a gate structure formed by an integrated memory manufacturing process. In the present embodiment, the gate structure 131 includes a gate dielectric layer 122, a semiconductor layer 132, a barrier layer 134, a metal layer 136 and a cap layer 138 sequentially stacked on the substrate 100 from bottom to top. Gate spacers 141 are disposed on sidewalls of the gate structure 131. In one embodiment, the gate dielectric layer 122 comprises an insulating material such as silicon oxide, the semiconductor layer 132 comprises a semiconductor material such as doped polysilicon, doped amorphous silicon, etc., the barrier layer 134 comprises a conductive barrier material such as titanium and/or titanium nitride (TiN), tantalum (Ta), and/or tantalum oxide (TaN), the metal layer 136 comprises copper, aluminum, tungsten, or other suitable low-resistivity conductive material, and the cap layer 138 comprises an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. The gate spacer 141 has a composite layer structure, for example, and includes a first spacer 142 and a second spacer 144 sequentially disposed on the side surfaces of the gate structure 131 in the horizontal direction, and a third spacer 146 covering the side surfaces and the top surface of the gate structure 131. In one embodiment, the first spacers 142 and the third spacers 146 comprise the same insulating material, such as silicon nitride, silicon carbonitride, etc., and the second spacers 144 comprise an insulating material different from the first spacers 142, 146, such as silicon oxide, silicon oxynitride, etc., but not limited thereto. In other embodiments, the spacer may have a single-layer structure.

On the other hand, the semiconductor device 10 further includes a plurality of bit lines 133 disposed in the memory region 103. In one embodiment, the fabrication process of the bit lines 133 is integrated with the fabrication process of the gate structures 131 disposed in the peripheral region 101, for example, such that each bit line 133 and each gate structure 131 comprise similar components and materials. In this embodiment, each bit line 133 is disposed on the dielectric layer 123, for example, and also includes a semiconductor layer 132 (e.g., including polysilicon), a barrier layer 134 (e.g., including titanium and/or titanium nitride), a metal layer 136 (e.g., including low-resistance metal such as tungsten, aluminum, or copper), and a cap layer 138 (e.g., including silicon oxide, silicon nitride, or silicon oxynitride). Wherein each bit line 133 is electrically connected to the active region in the storage region 103 by a Bit Line Contact (BLC) 133a formed correspondingly below the Bit Line Contact (BLC) extending into the substrate 100. The dielectric layer 123 includes, for example, a silicon oxide layer 124, a silicon nitride layer 126, and a silicon oxide layer 128, which are sequentially stacked to have an oxide-nitride-oxide (ONO) structure. In addition, a bit line spacer 143 is disposed on the sidewall of each bit line 133, and the process of fabricating the bit line spacer may be integrated with the process of fabricating the gate spacer 141 disposed in the peripheral region 101, and includes, but is not limited to, a first spacer 142 (e.g., including silicon nitride, silicon carbonitride), a second spacer 144 (e.g., including silicon oxide, silicon oxynitride) and a third spacer 146 (e.g., including silicon nitride, silicon carbonitride) sequentially stacked on the side surface of each bit line 133.

The semiconductor device 10 further includes a plurality of plugs 161 provided in the peripheral region 101 and a storage node plug 163 provided in the storage region 103. Plug 161 is disposed in first dielectric layer 150 and second dielectric layer 152 on opposite sides of gate structure 131 and physically contacts conductive layer 160 such that conductive layer 160 is electrically connected to the source or the drain disposed in substrate 100 through plug 161. Each plug 161 includes a metal silicide layer 164, a barrier layer 166, and a metal layer 168 sequentially stacked from bottom to top, wherein the metal layer 168 of the plug 161 is formed integrally with the conductive layer 160, for example, and includes the same material (including aluminum, titanium, copper, or tungsten, for example), but not limited thereto.

The storage node plugs 163 are alternately arranged with the bit lines 133 in the storage region 103 and electrically isolated from the bit lines 133 through the bit line space walls 143 on the sidewalls of the bit lines 133. A plurality of storage node pads (SN pads) 178 are further disposed above the storage node plugs 163, each including a metal silicide layer 164, a barrier layer 166, and a metal layer 168 stacked sequentially from bottom to top, and physically contacting each storage node plug 163. The storage node pads 178 are isolated from the insulating layer 180 by the bit line spacers 143. In one embodiment, the fabrication process of the storage node pads 178 is integrated with the fabrication process of the plugs 161, such that the storage node pads 178 include components and materials similar to the plugs 161, but are not limited thereto. In this manner, each storage node pad 178 is also electrically connected to the substrate 100 through the storage node plug 163, thereby receiving and transmitting voltage signals from the substrate 100 (e.g., the source or drain of a transistor device within the substrate 100). In one embodiment, the storage node plug 163 comprises an epitaxial material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and the metal silicide layer 164 comprises cobalt disilicide (CoSi) ₂ ) Titanium silicide (TiS)i ₂ ) Or nickel silicide (Ni ₂ Si), the barrier layer 166 includes, but is not limited to, conductive barrier materials such as titanium and/or titanium nitride, tantalum and/or tantalum oxide.

With this arrangement, the semiconductor device 10 of the present embodiment may cut the conductive layer 160 to form a plurality of connection segments 160a by penetrating the first insulating structure 170 disposed in the conductive layer 160 and the dielectric layer (including the first dielectric layer 150 and the second dielectric layer 152), and the connection segments may be used as the conductive lines electrically connected to the source, drain or gate structures 131, respectively. And, by locating the bottommost surfaces of the first insulating structures 170 on different planes, the wires with different positions are ensured to be electrically isolated from each other. Thus, the first metal interconnection line disposed above the gate structure 131 has a complete and reliable structure, so as to avoid the problems of short circuit and the like caused by incomplete separation between the first metal interconnection lines. The semiconductor device 10 of the present embodiment has an optimized structure and performance, and a capacitor structure (not shown) electrically connected to the storage node plug 163 can be continuously formed in the storage region 103 in the subsequent manufacturing process, thereby forming a dynamic random access memory (dynamic random access memory, DRAM) device and achieving more optimized operation performance.

It should be readily understood by those skilled in the art that the semiconductor device of the present invention may have other aspects and is not limited to the foregoing embodiments, so as to meet the needs of actual products. Further embodiments or variations of the semiconductor device of the present invention will be described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present invention are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a semiconductor device 30 according to a second embodiment of the invention. The semiconductor device 30 of the present embodiment is substantially the same as the semiconductor device 10 of the previous embodiment, with the main difference that the semiconductor device 30 includes a plurality of first insulating structures 370 and at least one second insulating structure 380.

In detail, each of the first insulating structure 370 and the second insulating structure 380 at least penetrates through the conductive layer 360 and a portion of the second dielectric layer 152, and the bottom surfaces of each of the first insulating structure 370 and the second insulating structure 380 are located on different planes. The first insulating structures 372, 374, 376 sequentially penetrate through the conductive layer 360, the second dielectric layer 152, and at least a portion of the first dielectric layer 150, such that the bottom surfaces of the first insulating structures 372, 374, 376 physically contact the third spacers 146 on the first dielectric layer 150 and the gate structure 131, respectively, or further penetrate through the third spacers 146 to physically contact the top surfaces of the gate structure 131. Accordingly, the conductive layer 360 is also cut off by the first insulating structure 370 to form a plurality of connection segments 360a and 360b, which are respectively used as wires for electrically connecting the source electrode, the drain electrode or the gate electrode 131.

It should be noted that, part of the connection segments 360b are disposed between the plugs 161 at both sides of the gate structure 131 and are alternately arranged with the respective first insulating structures 370. Wherein each connecting segment 360b includes an arcuate top surface, as shown in fig. 2. The second insulating structure 380 is disposed between the connecting segment 360b and the plug 361, and sequentially penetrates the conductive layer 360 and a portion of the second dielectric layer 152. That is, the bottom most surface of the second insulating structure 380 is located between the top and bottom surfaces of the second dielectric layer 152 without contacting the first dielectric layer 150. Therefore, the second insulating structure 380 physically contacts the plug 161 and the adjacent connecting segment 360b (i.e. the conductive layer 360) at the same time, so that the plug 161 and the connecting segment 360b are electrically isolated from each other, thereby effectively blocking unnecessary electrical connection between the plug 161 and the adjacent connecting segment 360b, and avoiding the problems of derivative short circuit and the like. In addition, in the present embodiment, the first insulating structure 370 and the second insulating structure 380 are further connected to each other by the insulating layer 378 disposed above, so that the manufacturing processes of the first insulating structure 370, the second insulating structure 380 and the insulating layer 378 can be integrated with each other to form the first insulating structure 370 and the second insulating structure 380 simultaneously. In this operation, the insulating layer 378, the first insulating structure 370 and the second insulating structure 380 may all include the same insulating material, such as silicon nitride, silicon carbonitride, etc., but not limited thereto.

With this arrangement, the semiconductor device 30 of the present embodiment can also cut the conductive layer 360 into a plurality of connection segments 360a, 360b by means of the first insulating structure 370 and the second insulating structure 380 penetrating the conductive layer 360 and the dielectric layer (including the first dielectric layer 150 and/or the second dielectric layer 152), and serve as the conductive lines electrically connecting the source, drain or gate structures 131, respectively. In addition, the first insulating structures 370 completely penetrate through the second dielectric layer 152, so that the second insulating structures 380 further isolate the connection between the plug 161 and the adjacent connecting segment 360b, and the problems such as derivative short circuit are more effectively avoided. Thus, the first metal interconnection line disposed above the gate structure 131 has a complete and reliable structure, so as to avoid the problem of short circuit between the first metal interconnection lines due to incomplete isolation. Thus, the semiconductor device 30 of the present embodiment has an optimized structure and performance, and a capacitor structure (not shown) electrically connected to the storage node plug 163 can be formed in the storage region 103 in the subsequent manufacturing process, thereby forming a dram device and achieving more optimized operation performance.

In order to enable those skilled in the art to which the present invention pertains to easily understand the semiconductor device 10 and the semiconductor device 30 of the present invention, the following description will further be made with respect to the manufacturing methods of the semiconductor device 10 and the semiconductor device 30 of the present invention.

Fig. 3 to 9 are schematic views illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the invention. First, as shown in fig. 3, a substrate 100 is provided, shallow trench isolations 111 and 113 are formed in a peripheral region 101 and a storage region 103 of the substrate 100, and a plurality of active regions (not shown) are defined in the peripheral region 101 and the storage region 103 of the substrate 100, respectively. Next, a plurality of gate structures 131 and a plurality of bit lines 133 are formed on the peripheral region 101 and the storage region 103 of the substrate 100, respectively, in a similar process. For example, a process of fabricating the gate structure 131 is performed first and then a process of fabricating the bit line 133 is performed, wherein the gate structure 131 and each bit line 133 have similar structures and materials, for example, each include a semiconductor layer (e.g., including polysilicon) 132, a barrier layer 134 (e.g., including titanium and/or titanium nitride), a metal layer 136 (e.g., including low-resistance metal such as tungsten, aluminum or copper) and a cap layer 138 (e.g., including silicon oxide, silicon nitride or silicon oxynitride), which are sequentially stacked on the substrate 100, and the gate spacers 141 disposed on the sidewalls of the gate structure 131 may be formed by the same process as the bit line spacers 143 disposed on the sidewalls of the bit line 133, respectively, but include a first spacer 142 (e.g., including silicon nitride, silicon carbonitride), a second spacer 144 (e.g., including silicon oxide, silicon oxynitride) and a third spacer 146 (e.g., including silicon nitride, silicon carbonitride) which are sequentially stacked in the horizontal direction.

As shown in fig. 4, a first dielectric layer 150 and a second dielectric layer 152 are formed on the peripheral region 101 of the substrate 100, covering the gate structures 131 and filling the space between the gate structures 131. Then, an epitaxial process is performed on the memory region 103 of the substrate 100, and storage node plugs 163 are formed on the substrate 100 between adjacent bit lines 133, respectively. In one embodiment, the storage node plug 163 includes, but is not limited to, an epitaxial material such as silicon, silicon-phosphorus, etc.

As shown in fig. 5, a plurality of through holes (not shown) penetrating the second dielectric layer 152 and the first dielectric layer 150 are formed in the peripheral region 101 through a mask layer (not shown) formed on the substrate 100, exposing a portion of the substrate 100. Then, the mask layer is removed, and a metal silicide process and at least one deposition process are sequentially performed on the substrate 100, a metal silicide layer 164 (including cobalt disilicide, titanium silicide, or nickel silicide, for example) is simultaneously formed on the exposed substrate 100 of the peripheral region 101 and the storage node plug 163 of the storage region 103, and a barrier layer 166 and a metal layer 168 are sequentially stacked. Wherein, the barrier layer 166 and the metal layer 168 formed in the peripheral region 101 are partially disposed in the through hole, and partially formed outside the through hole to further cover the second dielectric layer 152. Thus, the barrier layer 166 and the metal layer 168 formed in the via together with the underlying metal silicide layer 164 form the plug 161. Plugs 161 are formed on opposite sides of each gate structure 131 to electrically connect to the source or the drain disposed in the substrate 100, and a barrier layer 166 and a metal layer 168 formed over the second dielectric layer 152 together form a conductive layer 160 and physically contact the plugs 161. That is, the plug 161 and the conductive layer 160 include a film layer integrally formed, but not limited thereto.

On the other hand, the barrier layer 166 and the metal layer 168 formed in the memory region 103 are partially formed in the space between the bit lines 133, and are also partially formed outside the space and further cover the top surfaces of the bit lines 133. Wherein the barrier layer 166 and the metal layer 168 formed in and out of the space comprise an integrally continuous film layer, and are integrally formed.

As shown in fig. 6, the barrier layer 166 and the metal layer 168 covering the top surface of the bit line 133 are partially removed through another mask layer (not shown) formed on the substrate 100, and a plurality of through holes (not shown) partially exposing the bit line 133 and the bit line space wall 143 are formed in the memory region 103, while a plurality of storage node pads 178 are formed. Then, a deposition and etch back process is performed to fill the insulating layer 180 into the through holes, so that the storage node pads 178 are isolated from each other. In this operation, each storage node pad 178 is partially formed in the space between the bit lines 133 and partially formed in the via, but is not limited thereto. In this way, each storage node pad 178 is also electrically connected to the source or the drain disposed in the substrate 100 through the storage node plug 163 disposed below, and receives and transmits a voltage signal from the substrate 100.

As shown in fig. 7, a photolithography process is performed to form at least one first opening 276 by partially removing the conductive layer 160, the second dielectric layer 152 and the first dielectric layer 150 in the peripheral region 101 through a further mask layer (not shown) formed on the substrate 100. It should be noted that the photolithography process is, for example, to use the cap layer 138 of the gate structure 131 as an etching barrier layer, so that the first opening 276 vertically penetrates the conductive layer 160, the second dielectric layer 152, the first dielectric layer 150 and the third spacer 146 covering the top surface of the gate structure 131, and part of the cap layer 138 is exposed. That is, the bottom most surface of the first opening 276 is coplanar with the top surface of the cap layer 138.

As shown in fig. 8, another photolithography process is performed to form at least one first opening 274 by forming a further mask layer (not shown) on the substrate 100, and partially removing the conductive layer 160, the second dielectric layer 152 and the first dielectric layer 150 in the peripheral region 101 again. It should be noted that the other photolithography process is, for example, to use the third spacer 146 covering the top surface of the gate structure 131 as an etching barrier layer, so that the first opening 274 vertically penetrates the conductive layer 160, the second dielectric layer 152 and the first dielectric layer 150 covering the top surface of the gate structure 131, and the top surface of the third spacer 146 is partially exposed. That is, the bottom most surface of the first opening 274 is coplanar with the top surface of the third spacer 146.

As shown in fig. 9, a further photolithography process is performed to form a plurality of first openings 272 through a further mask layer (not shown) formed on the substrate 100, and the conductive layer 160, the second dielectric layer 152 and the first dielectric layer 150 in the peripheral region 101 are partially removed again. It should be noted that the further photolithography process is, for example, to control the etching time, so that each of the first openings 272 vertically penetrates the conductive layer 160, the second dielectric layer 152, and a portion of the first dielectric layer 150. That is, the bottommost surface of each first opening 272 is between the top and bottom surfaces of the first dielectric layer 150. Thus, after the first openings 272, 274, and 276 are formed individually, the conductive layer 160 is cut accordingly to form a plurality of connection segments 160a, which are arranged alternately with the respective first insulating structures 170 in the horizontal direction. The connection segments 160a are mainly formed between the plugs 161 on both sides of the gate structure 131 to serve as conductive lines electrically connected to the gate structure 131, but not limited thereto.

Then, the deposition and etching back process is continued in the peripheral region 101, and the first insulating structures 172, 174, 176 having the bottommost surfaces on different planes are formed in the respective first openings 272, 274, 276, respectively, so as to obtain the semiconductor device 10 shown in fig. 1. Alternatively, the semiconductor device 30 shown in fig. 2 may be manufactured by performing a deposition process only in the peripheral region 101, forming first insulating structures 372, 374, 376 having bottom surfaces located on different planes in the respective first openings 272, 274, 276, respectively, and simultaneously forming an insulating layer 378 covering the first insulating structures 372, 374, 376 and further connecting the respective first insulating structures 372, 374, 376. Although the process of forming the second insulating structure 380 is not specifically illustrated in the drawings of the present embodiment, it should be readily understood by those skilled in the art that the process of forming the first openings 272, 274, 276 may also be utilized in forming the second insulating structure 380. For example, a photolithography process (not shown) is also performed to form at least one second opening (not shown) by partially removing the conductive layer 160 and the second dielectric layer 152 in the peripheral region 101 by controlling etching time. The second opening is, for example, located between the connection segment 160a and the plug 161, and partially exposes the sidewall of the plug 161, so that, when the first insulating structures 372, 374, 376 are formed later, the second insulating structure 380 (as shown in fig. 2) with the bottommost surface between the top surface and the bottom surface of the second dielectric layer 152 can be formed in the second opening by the deposition process.

In addition, it should be understood by those skilled in the art that the method of manufacturing the semiconductor device of the present embodiment may have other operation modes and is not limited to the above. For example, in another embodiment, the first opening and/or the second opening may be formed by forming a plurality of openings with different pore sizes on a single mask layer (not shown), and performing an etching process through the single mask layer to form the first opening and/or the second opening with different depths at one time. Alternatively, in other embodiments, the photolithography process may be performed by exposing a plurality of hole patterns corresponding to the first holes and/or the second holes having different depths at a time by means of a half-tone (not shown). Alternatively, at least a portion of the first opening and/or the second opening, for example, the first opening and/or the second opening have a depth equal to or similar to that of the storage node pad 178, may be integrated with the manufacturing process of the insulating layer 180, so as to simplify the manufacturing method.

According to the foregoing manufacturing process, the manufacturing method of the semiconductor device in this embodiment is completed. In this operation, the semiconductor device 10 and/or the semiconductor device 30 of the present invention is provided with the first insulating structure 170/370 and/or the second insulating structure 380 penetrating the conductive layer 360 and the dielectric layer (including the first dielectric layer 150 and/or the second dielectric layer 152), and the conductive layer 160/360 is cut to form a plurality of connection segments 160a/360a, 360b and respectively serve as the conductive lines electrically connected to the source, drain or gate structures 131. Meanwhile, the electrical connection between the adjacent conductive or plug 161 and the adjacent connecting segment 360b is effectively isolated, so as to avoid the problems of derivative short circuit and the like. Thus, the first metal interconnection line disposed above the gate structure 131 in the semiconductor device 10 and/or the semiconductor device 30 of the present invention has a complete and reliable structure, so as to avoid the problems of short circuit between the first metal interconnection lines due to incomplete separation. Thus, the manufacturing process of the first metal interconnect line in the peripheral region 101 can be effectively integrated into the manufacturing process of the storage node pad 178 according to the manufacturing method of the semiconductor device in the present embodiment, so as to simplify the overall manufacturing process of the semiconductor devices 10 and 30. Meanwhile, the semiconductor devices 10, 30 manufactured by the manufacturing method of the present invention have an optimized structure and performance, and achieve more optimized operation performance.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device characterized by comprising:

a substrate;

a plurality of gate structures spaced apart on the substrate;

the first dielectric layer is arranged on the substrate and covers the grid structure;

the second dielectric layer is arranged on the substrate and covers the first dielectric layer;

the conducting layer is arranged on the substrate and is positioned on the second dielectric layer; and

the plurality of first insulating structures are arranged in the conducting layer and the second dielectric layer and penetrate through the bottom of the second dielectric layer.

2. The semiconductor device of claim 1, wherein a bottom most surface of at least one of the first insulating structures is between a top surface and a bottom surface of the first dielectric layer.

3. The semiconductor device of claim 1, wherein at least one of the first insulating structures further extends through the first dielectric layer on the gate structure.

4. The semiconductor device according to claim 1, further comprising:

and the gap wall covers the side surface and the top surface of the grid structure.

5. The semiconductor device of claim 4, wherein at least one of the insulating structures physically contacts a top surface of the spacer.

6. The semiconductor device of claim 4, wherein at least one of the first insulating structures extends through the spacer.

7. The semiconductor device of claim 1, wherein bottom-most surfaces of a plurality of the first insulating structures are on different planes.

8. The semiconductor device according to claim 1, further comprising:

a plurality of plugs respectively arranged at two opposite sides of each grid structure and in physical contact with the conductive layer; and

the connecting segments are respectively arranged between the plugs at two opposite sides of the grid structure and are alternately arranged with the first insulating structure, and each connecting segment comprises an arc-shaped top surface.

9. The semiconductor device according to claim 8, further comprising:

and the second insulating structure is arranged between one of the connecting segments and the plug, and the bottommost surface of the second insulating structure is positioned between the top surface and the bottom surface of the second dielectric layer.

10. The semiconductor device of claim 8, wherein the second insulating structure physically contacts the plug and the conductive layer.

11. A method of fabricating a semiconductor device, comprising:

providing a substrate;

forming a plurality of gate structures, which are arranged on the substrate in a separated manner;

forming a first dielectric layer on the substrate to cover the gate structure;

forming a second dielectric layer on the substrate and covering the first dielectric layer;

forming a conductive layer on the substrate and on the second dielectric layer; and

and forming a plurality of first insulating structures in the conductive layer and penetrating through the bottoms of the conductive layer and the second dielectric layer.

12. The method of claim 11, wherein forming a plurality of the first insulating structures within the conductive layer further comprises:

performing a photoetching process to form a plurality of first openings in the conductive layer;

the first insulating structure is formed in each of the first openings.

13. The method of claim 12, wherein during the photolithographic process, etching time is controlled such that the first opening penetrates the conductive layer and a portion of the second dielectric layer.

14. The method of manufacturing a semiconductor device according to claim 12, further comprising:

and forming a spacer on the gate structure to cover the side surface and the top surface of the gate structure.

15. The method of manufacturing a semiconductor device according to claim 14, further comprising:

in the photolithography process, the spacer is used as an etching barrier layer, so that the first opening vertically penetrates through the conductive layer, the second dielectric layer and part of the first dielectric layer to expose the spacer.

16. The method of manufacturing a semiconductor device according to claim 12, further comprising:

forming a plurality of plugs on opposite sides of each gate structure and physically contacting the conductive layer; and

and forming a plurality of connection segments which are respectively positioned between the plugs at two opposite sides of the grid structure and are alternately arranged with the first insulating structure, wherein each connection segment comprises an arc-shaped top surface.

17. The method of manufacturing a semiconductor device according to claim 16, further comprising:

forming a second opening between the connecting segment and the plug, the second opening exposing a sidewall of the plug; and

and forming a second insulating structure in the second opening, wherein the bottommost surface of the second insulating structure is positioned between the top surface and the bottom surface of the second dielectric layer.

18. The method of claim 17, wherein the second insulating structure physically contacts the conductive layer and the plug.

19. The method of claim 11, wherein bottom surfaces of the plurality of first insulating structures are on different planes.

20. The method of claim 11, wherein the at least one of the insulating structures physically contacts a top surface of the gate structure, and wherein a bottom-most surface of at least one other of the first insulating structures is between the top surface and the bottom surface of the first dielectric layer.