CN216354217U - Dynamic random access memory - Google Patents
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- CN216354217U CN216354217U CN202121956053.2U CN202121956053U CN216354217U CN 216354217 U CN216354217 U CN 216354217U CN 202121956053 U CN202121956053 U CN 202121956053U CN 216354217 U CN216354217 U CN 216354217U
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Abstract
The utility model provides a dynamic random access memory, comprising: the bit line structure comprises a substrate and a bit line structure positioned on the substrate, wherein the bit line structure sequentially comprises a metal silicide layer, a conductive layer and a hard mask layer from the substrate to the top. The dynamic random access memory provided by the utility model has the advantages that the metal silicide layer replacing the silicon layer is formed in the bit line structure, the bit line resistance is reduced, and the device efficiency is improved.
Description
Technical Field
The present invention relates to a memory, and more particularly, to a dynamic random access memory.
Background
A Dynamic Random Access Memory (DRAM), which belongs to a volatile memory, includes an array area (array area) composed of a plurality of memory cells (memory cells) and a peripheral area (peripheral area) composed of a control circuit. Each memory cell includes a transistor (transistor) electrically connected to a capacitor (capacitor), and the transistor controls the storage or release of charge in the capacitor for the purpose of storing data. The control circuit can be positioned to each memory cell to control the data access of the memory cell by a Word Line (WL) and a Bit Line (BL) which cross the array region and are electrically connected with the memory cells.
As generations evolve, the size of memory cells is gradually scaled to achieve higher packing density and storage capacity per unit area. However, the scaling of the memory device leads to an increase in the resistance of the lines of the memory device, which affects the performance.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to a dynamic random access memory device to reduce bit line resistance and improve device performance.
To achieve the above object, the present invention provides a dynamic random access memory, comprising:
the substrate comprises a plurality of active regions and an isolation structure surrounding the active regions;
and the bit line structure is positioned on the substrate, and the bit line structure sequentially comprises a metal silicide layer, a conductive layer and a hard mask layer from the substrate to the top.
Optionally, the metal silicide layer is in full contact with the bottom of the conductive layer.
Optionally, the dynamic random access memory further includes:
a dielectric layer between the bit line structure and the substrate; and
a plurality of recessed regions through the dielectric layer and exposing portions of the active regions and portions of the isolation structures, wherein the metal silicide layer is in direct contact with the active regions 120 within the recessed regions.
Optionally, a portion of the metal silicide layer is in direct contact with the isolation structure in the recessed region.
Optionally, the metal silicide layer includes a vertical extension portion extending downward into the substrate, and a recess depth of the vertical extension portion is greater than a recess depth of the recess region.
Optionally, the vertical extension is in direct contact with the isolation structure.
Optionally, the bit line structure further includes a sidewall spacer located on a sidewall of the bit line structure, wherein the metal silicide layer is covered by the sidewall spacer.
Optionally, the sidewall spacers include a first spacer, a second spacer and a third spacer, wherein,
the first spacing layer covers the side wall of the bit line structure and the inner wall of the recessed area;
the second spacer layer fills the recessed region;
the third spacer layer covers a portion of the sidewalls of the first spacer layer and contacts the top surface of the second spacer layer.
Optionally, the first spacer layer simultaneously contacts the active region, the isolation structure and the metal silicide layer.
Optionally, a top surface of the second spacer layer is lower than a top end of the metal silicide layer.
Optionally, the top of the third spacer layer is higher than the bottom of the hard mask layer.
In summary, the dram provided by the present invention includes the metal silicide layer in the bit line structure, thereby reducing the bit line resistance and improving the device performance.
Drawings
FIG. 1 is a flow chart of a method for fabricating a DRAM according to an embodiment of the present invention;
fig. 2A, fig. 2B, fig. 3A, fig. 3B, fig. 4, fig. 5 and fig. 6 are schematic structural diagrams corresponding to steps of a method for manufacturing a dynamic random access memory according to an embodiment of the present invention, wherein,
FIG. 2A is a simplified layout of a DRAM;
FIG. 2B is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 2A after forming a bit line stack layer;
FIG. 3A is a simplified layout of a DRAM after formation of a bit line structure;
FIG. 3B is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 3A after forming a bit line structure;
FIG. 4 is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 3A after a metal layer is formed;
FIG. 5 is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 3A after forming a metal silicide layer;
FIG. 6 is a schematic cross-sectional view of a DRAM formed with a sidewall spacer along the direction a-a' shown in FIG. 3A;
fig. 7, 8A, 8B, 9, 10, 11 and 12 are schematic structural diagrams corresponding to steps of a manufacturing method of a dynamic random access memory according to another embodiment of the present invention, wherein,
FIG. 7 is a cross-sectional view of a DRAM after forming a bit line stack;
FIG. 8A is a simplified layout of a DRAM after formation of a bit line structure;
FIG. 8B is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 8A after forming a bit line structure;
FIG. 9 is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 8A after forming a metal layer and an insulating layer;
FIG. 10 is a cross-sectional view of the DRAM along a-a' direction shown in FIG. 8A after forming a metal silicide layer;
FIG. 11 is a cross-sectional view of a DRAM after an over-etch process.
FIG. 12 is a schematic cross-sectional view of the DRAM along a-a' direction shown in FIG. 8A after forming a sidewall spacer;
fig. 13 is a schematic cross-sectional view of a dynamic random access memory according to yet another embodiment of the utility model.
Wherein the reference numerals are:
100. 200, 300-substrate; 110. 210, 310-isolation structures; 120. 220, 320-active area; 130. 230, 330-bit line architecture; 130 ', 230' -bit line stack layers;
101. 201, 301-dielectric layers; 102. 202-a metal layer; 203-an insulating layer; 231 a-horizontal extension;
131. 231-a silicon layer; 132. 232, 232-conductive layer; 133. 233, 333-hard mask layer;
134. 234, 334-metal silicide layer; 134a, 234 a-vertical extension; 140. 240, 340-recessed regions;
150. 250, 350-side wall spacing layer; 151. 251, 351-first spacer layer; 152. 252, 352-second spacer layer; 153. 253, 353-third spacer layer;
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 6 is a schematic diagram of a partial structure of the dynamic random access memory provided in this embodiment, and fig. 3A is a simplified layout of the dynamic random access memory in fig. 6, where fig. 6 is a schematic cross-sectional diagram of the dynamic random access memory structure in fig. 3A in a-a' direction. As shown in fig. 3A and fig. 6, the dynamic random access memory provided in this embodiment includes:
a substrate 100 including a plurality of active regions 120 and an isolation structure 110 surrounding the plurality of active regions 120;
a bit line structure 130 located on the substrate 100, wherein the bit line structure 130 sequentially includes a metal silicide layer 134, a conductive layer 132 and a hard mask layer 133 from the substrate 100 upward.
Specifically, the substrate 100 has a plurality of Active Areas (AA)120 and isolation structures 110 formed therein, the Active Areas (AA) extending along a first direction (direction D1), and the isolation structures 110 are, for example, trench isolation structures STI, which separate adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.
The substrate 100 further includes a plurality of word lines WL extending along a second direction (D2 direction) and intersecting with corresponding active regions AA, and the active regions AA include first and second source/drain doped regions respectively disposed at two sides of the word lines WL.
The substrate 100 has a plurality of bit line structures (BL)130 formed thereon and extending along a third direction (D3 direction) to pass through the corresponding active areas AA. Referring to fig. 3A, the bit line structure 130 includes a metal silicide layer 134, a conductive layer 132 and a hard mask layer 133 stacked in sequence. The material of the metal silicide layer 134 is, for example, cobalt silicide (CoSi)2) Titanium silicide (TiSi)2) Nickel silicide (NiSi)2) Molybdenum silicide (MoSi)2) Platinum silicide (PtSi)2) Aluminum silicide (AlSi2), tantalum silicide (TaSi)2) And tungsten silicide (WSi)2) And the like. The material of the conductive layer 132 includes, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co), and the material of the hard mask layer 133 includes, for example, at least one of silicon nitride (SiN) or silicon oxynitride (SiON).
In some embodiments, the dynamic random access memory further comprises a dielectric layer 101 and a plurality of recessed regions 140, the dielectric layer 101 being located between the bit line structure 130 and the substrate 100; the recess region 140 penetrates the dielectric layer 101 and exposes a portion of the active region 120 and a portion of the isolation structure 110, wherein the metal silicide layer 134 is in direct contact with the active region 120 in the recess region 140. Specifically, a dielectric layer 101 may be formed on the substrate 100, and then a patterning process is performed to etch the dielectric layer 101 and the substrate 100, so as to form a plurality of recessed regions 140 penetrating the dielectric layer 101 and recessed to a predetermined depth in the substrate 100. The recess region 140 overlaps the active region 120, revealing a middle portion of the active region 120 and the isolation structure 110 thereabout. The bit line structure 130 defines a recess region 140, i.e., a bit line node contact hole (DC), and the metal silicide layer 134 is received in the bit line node contact hole 121 as a bit line node contact plug, and the bit line resistance is reduced by forming the metal silicide layer 134 as a bit line node contact plug.
The dielectric layer 101 is formed of an insulating material, such as, but not limited to, silicon oxide (SiO)2) Silicon nitride SiN) or silicon oxynitride (SiON), which may comprise a single layer or a multi-layer structure. In some embodiments, the dielectric layer 101 comprises an oxide-nitride-oxide (ono) stack of a silicon oxide layer and a silicon nitride layer. The dielectric layer 101 and the substrate 100 may be patterned by using a known photolithography process and an etching process to define the recess region 140, which will not be described herein.
As shown in fig. 6, a portion of the metal silicide layer 134 is in direct contact with the active region 120 and the isolation structure 110. In some embodiments of the present invention, the metal silicide layer 134 includes a vertical extension 134a protruding downward into the substrate 100, and a recess depth of the vertical extension 134a is greater than a recess depth of the recess region 140. And the vertical extension 134a is in direct contact with the isolation structure 110.
Further, the dynamic random access memory provided in this embodiment further includes a sidewall spacer 150 located on the sidewall of the bit line structure 130, wherein the metal silicide layer 134 is covered by the sidewall spacer 150. The sidewall spacers 150 include a first spacer 151, a second spacer 152, and a third spacer 153, wherein the first spacer 151 covers sidewalls of the bit line structures 130 and inner walls of the recess regions 140; the second spacer 152 fills the recess region 140; the third spacer layer 153 covers a portion of the sidewalls of the first spacer layer 151 and contacts the top surface of the second spacer layer 152.
In the present embodiment, the first spacer layer 151 simultaneously contacts the active region 120, the isolation structure 110 and the metal silicide layer 134. The top surface of the second spacer 152 is lower than the top end of the metal silicide layer 134. The top of the third spacer layer 153 is higher than the bottom of the hard mask layer 133.
Accordingly, the present embodiment further provides a manufacturing method of a dynamic random access memory, and fig. 1 is a flowchart of the manufacturing method of the dynamic random access memory provided in the present embodiment. As shown in fig. 1, the method for manufacturing the dynamic random access memory includes:
step S01: providing a substrate 100 including a plurality of active regions 120 and an isolation structure 110 surrounding the plurality of active regions 120;
step S02: forming a bit line stack layer 130' on the substrate 100;
step S03: patterning the bit line stack layer 130' to form a bit line structure 130, wherein the bit line structure 130 sequentially comprises a silicon layer 131, a conductive layer 132 and a hard mask layer 133 from the substrate to the top; and the number of the first and second groups,
step S04: a silicidation reaction is performed to form a metal silicide layer 134 replacing the silicon layer 131.
The following describes the method for manufacturing the dynamic random access memory according to the present embodiment in detail with reference to fig. 2A to fig. 6.
Referring to fig. 2A and 2B, step S01 is performed to provide a substrate 100 including a plurality of active regions 120 and an isolation structure 110 surrounding the plurality of active regions 120. The substrate 100 is, for example, a silicon substrate (silicon substrate), a silicon containing substrate (silicon containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like. An isolation structure 110, such as a trench isolation structure STI, is formed in the substrate 100, and a plurality of Active Areas (AA)120 are defined by the isolation structure 110. The active areas AA are distributed in an array. The STI is formed by, for example, forming at least one isolation trench in the substrate 100 by etching, and then filling the isolation trench with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.
The substrate 100 further includes a plurality of word lines WL extending along a second direction (D2 direction) and intersecting with corresponding active regions AA, and the active regions AA include first and second source/drain doped regions respectively disposed at two sides of the word lines WL.
Next, as shown in fig. 2A and fig. 2B, step S02 is executed to form a bit line stack layer 130' on the substrate 100.
Specifically, first, a dielectric layer 101 is formed on the substrate 100, and then a patterning process is performed to etch the dielectric layer 101 and the substrate 100, so as to form a plurality of recessed regions 140 penetrating through the dielectric layer 101 and recessed to a predetermined depth in the substrate 100. The recess region 140 overlaps the active region 120, revealing a middle portion of the active region 120 and the isolation structure 110 thereabout.
After defining the recess region 140, i.e., the bit line node contact hole (DC), a bit line stack layer 130' is formed on the substrate 100. In some embodiments, the bit line stack layer 130' may include a silicon layer 131, a conductive layer 132 on the silicon layer 131, and a hard mask layer 133 on the conductive layer 132. The silicon layer 131 material may include, but is not limited to, polysilicon, amorphous silicon, or a silicon-containing compound. The silicon layer 131 fills the recess region 140 and directly contacts the middle portion of the active region 120 exposed by the recess region 140 and the adjacent isolation structure 110. The conductive layer 132 may include a metallic conductive material, such as aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum alloy (Ti-Al alloy), or other suitable metallic conductive material. The hard mask layer 133 comprises an insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable insulating material.
Next, referring to fig. 3A and 3B, step S03 is executed to pattern the bitline stack 130' to form a bitline structure (BL)130, wherein the bitline structure 130 includes a silicon layer 131, a conductive layer 132 and a hard mask layer 133 in sequence from the substrate 100. Specifically, the bit line stack layer 130 'is patterned to remove a portion of the bit line stack layer 130', so as to form the bit line structure BL. The bitline structures 130 extend along the first direction (D1 direction) and are arranged in parallel along the third direction (D3 direction), passing through the middle portion of each active region 120 (through each recessed region 140). The silicon layer 131 of the bit line structure 130 in the recess region 140 is in direct contact with the middle portion of the active region 120 exposed from the recess region 140, and the other portion of the silicon layer 131 is separated from the substrate 100 by the dielectric layer 101. In one embodiment, the widths of the hard mask layer 133, the conductive layer 132, and the upper portion of the silicon layer 131 may be substantially the same, such as the sidewalls of the conductive layer 132 and the sidewalls of the silicon layer 131 are aligned. In some other embodiments of the present invention, the widths of the hard mask layer 133 and the conductive layer 132 are the same, and the width of the upper portion of the silicon layer 131 is smaller than the width of the conductive layer 132, as shown in fig. 3B.
Next, referring to fig. 4 and 5, step S04 is performed to perform a silicidation reaction to form a metal silicide layer 134 instead of the silicon layer 131.
Specifically, referring to fig. 4, a metal layer 102 is globally formed on the substrate 100, covering the dielectric layer 101, the top surface and the sidewalls of the bit line structure 130, and the surface of the recess region 140 not covered by the bit line structure 130. Illustratively, the material of the metal layer 102 may include cobalt, titanium, tantalum, nickel, tungsten, molybdenum, aluminum, platinum, etc., or a combination thereof, but is not limited thereto.
Next, an annealing process is performed to react the metal layer 102 with the silicon layer 131 to form a metal silicide layer 134 replacing the silicon layer 131, and then the unreacted metal layer 102 is removed. According to some embodiments of the present invention, the material of the metal silicide layer 134 is, for example, cobalt silicide (CoSi) according to the material of the metal layer 102 selected2) Titanium silicide (TiSi)2) Nickel silicide (NiSi)2) Molybdenum silicide (MoSi)2) Platinum silicide (PtSi)2) Aluminum silicide (AlSi2), tantalum silicide (TaSi)2) And tungsten silicide (WSi)2) And the like, but is not limited thereto. After the silicidation reaction, the metal silicide layer 134 is formed from the silicon layer 131, and the width of the metal silicide layer 134 is increased compared to the silicon layer 131, for example, as shown in fig. 5, the width of the metal silicide layer 134 is the same as the width of the conductive layer 132.
In some embodiments, when the metal layer 102 in the recess region 140 directly contacts the active region 120 exposed from both sides of the bit line structure BL, the annealing process may also react the silicon of the metal layer 102 and the active region 120 to form a partial metal silicide on the active region 120 in the recess region 140, which may directly contact the isolation structure 110. Specifically, the metal silicide layer 134 includes a vertical extension 134a extending downward into the substrate 100, a recess depth of the vertical extension 134a is greater than a recess depth of the recess region 140, and the vertical extension 134a is in direct contact with the isolation structure 110.
Next, referring to fig. 6, the method for manufacturing a dynamic random access memory according to the present embodiment further includes forming a sidewall spacer 150 on the sidewall of the bit line structure 130, wherein the metal silicide layer 134 is covered by the sidewall spacer 150.
Specifically, the sidewall spacers 150 include a first spacer 151, a second spacer 152, and a third spacer 153, wherein the first spacer 151 covers sidewalls of the bit line structures 130 and inner walls of the recess regions 140; the second spacer 152 fills the recess region 140; the third spacer layer 153 covers a portion of the sidewalls of the first spacer layer 151 and contacts the top surface of the second spacer layer 152. In the present embodiment, the first spacer layer 151 simultaneously contacts the active region 120, the isolation structure 110 and the metal silicide layer 134. The top surface of the second spacer 152 is lower than the top end of the metal silicide layer 134. The top of the third spacer layer 153 is higher than the bottom of the hard mask layer 133.
The method for forming the sidewall spacers 150 may, for example, sequentially form a first spacer 151 and a second spacer 152, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or other insulating materials, and then perform an anisotropic etching process to remove a portion of the first spacer 151 and the second spacer 152, where the first spacer 151 and the second spacer 152 may fill the recess 140 and completely cover the exposed active region 120 and the exposed isolation structure 110. Subsequently, a third spacer 152, such as silicon oxide, is formed on the sidewall of the bit line structure BL to enhance the insulation between the bit line structure BL and the storage node contact plug formed subsequently.
Example two
As shown in fig. 12, the dynamic random access memory provided in this embodiment includes: a substrate 200 including a plurality of active regions 220 and an isolation structure 210 surrounding the plurality of active regions 220; a bit line structure 230 located on the substrate 200, wherein the bit line structure 230 sequentially includes a metal silicide layer 234, a conductive layer 232, and a hard mask layer 233 from the substrate 100. The difference from the first embodiment is that, in the present embodiment, the metal silicide layer 234 is not in direct contact with the isolation structure 210.
The following describes the method for manufacturing the dynamic random access memory according to this embodiment in detail with reference to fig. 7 to 12.
Referring to fig. 7, a substrate 200 is provided, which includes a plurality of active regions 220 and an isolation structure 210 surrounding the plurality of active regions 220. The substrate 200 is, for example, a silicon substrate (silicon substrate), a silicon-containing substrate (silicon-containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like. An isolation structure 210, such as a trench isolation structure STI, is formed in the substrate 200, and a plurality of Active Areas (AA)220 are defined by the isolation structure 110. The active areas AA are distributed in an array. The STI is formed by, for example, forming at least one isolation trench in the substrate 200 by etching, and then filling the isolation trench with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.
The substrate 200 further has a plurality of word lines WL formed therein, the word lines extending along a second direction (D2 direction) and intersecting with corresponding active regions AA, and the active regions AA have first and second source/drain doping regions formed therein, and the first and second source/drain doping regions are respectively disposed at both sides of the word lines WL.
Next, with continuing reference to fig. 7, a bit line stack 230' is formed over the substrate 200.
Specifically, first, a dielectric layer 201 is formed on the substrate 200, and then a patterning process is performed to etch the dielectric layer 201 and the substrate 200, so as to form a plurality of recessed regions 240 penetrating through the dielectric layer 201 and recessed to a predetermined depth in the substrate 200. The recess region 240 overlaps the active region 220, revealing a middle portion of the active region 220 and the nearby isolation structures 210.
After the recessed region 240 is defined, i.e., a bit line node contact hole (DC), a bit line stack layer 230' is formed on the substrate 200. In some embodiments, the bit line stack layer 230' may include a silicon layer 231, a conductive layer 232 on the silicon layer 231, and a hard mask layer 233 on the conductive layer 232. The silicon layer 231 material may include, but is not limited to, polysilicon, amorphous silicon, or a silicon-containing compound. The silicon layer 231 fills the recess region 240 and is in direct contact with the middle portion of the active region 220 exposed by the recess region 240 and the isolation structure 210 nearby. The conductive layer 232 may include a metal conductive material, such as aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum alloy (Ti-Al alloy), or other suitable metal conductive material. The hard mask layer 233 includes an insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable insulating material.
Next, referring to fig. 8A and 8B, the bit line stack layer 230' is patterned to form a bit line structure (BL) 230. The bit line structure 230 may further include a horizontal extension 231a of the silicon layer 231 covering the surface of the recess region 240 after the patterning process by adjusting the patterning process. Therefore, after the patterning process, the active region 220 and the isolation structure 210 are not exposed from the recess region 240. The widths of the hard mask layer 233, the conductive layer 232, and the upper portion of the silicon layer 231 may be substantially the same, as the sidewalls of the conductive layer 232 and the silicon layer 231 are aligned. In some other embodiments of the present invention, the widths of the hard mask layer 233 and the conductive layer 232 are the same, and the width of the upper portion of the silicon layer 231 is smaller than the width of the conductive layer 232, as shown in fig. 8B.
Next, referring to fig. 9, 10 and 11, a silicidation reaction is performed to form a metal silicide layer 134 instead of the silicon layer 131.
Specifically, referring to fig. 9, a metal layer 202 is globally formed on the substrate 200, covering the dielectric layer 201, the top surface and the sidewalls of the bit line structure 230, and the surface of the recess region 240 not covered by the bit line structure 230. Illustratively, the metal layer 202 material may include cobalt, titanium, tantalum, nickel, tungsten, molybdenum, aluminum, platinum, or the like, or a combination thereof, but is not limited thereto.
Next, an insulating layer 203 is formed on the metal layer 202. An insulating layer 203 may be deposited as a protective layer on the metal layer 202 using a chemical vapor deposition process or a physical vapor deposition process. The insulating layer 203 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or the like.
Next, an annealing process is performed to react the metal layer 202 with the silicon layer 231 to form a metal silicide layer 234 instead of the silicon layer 231, and then the unreacted metal layer 202 and the insulating layer 203 are removed, as shown in fig. 10. In this embodiment, the insulating layer 203 serves as a protection layer to protect the surface of the metal layer 202 from being oxidized in the subsequent process, and the problem of volume expansion caused by the silicidation reaction can be avoided to a certain extent. In addition, the insulating layer 203 does not participate in the reaction in the subsequent annealing process, and may be removed during the removal of the excess metal layer 202.
Next, referring to fig. 11, after removing the unreacted metal layer 202, an over-etching process is performed to remove the horizontal extension 231a, exposing the active region 220 and the isolation structure 210 in the recessed region 240. For example, an over-etching process may be performed by using the hard mask layer 233 and the dielectric layer 201 as an etching mask to remove the horizontal extension 231a after the silicidation until the active region 220 and the isolation structure 210 in the recessed region 240 are exposed. As shown in fig. 11, after the over-etching process, the metal silicide layer 234 does not directly contact the isolation structure 210.
In some embodiments, when the metal layer 202 in the recess region 240 directly contacts the active region 220 exposed from both sides of the bit line structure BL, the annealing process may also react the silicon of the metal layer 202 and the active region 220 to form a partial metal silicide on the active region 220 in the recess region 240, which may directly contact the isolation structure 210. Specifically, the metal silicide layer 234 includes a vertical extension 234a extending downward into the substrate 200, the recess depth of the vertical extension 234a is greater than the recess depth of the recess region 240, and the vertical extension 234a is not in direct contact with the isolation structure 210.
According to some embodiments of the present invention, the material of the metal silicide layer 234 is, for example, cobalt silicide (CoSi) according to the material of the metal layer 202 selected2) Titanium silicide (TiSi)2) Nickel silicide (NiSi)2) Molybdenum silicide (MoSi)2) Platinum silicide (PtSi)2) Aluminum silicide (AlSi2), tantalum silicide (TaSi)2) And tungsten silicide (WSi)2) And the like, but is not limited thereto. After the silicidation reaction, the metal silicide layer 234 is formed from the silicon layer 231, and the width of the metal silicide layer 234 is increased compared to the silicon layer 231, and illustratively, as shown in fig. 10 and 11, the width of the metal silicide layer 234 is the same as the width of the conductive layer 232.
Next, referring to fig. 11, the method for manufacturing a dynamic random access memory according to the present embodiment further includes forming a sidewall spacer 250 on the sidewall of the bit line structure 230, wherein the sidewall spacer 250 covers the metal silicide layer 234, and covers the active region 220 and the isolation structure 210 exposed from the recessed region 240, so as to provide electrical insulation between the bit line structure and a storage node contact (storage node contact) formed subsequently.
Specifically, the sidewall spacers 250 include a first spacer 251, a second spacer 252 and a third spacer 253, wherein the first spacer 251 covers sidewalls of the bit line structure 230 and inner walls of the recess region 140; the second spacer 152 fills the recess region 240; the third spacer layer 253 covers a portion of the sidewalls of the first spacer layer 251 and contacts the top surface of the second spacer layer 252. In the present embodiment, the first spacer layer 251 simultaneously contacts the active region 220, the isolation structure 210 and the metal silicide layer 234. The top surface of the second spacer layer 252 is lower than the top end of the metal silicide layer 234. The top of the third spacer layer 253 is higher than the bottom of the hard mask layer 233.
The method for forming the sidewall spacers 250 is, for example, sequentially forming a first spacer 251 and a second spacer 252, such as insulating materials, e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, etc., and then performing an anisotropic etching process to remove a portion of the first spacer 251 and the second spacer 252, wherein the first spacer 251 and the second spacer 252 fill the recess 140 and completely cover the exposed active region 220 and the exposed isolation structure 210. Subsequently, a third spacer 253, such as silicon oxide, is formed on the sidewall of the bit line structure BL to enhance the insulation between the bit line structure BL and the storage node contact plug formed subsequently.
EXAMPLE III
As shown in fig. 13, the dynamic random access memory provided in this embodiment includes: a substrate 300 including a plurality of active regions 320 and an isolation structure 310 surrounding the plurality of active regions 320; a bit line structure 330 located on the substrate 300, wherein the bit line structure 330 sequentially includes a metal silicide layer 334, a conductive layer 332, and a hard mask layer 333 from the substrate 300.
In this embodiment, the thickness of the metal silicide layer 334 is thicker than the thickness of the silicon layer for reacting with the metal layer, so that the metal silicide layer 334 is fully contacted with the bottom of the conductive layer 332, i.e. the metal silicide layer 334 may protrude from the sidewall of the conductive layer 234 and be misaligned with the sidewall of the conductive layer 332, and the two are slightly stepped.
The dynamic random access memory further comprises a dielectric layer 301 and a plurality of recessed regions 340, wherein the dielectric layer 301 is located between the bit line structure 330 and the substrate 300, the recessed regions 340 penetrate through the dielectric layer 301 and expose a portion of the active region 320 and a portion of the isolation structure 310, and the metal silicide layer 334 is in direct contact with the active region 320 in the recessed regions 340. The metal silicide layer 334 includes a vertical extension 334a extending downward into the substrate 300, and the recess depth of the vertical extension 334a is greater than the recess depth of the recess region 340. The vertical extension 334a is in direct contact with the isolation structure 310.
Further, the dynamic random access memory provided in this embodiment further includes a sidewall spacer 350 located on the sidewall of the bit line structure 330, wherein the metal silicide layer 334 is covered by the sidewall spacer 350. The sidewall spacers 350 include a first spacer 351, a second spacer 352 and a third spacer 353, wherein the first spacer 351 covers sidewalls of the bit line structure 330 and inner walls of the recess region 340; the second spacer 352 fills the recessed region 340; the third spacer 353 covers a portion of the sidewall of the first spacer 351 and contacts the top surface of the second spacer 352.
In this embodiment, the portions of the first spacer layer 351 and the third spacer layer 353 located on the sidewalls of the bit line structure 330 are stepped. The first spacers 351 simultaneously contact the active regions 320, the isolation structures 310, and the metal silicide layers 334. The top surface of the second spacer 352 is lower than the top end of the metal silicide layer 334. The top of the third spacer 353 is higher than the bottom of the hard mask layer 333.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the utility model without departing from the scope of the utility model. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the utility model as defined by the appended claims.
Claims (10)
1. A dynamic random access memory, comprising:
the substrate comprises a plurality of active regions and an isolation structure surrounding the active regions;
the bit line structure is positioned on the substrate, wherein the bit line structure sequentially comprises a metal silicide layer, a conducting layer and a hard mask layer from the substrate to the top, and the bottom of the conducting layer is completely contacted with the metal silicide layer.
2. The dynamic random access memory of claim 1, further comprising:
a dielectric layer between the bit line structure and the substrate; and
and a plurality of recess regions penetrating the dielectric layer and exposing a portion of the active region and a portion of the isolation structure, wherein the metal silicide layer is in direct contact with the active region in the recess regions.
3. The dynamic random access memory according to claim 2, wherein a portion of the metal silicide layer is in direct contact with the isolation structure in the recessed region.
4. The dynamic random access memory of claim 2, wherein the metal silicide layer comprises vertical extensions extending down into the substrate, the vertical extensions having a recess depth greater than a recess depth of the recess regions.
5. The dynamic random access memory of claim 4, wherein the vertical extension is in direct contact with the isolation structure.
6. The dynamic random access memory according to claim 2, further comprising a sidewall spacer on a sidewall of the bit line structure, wherein the metal silicide layer is covered by the sidewall spacer.
7. The dynamic random access memory of claim 6, wherein the sidewall spacers comprise a first spacer, a second spacer and a third spacer, wherein,
the first spacing layer covers the side wall of the bit line structure and the inner wall of the recessed area;
the second spacer layer fills the recessed region;
the third spacer layer covers a portion of the sidewalls of the first spacer layer and contacts the top surface of the second spacer layer.
8. The dynamic random access memory according to claim 7, wherein the first spacer layer simultaneously contacts the active region, the isolation structure and the metal silicide layer.
9. The dynamic random access memory according to claim 7, wherein a top surface of the second spacer layer is lower than a top end of the metal silicide layer.
10. The dynamic random access memory of claim 7, wherein the top of the third spacer layer is higher than the bottom of the hard mask layer.
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