CN214411198U

CN214411198U - Semiconductor device with a plurality of transistors

Info

Publication number: CN214411198U
Application number: CN202120968517.5U
Authority: CN
Inventors: 张钦福; 冯立伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2021-10-15
Anticipated expiration: 2031-05-08

Abstract

The utility model discloses a semiconductor device and forming method thereof, semiconductor device includes substrate, a plurality of gate structures, a plurality of isolation fins and an at least bit line. Gate structures disposed on the substrate, each gate structure being parallel to each other and extending along a first direction; isolation fins are disposed on the substrate, each isolation fin being parallel to one another and extending along a first direction on each gate structure, respectively. At least one bit line is disposed on the substrate and extends along a second direction perpendicular to the first direction, wherein the at least one bit line includes a plurality of pins extending along the direction perpendicular to the substrate, and each pin and each isolation fin are alternately arranged in the second direction.

Description

Semiconductor device with a plurality of transistors

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to semiconductor memory devices.

Background

Dynamic Random Access Memory (DRAM) is a volatile memory that is widely used as an important part in many electronic devices. Conventional dram devices are formed by aggregating a plurality of memory cells into an array for data storage. Each memory cell may be comprised of a Metal Oxide Semiconductor (MOS) transistor and a capacitor in series.

As the integration density is increased and the size of the dram device is reduced, the establishment of electrical connections between memory cells becomes more and more difficult. Meanwhile, the transistors and capacitors in each memory cell of a dram device have many different structural designs due to product requirements and cell density considerations. Therefore, how to improve the manufacturing process of the dynamic random access memory is still a hot research in the related field.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide a semiconductor device and a method of forming the same, wherein the semiconductor device includes a comb or gate bit line having pins that may or may not be selectively connected to transistors in order to provide better functionality and performance. In addition, the comb-shaped or gate-shaped bit lines of the semiconductor device may be formed through a dual damascene manufacturing process, and the manufacturing process of the semiconductor device is implemented through a fast and convenient process flow to save time and cost.

In order to achieve the above objects, one embodiment of the present invention provides a semiconductor device including a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, each of the gate structures being parallel to each other and extending along a first direction. The isolation fins are disposed on the substrate, each of the isolation fins being parallel to each other and extending along the first direction on each of the gate structures, respectively. The at least one bit line is disposed on the substrate and extends along a second direction perpendicular to the first direction, wherein the at least one bit line includes a plurality of pins extending along the direction perpendicular to the substrate, and each of the pins and each of the spacer fins are alternately arranged in the second direction.

In order to achieve the above object, one embodiment of the present invention provides another semiconductor device including a substrate, an insulating layer, and a plurality of gate structures. The insulating layer is arranged on the substrate, and the gate structure is arranged on the substrate, wherein the gate structure comprises a first gate structure arranged on the insulating layer and a second gate structure partially extending into the substrate.

The objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures.

Drawings

Fig. 1 and 2 show schematic views of a semiconductor device according to a preferred embodiment of the present invention, in which:

fig. 1 shows a top view of a semiconductor device; and

fig. 2 shows a cross-sectional view taken along the section line a-a' in fig. 1.

Fig. 3-12 show schematic diagrams of methods of forming semiconductor devices according to preferred embodiments of the present invention, wherein:

FIG. 3 illustrates a top view of the semiconductor device after forming an isolation layer;

FIG. 4 shows a cross-sectional view taken along section lines B-B ', C-C' in FIG. 3;

fig. 5 illustrates a top view of the semiconductor device after formation of the isolation fins;

FIG. 6 shows a cross-sectional view taken along section lines B-B ', C-C' in FIG. 5;

FIG. 7 illustrates a cross-sectional view of the semiconductor device after forming a first photoresist structure;

FIG. 8 illustrates a cross-sectional view of the semiconductor device after forming a second photoresist structure;

fig. 9 shows a top view of the semiconductor device after forming the opening;

FIG. 10 shows a cross-sectional view taken along section lines B-B ', C-C' in FIG. 9;

fig. 11 shows a cross-sectional view of the semiconductor device after forming spacers;

fig. 12 shows a cross-sectional view of the semiconductor device after forming a conductive layer; and

fig. 13 illustrates a cross-sectional view of the semiconductor device after forming a cap layer.

Wherein the reference numerals are as follows:

100-semiconductor device

110-substrate

111-active region

112-shallow trench isolation

120-gate structure

121-groove

122-interfacial dielectric layer

123-Gate dielectric layer

124-gate electrode layer

125-cap layer

130-insulating layer

140-isolation fin

141-part spacer fin

143-partial spacer fin

150-bit line

150 a-bit line contact

151-pin

152-semiconductor layer

153-Pin

154-Barrier layer

156-conductive layer

158-cap layer

160-isolation structure

170-spacer

171-spacer

173-spacer

173 a-bottommost surface

210-first photoresist Structure

211-sacrificial layer

213-antireflection layer

215-first photoresist layer

216-groove pattern

220-second photoresist structure

221-sacrificial layer

223-antireflection layer

225-second photoresist layer

226-via pattern

240-spacer fin

250-trench opening

250 a-via opening

260-isolating layer

H1-height

H2-height

D1-direction

D2-direction

D3-direction

Angle theta

Detailed Description

For a better understanding of the present invention, preferred embodiments will be described in detail hereinafter. The preferred embodiments of the present invention are illustrated by the numbered elements in the figures. Furthermore, technical features in different embodiments described hereinafter may be replaced with, recombined with or mixed with each other to constitute another embodiment without departing from the spirit of the present invention.

Fig. 1 and 2 show schematic diagrams of a semiconductor memory device 100 according to a preferred embodiment of the present invention, and fig. 1 and 2 show a top view and a cross-sectional view of the semiconductor device 100, respectively. In the present embodiment, the semiconductor device 100 is, for example, a dynamic random access memory device, and includes at least one transistor structure (not shown) and at least one capacitor structure (not shown) for receiving signals from Bit Lines (BLs) and Word Lines (WLs) during operation.

The semiconductor device 100 includes a substrate 110, such as a silicon substrate, an epitaxial silicon substrate, or a Silicon On Insulator (SOI) substrate, and at least one shallow trench isolation 112 disposed in the substrate 110 to define a plurality of Active Areas (AAs) 111 within the substrate 110. In an embodiment, the active regions 111 are parallel to each other to extend along the direction D1, and preferably, the direction D1 is not perpendicular to the y-direction (e.g., the direction D2) or the x-direction (e.g., the direction D3), for example, having an angle θ of about 30-120 degrees with the y-direction (e.g., the direction D2) or the x-direction (e.g., the direction D3), as shown in fig. 1, but not limited thereto.

A plurality of gate structures 120 are disposed within the substrate 110 as Buried Word Lines (BWLs) for receiving and transmitting signals of respective memory cells in the semiconductor device 100, wherein the gate structures 120 are parallel to each other and extend along the direction D2. In the present embodiment, the gate structure 120 is formed by, but not limited to, the following manufacturing process. First, a plurality of trenches 121 are formed in the substrate 110 in parallel with each other to extend in the direction D2, and an interfacial dielectric layer 122, a gate dielectric layer 123, a gate electrode layer 124, and a capping layer 125 are sequentially formed in each trench 121 to form each gate structure 120. As shown in fig. 2, the interfacial dielectric layer 122 completely covers the surface of each trench 121, followed by forming a gate dielectric layer 123 and a gate electrode layer 124 filled in the bottom of each trench 121, and forming a cap layer 125 filled in the top of each trench 121 on the gate dielectric layer 123 and the gate electrode layer 124. It is noted that the cap layer 125 has a topmost surface (not shown) that is flush with a topmost surface (not shown) of the substrate 110, such that each gate structure 120 may be embedded in the substrate 110.

Next, an insulating layer 130 is disposed on the top-most surface of the substrate 110, preferably comprising an oxide-nitride-oxide (ONO) structure, and a plurality of spacer fins 140 and a plurality of bitlines 150 are disposed on the insulating layer 130. Specifically, the spacer fins 140 are also parallel to each other and extend along the direction D2, each spacer fin 140 is aligned with each gate structure 120 disposed thereunder in the projection direction (not shown) of the substrate 110, and the bit lines 150 are parallel to each other and extend along the direction D3 to cross a portion of each spacer fin 140, as shown in fig. 1. In addition, referring to fig. 2 together, a portion of the isolation fin 141, i.e., the portion of the isolation fin 140 crossed by the bit line 150, has a relatively small height H1 in the projection direction, and a portion of the isolation fin 141 is disposed under the bit line 150 to overlap the bit line 150, so that the top surface of the portion of the isolation fin 141 can be directly covered by at least one bit line. On the other hand, another portion of the spacer fins 143 not crossed by the bit line 150 has a relatively large height H2 in the projection direction, and the other portion of the spacer fins 143 obviously does not overlap the bit line 150, as shown in fig. 1 and 2. It is further noted that each bit line 150 includes a plurality of pins (pins)151, 153 extending toward the substrate 110 along the projection direction, and each

151, 153 alternates with each spacer fin 140 along the direction D3. As shown in fig. 2, each pin 151 further extends into the substrate 110 to directly contact the substrate 110, the bottommost surface of each pin 151 being lower than the topmost surface of the substrate 110, while the pin 153 extends only over the substrate 110 and is disposed on the insulating layer 130, without directly contacting the substrate 110. Thus, the bottom of the pin 151 of the bit line 150 serves as a Bit Line Contact (BLCs) 150a disposed below the bit line 150 to electrically connect transistors (not shown) for receiving or transmitting signals. That is, the bit line contact 150a and the bit line 150 of the semiconductor device are integrally formed.

On the other hand, each bit line 150 further includes a semiconductor layer 152, a barrier layer 154, a conductive layer 156, and a cap layer 158, which are sequentially stacked from bottom to top. Preferably, the bit line 150 may be formed by a fabrication process similar to a metal gate replacement fabrication process, so the semiconductor layer 152 and the barrier layer 154 may respectively include a U-shaped structure, and the conductive layer 156 may fill the bottom of each bit line trench to connect the pin 151, the pin 153, as shown in fig. 2. The semiconductor layer 152 includes, for example, polysilicon or other suitable semiconductor material, the barrier layer 154 includes, for example, titanium or titanium nitride, the conductive layer 156 includes, for example, a low resistance metal such as tungsten (W), aluminum (Al), or copper (Cu), and the cap layer 158 includes, for example, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), but is not limited thereto.

In addition, the semiconductor device 100 further includes a plurality of isolation structures 160 and a plurality of spacers 170, wherein the spacers 170 are disposed on sidewalls of the bit lines 150 and sidewalls of the isolation fins 140, and the isolation structures 160 are disposed in remaining spaces between the isolation fins 140 and the bit lines 150 over the insulating layer 130. Specifically, the spacers 171 are disposed on the sidewalls of the bit lines 150 along the direction D3, and the spacers 173 are partially disposed on the sidewalls of the spacer fins 140 along the direction D2, as shown in fig. 1. Accordingly, a spacer 171 may be disposed between the isolation structure 160 and the bit line 150, and a spacer 173 may be disposed between a portion of the isolation fin 141 and the

leads

151, 153 of the bit line 150, such that a portion of the spacer 173 extends further into the substrate 110 through the leads 151 to obtain a bottom-most surface 173a that is also lower than the top-most surface of the substrate 110, as shown in fig. 2. In one embodiment, the

spacers

171 and 173 may respectively include a single-layer structure as shown in fig. 1 and 2, or a multi-layer structure, for example, having at least a first spacer layer (not shown) and a second spacer layer (not shown) stacked on the first spacer layer, but not limited thereto.

It should be noted that, as shown in fig. 1, the isolation structures 160 are disposed on two opposite sides of each bit line contact 150a in the direction D2, the isolation fins 140 are disposed on two opposite sides of each bit line contact 150a in the direction D3, and the topmost surfaces of the isolation structures 160 are substantially the same as the top surfaces of the other portion of the isolation fins 143 and are significantly higher than the top surfaces of the portion of the isolation fins 141 (shown with reference to fig. 2). Preferably, the isolation structures 160 and the isolation fins 140 may comprise dielectric materials with different etch selectivity ratios, such as silicon oxide, silicon nitride, and other suitable materials. In the present embodiment, the isolation fins 140 may comprise silicon nitride and the isolation structures 160 comprise oxidizable silicon, but are not limited thereto.

Thus, each bit line 150 in the semiconductor device 100 of the present embodiment may have a comb-like or gate-like structure, wherein the

pins

151 and 153 of the bit line 150 may be selectively in contact with or not in contact with the substrate 110, thereby providing better function and performance. It is noted that each pin 151 of each bit line 150 may serve as a bit line contact 150a, which may also be referred to as a bit line gate structure (bit line gate structure), for receiving or transmitting signals; each of the pins 153 of each of the bit lines 150 may be used as a dummy bit line gate structure (dummy bit line gate structure), wherein the bit line gate structure (i.e., the pin 151 extending into the substrate 110) and the dummy bit line gate structure (i.e., the pin 153 extending over the substrate) disposed on the substrate 110 respectively include a U-shaped semiconductor layer 152, a U-shaped barrier layer 154, and a conductive layer 156 stacked from bottom to top, the spacers 173/171 respectively surround the bit line gate structure (i.e., the pin 151) and the dummy bit line gate structure (i.e., the pin 153), and the bit line gate structure (i.e., the pin 151) and the dummy bit line gate structure (i.e., the pin 153) are separated from each other by a portion of the isolation fins 141. However, if the spacers 173/171 are disposed on the sidewalls of the bit line gate structure (i.e., the pin 151) and the dummy bit line gate structure (i.e., the pin 153), respectively, as seen in the cross-sectional view of fig. 2, the bit line gate structure (i.e., the pin 151) and the dummy bit line gate structure (i.e., the pin 153) are connected to each other through the conductive layer 156, and the connecting portion of the conductive layer 156 is disposed and directly covers a portion of the top surface of the isolation fin 141 for connecting the conductive layer 156 of the bit line gate structure (i.e., the pin 151) and the conductive layer 156 of the dummy bit line gate structure (i.e., the pin 153). In one embodiment, the connecting portion of the conductive layer 156 may span at least two of the spacer fins 141, as shown in fig. 2. Thus, the bit line 150 of the semiconductor device 100 can be quickly and conveniently formed through a simplified process flow, thereby saving time and cost.

To enable those skilled in the art to practice the present invention, the description further describes the method of forming the semiconductor device 100 of the present invention. Referring to fig. 3 to 13, fig. 3 to 13 respectively show the formation process of the semiconductor device 100 according to the preferred embodiment of the present invention, wherein fig. 3 and 5 are top views of the semiconductor device 100 during the formation process, fig. 4 and 6 are cross-sectional views along the lines B-B ', C-C' in fig. 3 and 5, and the other figures are cross-sectional views of the semiconductor device 100 during the formation process.

First, as shown in fig. 3 and 4, a substrate 110 is provided, wherein shallow trench isolations 112 and active regions 111 are formed within the substrate 110, and a gate structure 120 is formed in the substrate 110, an insulating layer 130 is formed on the substrate 110 such that a top surface of the gate structure 120 is flush with the topmost surface of the substrate 110, and such that the insulating layer 130 covers the active regions 111, the shallow trench isolations 112, and the gate structure 120. It is noted that the detailed features of the gate structure 120 and the formation thereof have been mentioned above, and thus are not described herein again. As shown in fig. 3 and 4, an isolation layer 260, for example, comprising a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, is formed entirely on the insulating layer 130 to cover all of the active region 111 and the shallow trench isolation 112 therebelow. In the present embodiment, the isolation layer 260 preferably includes silicon oxide, but is not limited thereto.

Next, as shown in fig. 5 and 6, a plurality of spacer fins 240 are formed within the spacer layer 260 to extend along the D2 direction. In one embodiment, the formation of the spacer fins 240 may be accomplished by the following steps. A portion of the isolation layer 260 is first removed to form a plurality of trenches (not shown) in the isolation layer 260, wherein each of the trenches is parallel to each other and extends along the direction D2 to partially expose the underlying insulating layer 130, and the trenches are filled with a dielectric material to form the isolation fins 240 having top surfaces flush with the isolation layer 260. Thus, the spacer fin 240 may achieve the same height as the spacer layer 260, such as height H2 shown in fig. 6. The dielectric material of the isolation fin 240 may be, but is not limited to, silicon oxide, silicon nitride, or silicon carbonitride. Preferably, the dielectric material of the isolation fin 240 may be a dielectric material having an etch selectivity with respect to the isolation layer 260, such as, but not limited to, silicon nitride and silicon dioxide.

In the following fabrication process, at least one bit line trench is formed, and then at least one bit line 150 is formed within the at least one bit line trench. As shown in fig. 7 to 10, at least one trench opening 250 and at least one via opening 250a are sequentially defined and formed to constitute the bit line trench. In one embodiment, the trench opening 250 and the via opening 250a may be formed by a dual damascene fabrication process, such as a trench first (trench first) dual damascene fabrication process. Specifically, a first photoresist structure 210 is formed on the substrate 110 to define a trench opening 250, wherein the first photoresist structure 210 includes a sacrificial layer 211 (e.g., an Organic Dielectric Layer (ODL)), an anti-reflective layer 213 (e.g., a dielectric anti-reflective coating (DARC)), and a first photoresist layer 215 stacked on top of each other, as shown in fig. 7, and at least one etching process (not shown) is performed to transfer a trench pattern 216 of the first photoresist layer 215 into the underlying anti-reflective layer 213, sacrificial layer 211, isolation layer 260, and isolation fin 240 to form the trench opening 250. Meanwhile, after the etching process, the isolation layer 260 remains to form the isolation structure 160, as shown in fig. 8. In addition, the etching process is performed by using the insulating layer 130 as an etching stop layer, so that a portion of the insulating layer 130 can be exposed from the trench opening 250, as shown in fig. 8 and 10. On the other hand, due to the etch selectivity between the material of the isolation layer 260 and the isolation fins 240, the isolation fins 240 exposed from the trench pattern 216 may be partially etched instead of being completely etched, thereby obtaining the isolation fins 141 having portions with a reduced height H1 compared to the height H2 of the remaining portions of the isolation fins 143.

After forming the trench opening 250, the first photoresist structure 210 is completely removed, and then the second photoresist structure 220 is formed to define a via opening 250 a. As shown in fig. 8, the second photoresist structure 220 includes a sacrificial layer 221 (e.g., an organic dielectric layer), an anti-reflective layer 223 (e.g., a dielectric anti-reflective coating), and a second photoresist layer 225 stacked on each other, the sacrificial layer 221 fills the trench opening 250 to obtain a flat top surface, and then another etching process is performed to transfer the via pattern 226 of the second photoresist layer 225 into the anti-reflective layer 223, the sacrificial layer 221, the insulating layer 130, and a portion of the substrate 110, as shown in fig. 9 and 10. Note that the via opening 250a extends further into the substrate 100 to expose the substrate 110. It should also be understood by those skilled in the art that in another embodiment, the aforementioned via openings 250a and trench openings 250 may also be selected by a via first (via first) dual damascene process (not shown), and furthermore, although only a single trench opening 250 and a single via opening 250a are shown in fig. 7 to 9, the actual number of trench openings 250 and via openings 250a is not limited thereto and may be adjusted according to the actual device requirements. For example, when viewed from a top view as shown in fig. 8, a plurality of trench openings 250 and a plurality of via openings 250a may be formed to make up a plurality of the bitline trenches, and the actual number of the bitline trenches may also be adjusted according to the desired number of bitlines 150 in the device.

Next, as shown in fig. 11, spacers 170 are formed on the sidewalls of the bit line trenches (i.e., the sidewalls of the trench openings 250 and the via openings 250 a), and the spacers 170 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable material. In an embodiment, the spacer 170 may include a single layer structure, and its formation may be, but is not limited to, by the following steps. A layer of dielectric material (not shown) is first deposited over the substrate 110 covering all exposed surfaces thereof and an etch-back process is performed to remove the layer of dielectric material disposed on horizontal surfaces, leaving

spacers

171, 173 between the bit line trenches and the isolation fins 140 or between the bit line trenches and the isolation structures 160. However, in another embodiment, the spacer may also include a multi-layer structure, and its formation may be accomplished by steps similar to those above. Note that the spacer 171 disposed on the sidewall of the via trench 250 is formed on the insulating layer 130 without directly contacting the substrate 110, and the spacer 173 disposed on the sidewall of the via opening 250a may further extend into the substrate 110 to directly contact the substrate 110, wherein the spacer 173 has a bottom-most surface 173a lower than the top-most surface of the substrate 110.

Finally, as shown in fig. 12 and 13, at least one bit line 150 is formed to fill the bit line trench, for example, by a fabrication process similar to a metal gate replacement fabrication process. Specifically, the bit line 150 is formed by the following steps: a semiconductor material layer (not shown) and a barrier material layer (not shown) are sequentially and conformally formed on the substrate 110, an etch-back process is performed to remove the semiconductor material layer and the barrier material layer, thereby forming a U-shaped semiconductor layer 152 and a barrier layer 154 as shown in fig. 12 on the surfaces of the trench opening 250 and the via opening 250a, and then a conductive layer 156 is filled at the bottom of each of the bit line trenches. However, it should be understood by those skilled in the art that, in another embodiment, the etch-back process of the semiconductor material layer and the barrier material layer may be omitted so as to form a conformal and continuous semiconductor layer (not shown) and barrier layer (not shown) on the substrate 110. Note that the semiconductor layer 152, barrier layer 154, and conductive layer 156 filled in the via opening 250a form a pin 151 of each bit line 150 to directly contact the substrate 110, and the semiconductor layer 152, barrier layer 154, and conductive layer 156 filled in the trench opening 250 form a pin 153 of each bit line 150 without directly contacting the substrate 110, wherein each pin 151, pin 153 are connected to each other through the conductive layer 156, as shown in fig. 12. Subsequently, a capping layer 158 is formed to fill the top of each of the bit line trenches to constitute each bit line 150. Therefore, in the cross-sectional view of fig. 13, the bit line 150 may have a comb-like structure or a gate-like structure, wherein the

pins

151 and 153 may selectively extend into the substrate 110 to electrically connect the substrate 110, and the pin 151 is disposed between two adjacent pins 153, but is not limited thereto.

Thereby, a semiconductor device 100 of a preferred embodiment of the present invention can be obtained, which has at least one bit line 150 that can be a comb-like structure or a gate-like structure to achieve better function and performance. In the foregoing formation method, comb-shaped bit lines or gate-shaped bit lines may be formed by a dual damascene fabrication process, a trench opening 250 and a via opening 250a are sequentially formed in the isolation layer 260 to constitute the bit line trench, and then each bit line 150 is formed in the bit line trench. With this arrangement, the comb-shaped or gate-shaped bit line may have a pin 151 directly contacting the substrate 110 and a pin 153 not contacting the substrate 110, wherein the

pins

151 and 153 are connected to each other through the conductive layer 156, and the connection portion of the conductive layer 156 is directly disposed on a portion of the isolation fin 141 to overlap a portion of the isolation fin 141. In addition, the bit line 150 of the semiconductor memory device 100 overlaps a portion of the isolation fin 141, and the portion of the isolation fin 141 separates each of the

legs

151 and 153 of the bit line 150. Therefore, the semiconductor device 100 of the present embodiment can be formed by a simplified process flow to save time and cost.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of gate structures disposed in the substrate, the gate structures being parallel to each other and extending along a first direction;

a plurality of isolation fins disposed on the substrate, the isolation fins being parallel to each other and extending along the first direction on the gate structures, respectively; and

at least one bit line is disposed on the substrate and extends along a second direction perpendicular to the first direction, wherein the at least one bit line includes a plurality of pins extending along the direction perpendicular to the substrate, and each of the pins and each of the spacer fins are alternately arranged in the second direction.

2. The semiconductor device of claim 1, wherein the leads comprise a plurality of first leads that do not directly contact the substrate and a plurality of second leads that directly contact the substrate.

3. The semiconductor device according to claim 2, wherein each of the second leads is disposed between two adjacent ones of the first leads.

4. The semiconductor device of claim 1, wherein a portion of a top surface of the isolation fin is covered by the at least one bit line.

5. The semiconductor device of claim 1, further comprising:

a first spacer disposed on a sidewall of the at least one bit line; and

a second spacer disposed on a sidewall of the isolation fin, wherein a portion of the second spacer is disposed within a substrate and a bottom-most surface of the portion of the second spacer is lower than a top surface of the substrate.

6. The semiconductor device of claim 1, wherein the at least one bit line comprises a bottom-up stack of a semiconductor layer, a barrier layer, and a conductive layer, and wherein the semiconductor layer and the barrier layer comprise a U-shaped structure.

7. The semiconductor device of claim 6, wherein the at least one bitline further comprises a cap layer disposed over the semiconductor layer, the barrier layer, and the conductive layer.

8. A semiconductor device, comprising:

a substrate;

an insulating layer disposed on the substrate; and

a plurality of gate structures disposed on the substrate, the gate structures comprising:

the first gate structure is arranged on the insulating layer; and

the second gate structure extends partially into the substrate.

9. The semiconductor device of claim 8, wherein each of the gate structures comprises a semiconductor layer, a barrier layer and a conductive layer stacked from bottom to top, and the conductive layer of the first gate structure and the conductive layer of the second gate structure are connected to each other.

10. The semiconductor device according to claim 9, wherein the semiconductor layer and the barrier layer of the first gate structure and the second gate structure each have a U-shaped structure.

11. The semiconductor device according to claim 9, further comprising:

an isolation fin is disposed on the insulating layer between the first gate structure and the second gate structure.

12. The semiconductor device of claim 11, wherein the connecting portion of the conductive layer is disposed over the spacer fins and spans at least two of the spacer fins.

13. The semiconductor device according to claim 8, further comprising:

a first spacer disposed on a sidewall of the first gate structure; and

and the second gap wall is arranged on the side wall of the second gate structure, wherein the second gap wall part extends into the substrate.

14. The semiconductor device of claim 8, wherein a bottom-most surface of the second gate structure is lower than a top-most surface of the substrate.