CN105374820A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN105374820A CN105374820A CN201410424367.6A CN201410424367A CN105374820A CN 105374820 A CN105374820 A CN 105374820A CN 201410424367 A CN201410424367 A CN 201410424367A CN 105374820 A CN105374820 A CN 105374820A
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- substrate
- semiconductor structure
- polysilicon
- contact
- contact window
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Abstract
The present invention discloses a semiconductor structure which reduces contact resistance. The semiconductor structure at least comprises a substrate, buried word lines, isolation layers, polysilicon spacer walls and contact window plugs. The substrate has a plurality of channels. The buried word lines are in the channels, and the top surfaces of the buried word lines are lower than the surface of the substrate for a first distance. The isolation layers are on the buried word lines and the top surfaces of the isolation layers are lower than the surface of the substrate for a second distance. The polysilicon spacer walls are at the side walls of the channels on the isolation layers to be in direct contact with the substrate. The contact area of contact window plugs and the substrate can be increased through the polysilicon spacer walls, and thus the resistance between the substrate and the contact window plugs is reduced. According to the semiconductor structure, the contact area between the substrate and the contact window plugs can be increased, and thus the contact resistance between the substrate and the contact window plugs can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor structure, and in particular to a kind of semiconductor structure reducing contact resistance.
Background technology
Dynamic random access memory is after developing into the nanometer generation along with element, the difficulty faced is more and more many, such as along with contact area reduction, element current also diminishes gradually.Especially when the position of capacitor contact window slightly offsets, and when reducing the contact area with element active area (AA), problem will worsen more.
The mode of current improvement adopts line style contact structure; Namely capacitor contact window is changed employing linear structure, increase contact area.But, just need extra storage node structure to connect line style contact structure thus, and because during making line style contact structure, need to remove more electric conducting material when chemico-mechanical polishing (CMP) manufacturing process, so easily cause damage to peripheral cell.
Summary of the invention
The invention provides a kind of semiconductor structure, the resistance between substrate and contact window plug can be reduced, and the problem avoiding line style contact structure to cause occurs.
Semiconductor structure of the present invention at least comprises the substrate with several raceway groove, the embedded type word line being positioned at raceway groove, the separator be positioned on embedded type word line, polysilicon clearance wall and contact window plug, wherein has substrate to expose between above-mentioned raceway groove.The end face of embedded type word line lower than surface one first distance of substrate, the end face of separator lower than surface one second distance of substrate.The sidewall of the polysilicon clearance wall then raceway groove of position on separator, directly to contact with substrate.Contact window plug position is also connected with electrical property of substrate with polysilicon clearance wall respectively on substrate.
In one embodiment of this invention, above-mentioned contact window plug comprises capacitor contact window connector.
In one embodiment of this invention, above-mentioned second distance is less than the thickness of described separator.
In one embodiment of this invention, the thickness of each polysilicon clearance wall above-mentioned is between 5nm ~ 15nm.
In one embodiment of this invention, above-mentioned semiconductor structure also can comprise the insulating barrier between substrate and embedded type word line.
In one embodiment of this invention, above-mentioned semiconductor structure also can comprise the metal silicide layer on the surface being positioned at polysilicon clearance wall, and directly contacts with contact window plug.Described metal silicide layer comprises silicon cobalt substrate, nickel silicide layer or titanium silicide layer.
In one embodiment of this invention, above-mentioned semiconductor structure also can comprise position on substrate and across the bit line of embedded type word line.
In one embodiment of this invention, above-mentioned semiconductor structure also can comprise the metal silicide layer on the surface being positioned at bit line, and wherein said metal silicide layer comprises silicon cobalt substrate, nickel silicide layer or titanium silicide layer.
Based on above-mentioned, structure of the present invention, by polysilicon clearance wall (with metal silicide layer), increases the contact area of contact window plug and substrate, so can reduce the resistance between substrate and contact window plug, maintains the magnitude of current of array element.In addition, the present invention uses pass contact hole, so can not face the problem of current line style contact hole.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is the generalized section of a kind of semiconductor structure according to the first embodiment of the present invention.
Figure 1B is the generalized section of a kind of semiconductor structure according to the second embodiment of the present invention.
Fig. 2 A to Fig. 2 E is the manufacturing process profile of a kind of semiconductor structure according to the third embodiment of the present invention.
Fig. 3 A to Fig. 3 C is the manufacturing process profile of a kind of semiconductor structure according to the fourth embodiment of the present invention.
Fig. 4 A is the schematic top plan view of the semiconductor structure of Fig. 3 A.
Fig. 4 B is the schematic top plan view of the semiconductor structure of Fig. 3 C.
Wherein, description of reference numerals is as follows:
100,200: substrate
100a, 200a, 220a: surface
102,216: embedded type word line
102a, 104a, 218a: end face
104,218: separator
106,220: polysilicon clearance wall
108,226,310: contact window plug
110,208: raceway groove
112,230: region
114,212: barrier layer
116,222,306: dielectric layer
118: insulating barrier
120,206a: hard mask
122,202: trench isolation structures
124,304: metal silicide layer
204: high-density plasma oxide layer
206b: polysilicon mask
210: silicon oxide layer
214,300: metal level
224,308: contact window opening
302: silicon nitride cap layer
400: bit line
CA: contact area
D1: the first distance
D2: second distance
T1, t2: thickness
Embodiment
Figure 1A is the generalized section of a kind of semiconductor structure according to the first embodiment of the present invention.
Please refer to Figure 1A, the semiconductor structure of the present embodiment at least comprises substrate 100, embedded type word line 102, the separator 104 be positioned on embedded type word line 102, polysilicon clearance wall 106 and contact window plug 108, and described separator 104 is such as SiN.In substrate 100, have multiple raceway groove 110, and come out in the region 112 between raceway groove 110.Embedded type word line 102 be position in raceway groove 110, and its end face 102a lower than the surperficial 100a first of substrate 100 apart from d1, between 80nm ~ 100nm.In addition, one deck barrier layer 114 can be established between embedded type word line 102 and raceway groove 110, as Ti/TiN.The same position of separator 104 is in raceway groove 110, and the end face 104a of separator 104 is lower than the surperficial 100a second distance d2 of substrate 100, between 30nm ~ 40nm.In one embodiment, second distance d2 is less than the thickness t1 of separator 104, but the present invention is not limited to this.As for the sidewall that polysilicon clearance wall 106 is position raceway grooves 110 on separator 104, directly to contact with contact window plug 108.In another embodiment, the thickness t2 of polysilicon clearance wall 106 is such as about between 5nm ~ 15nm, but the present invention is not limited to this.Contact window plug 108 is electrical connected with the region 112 of polysilicon clearance wall 106 with substrate on the substrate 100 and respectively, and contact window plug 108 is generally that position is in dielectric layer 116.In addition, between substrate 100 and each embedded type word line 102, insulating barrier 118 can be set, to reduce the interference between embedded type word line 102.And substrate 100 between raceway groove 110 can be provided with hard mask 120, it is etching mask (mask) used when making raceway groove 110, can remain the part as semiconductor structure, but the present invention is not limited to this; That is, the hard mask 120 of this layer also can remove after formation polysilicon clearance wall 106.And hard mask 120 is such as SiN layer.
In figure ia, there is a trench isolation structures 122 wherein between two embedded type word lines 102, become at least two active areas to separate substrate 100, but the present invention is not limited to this; In other words, other isolation structures can be set or not establish isolation structure in substrate 100.
In one embodiment, if above-mentioned semiconductor structure is applied to dynamic random access memory, then contact window plug 108 can be capacitor contact window connector.
Figure 1B is the generalized section of a kind of semiconductor structure according to the second embodiment of the present invention, wherein uses the component symbol identical with the first embodiment to represent same or analogous component.
Please refer to Figure 1B, semiconductor structure in the present embodiment is except substrate 100, embedded type word line 102, separator 104, polysilicon clearance wall 106 and contact window plug 108, also have one deck to be positioned at the metal silicide layer 124 of the surperficial 106a of polysilicon clearance wall 106, and directly contact with contact window plug 108.Wherein, metal silicide layer 124 is silicon cobalt substrate, nickel silicide layer or titanium silicide layer such as, can reduce the contact resistance (contactresistance) between the region 112 of substrate and contact window plug 108 further.
About the making of structure of the present invention, can refer to following manufacturing process, but the present invention is not limited to this.
Fig. 2 A to Fig. 2 E is the manufacturing process profile of a kind of semiconductor structure according to the third embodiment of the present invention.
Please also refer to Fig. 2 A, in a substrate 200, first produce the trench isolation structures 202 of definition active area, and one deck high-density plasma oxide layer 204 can be set in trench isolation structures 202.Then, utilize hard mask 206a and the polysilicon mask 206b on it as etching mask, in substrate 200, etch multiple raceway groove 208.Above-mentioned hard mask 206a is such as SiN layer.Then, the manufacturing process as steam generation technology (ISSG) and so on of coming personally can be utilized to form silicon oxide layer 210 on raceway groove 208 surface, simultaneously also can at polysilicon mask 206b surface formation silicon oxide layer 210.
Then, please refer to Fig. 2 B, sequentially in raceway groove 208, form barrier layer 212 and metal level 214, wherein barrier layer 212 for example Ti/TiN, metal level 214 for example tungsten (W).Then, above-mentioned barrier layer 212 and metal level 214 is eat-back, to obtain embedded type word line 216.
Afterwards, please refer to Fig. 2 C, utilize (ALD) technology layer deposited isolating 218 in raceway groove 208 as long-pending in atomic layer Shen, again using the polysilicon mask 206b of Fig. 2 B as etching mask, etch-back separator 218, until its end face 218a is lower than the surperficial 200a (scope of such as 30nm ~ 40nm) of substrate 200, described separator 218 is such as SiN.Then, the polysilicon mask 206b of Fig. 2 B is removed, recycle as wet dip (wetdip) mode removes the silicon oxide layer 210 that separator more than 218 exposes.
Then, please refer to Fig. 2 D, deposition one deck polysilicon layer (not illustrating), its thickness can be controlled in the diameter D of raceway groove 208 1/10 ~ 1/3 between (scope of such as 5nm ~ 15nm), in order to follow-up formation clearance wall.Then, the manufacturing process as reactive ion etching (RIE) is carried out to polysilicon layer, form polysilicon clearance wall 220 with raceway groove 208 sidewall on separator 218.
Then, please refer to Fig. 2 E, after Subsequent semiconductor manufacturing process (as made grid or bit line etc.), dielectric layer 222 on substrate 200, then form the contact window opening 224 through the hard mask 206a of dielectric layer 222 and part.Subsequently, in contact window opening 224, contact window plug 226 is formed, directly to contact in polysilicon clearance wall 220 and substrate 200.Because the existence of polysilicon clearance wall 220, contact window plug 226 will increase the area of polysilicon clearance wall 220 with the contact area of substrate 200, therefore can reduce contact resistance therebetween.
Fig. 3 A to Fig. 3 C is the manufacturing process profile of a kind of semiconductor structure according to the fourth embodiment of the present invention, and the present embodiment is the upper Fig. 2 D that continues, so partial component is identical with the 3rd embodiment.
Please refer to Fig. 3 A, after formation polysilicon clearance wall 220, first can carry out the bit line 400 of making as Fig. 4 A of other semiconductor structures, comprehensively depositing metal layers 300 on substrate 200 again, and on metal level 300 deposited silicon nitride cap layer (caplayer) 302, wherein above-mentioned metal level 300 such as cobalt layers, nickel dam or titanium layer.
Then, please refer to Fig. 3 B, carry out first time rapid thermal treatment (RTP) manufacturing process, form metal silicide layer 304 (as CoSix, NiSix, TiSix etc.) with the surperficial 220a in polysilicon clearance wall 220, and now bit line (400 of Fig. 4 A and Fig. 4 B) surface also can form metal silicide layer.Afterwards, silicon nitride cap layer 302 and remaining metal level 300 are removed completely.
Then, please refer to Fig. 3 C, second time rapid thermal treatment (RTP) manufacturing process can be carried out, to reduce resistance.Then, dielectric layer 306 on substrate 200, form the contact window opening 308 through the hard mask 206a of dielectric layer 306 and part again, then in contact window opening 308, form contact window plug 310, directly to contact in metal silicide layer 304, polysilicon clearance wall 220 and substrate 200.As with Fig. 4 B overlooked, contact window plug 310 by polysilicon clearance wall 220, and increases the contact area CA between substrate 200.
In sum, the present invention, by polysilicon clearance wall, increases the contact area between substrate and contact window plug, and reduces contact resistance between the two by this.Therefore, when the present invention is applied to the device as dynamic random access memory, storage node structure needn't be made in addition and come connection substrate and line style contact structure, and the more CMP manufacturing process needed for line style contact structure can be avoided to separate line style contact structure to become in the process of each independent contact window, to the hurtful possibility of peripheral cell.In addition, the present invention also can form the metal silicide layer that can reduce resistance at above-mentioned polysilicon gap wall surface.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appending claims person of defining.
Claims (10)
1. a semiconductor structure, comprising:
One substrate, has most raceway grooves;
A most embedded type word line, position is in the described raceway groove of described substrate, and the end face of described embedded type word line is lower than surface one first distance of described substrate;
A most separator, lay respectively in the described raceway groove on described embedded type word line, and the end face of described separator is lower than surface one second distance of described substrate;
A most polysilicon clearance wall, the sidewall of the described raceway groove of position on described separator, directly to contact with described substrate; And
Most contact window plugs, position on the substrate and be connected with described electrical property of substrate with described polysilicon clearance wall respectively.
2. semiconductor structure as claimed in claim 1, wherein said contact window plug comprises capacitor contact window connector.
3. semiconductor structure as claimed in claim 1, wherein said second distance is less than the thickness of described separator.
4. semiconductor structure as claimed in claim 1, wherein the thickness of polysilicon clearance wall described in each is between 5nm ~ 15nm.
5. semiconductor structure as claimed in claim 1, also comprises an insulating barrier, at described substrate and described in each between embedded type word line.
6. semiconductor structure as claimed in claim 1, also comprises most metal silicide layers, lays respectively at the surface of described polysilicon clearance wall, and directly contact with described contact window plug.
7. semiconductor structure as claimed in claim 6, wherein said metal silicide layer comprises silicon cobalt substrate, nickel silicide layer or titanium silicide layer.
8. semiconductor structure as claimed in claim 1, also comprises most bit lines, and position is on the substrate and across described embedded type word line.
9. semiconductor structure as claimed in claim 8, also comprises most metal silicide layers, lays respectively at the surface of described bit line.
10. semiconductor structure as claimed in claim 9, wherein said metal silicide layer comprises silicon cobalt substrate, nickel silicide layer or titanium silicide layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410424367.6A CN105374820B (en) | 2014-08-26 | 2014-08-26 | Semiconductor structure |
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|---|---|---|---|
| CN201410424367.6A CN105374820B (en) | 2014-08-26 | 2014-08-26 | Semiconductor structure |
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| CN105374820A true CN105374820A (en) | 2016-03-02 |
| CN105374820B CN105374820B (en) | 2018-07-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346666A (en) * | 2017-01-23 | 2018-07-31 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| CN113437070A (en) * | 2021-07-09 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
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| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN103178019A (en) * | 2011-12-20 | 2013-06-26 | 华邦电子股份有限公司 | Method for manufacturing word lines of embedded flash memory |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
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2014
- 2014-08-26 CN CN201410424367.6A patent/CN105374820B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN103178019A (en) * | 2011-12-20 | 2013-06-26 | 华邦电子股份有限公司 | Method for manufacturing word lines of embedded flash memory |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346666A (en) * | 2017-01-23 | 2018-07-31 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| US11502180B2 (en) | 2017-01-23 | 2022-11-15 | United Microelectronics Corp. | Semiconductor device and method of forming the same |
| CN113437070A (en) * | 2021-07-09 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
| CN113437070B (en) * | 2021-07-09 | 2023-05-23 | 福建省晋华集成电路有限公司 | Semiconductor device and method for forming the same |
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| CN105374820B (en) | 2018-07-17 |
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