CN105374820B - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN105374820B CN105374820B CN201410424367.6A CN201410424367A CN105374820B CN 105374820 B CN105374820 B CN 105374820B CN 201410424367 A CN201410424367 A CN 201410424367A CN 105374820 B CN105374820 B CN 105374820B
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Abstract
The invention discloses a kind of semiconductor structures reducing contact resistance, include at least substrate, embedded type word line, separation layer, polysilicon clearance wall and contact window plug.There are several raceway grooves in substrate.Embedded type word line is then located in raceway groove, and wherein the top surface of embedded type word line is less than one first distance of surface of substrate.Separation layer is located at one second distance of surface that on embedded type word line and its top surface is less than substrate.The side wall of polysilicon clearance wall then raceway groove of the position on separation layer, to be in direct contact with substrate.Contact window plug can increase the contact area with substrate by above-mentioned polysilicon clearance wall, and then reduce the resistance value between substrate and contact window plug.The present invention can increase the contact area between substrate and contact window plug, and thereby reduce contact resistance between the two.
Description
Technical field
The present invention relates to a kind of semiconductor structures, and more particularly to a kind of semiconductor structure reducing contact resistance.
Background technology
Dynamic random access memory with element after developing to the nanometer generation, difficult more and more, the example that faces
Such as contact area reduces, element current also tapers into.Especially when the position of capacitor contact window is slightly offset, and subtract
When few and element active area (AA) contact area, problem will more deteriorate.
The mode improved at present is to use line style contact structure；Namely capacitor contact window is changed using line style knot
Structure, to increase contact area.However, thus just need additional storage node structure to connect line style contact structure,
And it because during making line style contact structure, needs to remove more lead in chemically mechanical polishing (CMP) manufacturing process
Electric material, so being easy to damage peripheral cell.
Invention content
The present invention provides a kind of semiconductor structure, can reduce the resistance value between substrate and contact window plug, and avoid line style
Problem caused by contact structure occurs.
The semiconductor structure of the present invention include at least with the substrates of several raceway grooves, the embedded type word line in raceway groove,
Separation layer, polysilicon clearance wall on embedded type word line and contact window plug, wherein there is substrate dew between above-mentioned raceway groove
Go out.The top surface of embedded type word line is less than the surface one second of substrate less than one first distance of surface of substrate, the top surface of separation layer
Distance.The side wall of polysilicon clearance wall then raceway groove of the position on separation layer, to be in direct contact with substrate.Contact window plug position is in base
It is connected on plate and respectively with polysilicon clearance wall with electrical property of substrate.
In one embodiment of this invention, above-mentioned contact window plug includes capacitor contact window plug.
In one embodiment of this invention, above-mentioned second distance is less than the thickness of the separation layer.
In one embodiment of this invention, the thickness of above-mentioned each polysilicon clearance wall is between 5nm~15nm.
In one embodiment of this invention, above-mentioned semiconductor structure may also include between substrate and embedded type word line one absolutely
Edge layer.
In one embodiment of this invention, above-mentioned semiconductor structure may also include the gold positioned at the surface of polysilicon clearance wall
Belong to silicide layer, and is in direct contact with contact window plug.The metal silicide layer includes silicon cobalt substrate, nickel silicide layer or silication
Titanium layer.
In one embodiment of this invention, above-mentioned semiconductor structure may also include position on substrate and across embedded type word line
Bit line.
In one embodiment of this invention, above-mentioned semiconductor structure may also include the metal silicide positioned at the surface of bit line
Layer, wherein the metal silicide layer includes silicon cobalt substrate, nickel silicide layer or titanium silicide layer.
Based on above-mentioned, of the invention structure by polysilicon clearance wall (with metal silicide layer), inserted to increase contact hole
The contact area of plug and substrate maintains the magnitude of current of array element so the resistance value between substrate and contact window plug can be reduced.
In addition, the present invention uses pass contact hole, so the problem of will not facing current line style contact hole.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make
Carefully it is described as follows.
Description of the drawings
Figure 1A is the diagrammatic cross-section according to a kind of semiconductor structure of the first embodiment of the present invention.
Figure 1B is the diagrammatic cross-section according to a kind of semiconductor structure of the second embodiment of the present invention.
Fig. 2A to Fig. 2 E is the manufacturing process sectional view according to a kind of semiconductor structure of the third embodiment of the present invention.
Fig. 3 A to Fig. 3 C are the manufacturing process sectional views according to a kind of semiconductor structure of the fourth embodiment of the present invention.
Fig. 4 A are the schematic top plan views of the semiconductor structure of Fig. 3 A.
Fig. 4 B are the schematic top plan views of the semiconductor structure of Fig. 3 C.
Wherein, the reference numerals are as follows：
100、200：Substrate
100a、200a、220a：Surface
102、216：Embedded type word line
102a、104a、218a：Top surface
104、218：Separation layer
106、220：Polysilicon clearance wall
108、226、310：Contact window plug
110、208：Raceway groove
112、230：Region
114、212：Barrier layer
116、222、306：Dielectric layer
118：Insulating layer
120、206a：Hard mask
122、202：Trench isolation structures
124、304：Metal silicide layer
204：High-density plasma oxide layer
206b：Polysilicon mask
210：Silicon oxide layer
214、300：Metal layer
224、308：Contact window opening
228：Contact area
302：Silicon nitride cap layer
400：Bit line
CA：Contact area
d1：First distance
d2：Second distance
t1、t2：Thickness
Specific implementation mode
Figure 1A is the diagrammatic cross-section according to a kind of semiconductor structure of the first embodiment of the present invention.
Figure 1A is please referred to, the semiconductor structure of the present embodiment includes at least substrate 100, embedded type word line 102, is located at embedment
Separation layer 104, polysilicon clearance wall 106 and contact window plug 108, the separation layer 104 in formula wordline 102 are, for example,
SiN.There are multiple raceway grooves 110 in substrate 100, and the region 112 between raceway groove 110 is exposed.Embedded type word line 102 is
Position is in raceway groove 110, and its top surface 102a is less than surface 100a the first distance d1 of substrate 100, as between 80nm~100nm.
In addition, one layer of barrier layer 114 can be set between embedded type word line 102 and raceway groove 110, such as Ti/TiN.104 same position of separation layer is in ditch
In road 110, and the top surface 104a of separation layer 104 be less than substrate 100 surface 100a second distance d2, as 30nm~40nm it
Between.In one embodiment, second distance d2 is less than the thickness t1 of separation layer 104, but the present invention is not limited thereto.As for polysilicon
Clearance wall 106 is the side wall of raceway groove 110 of the position on separation layer 104, to be in direct contact with contact window plug 108.In another reality
It applies in example, between thickness t2 for example, about 5nm~15nm of polysilicon clearance wall 106, but the present invention is not limited thereto.Contact hole is inserted
Plug 108 is electrical connected with polysilicon clearance wall 106 and the region 112 of substrate on the substrate 100 and respectively, and contact window plug
108 usually positions are in dielectric layer 116.In addition, insulating layer 118 can be set between substrate 100 and each embedded type word line 102,
To reduce the interference between embedded type word line 102.And hard mask 120 can be equipped on the substrate 100 between raceway groove 110, it is
Etching mask (mask) used when raceway groove 110 is made, the part as semiconductor structure can be remained, but the present invention is simultaneously
It is without being limited thereto；That is, the hard mask of this layer 120 can also remove after forming polysilicon clearance wall 106.Moreover, hard mask 120
E.g. SiN layer.
In figure 1A, there are one trench isolation structures 122 wherein between two embedded type word lines 102, to separate base
Plate 100 becomes at least two active areas, but the present invention is not limited thereto；In other words, other isolation junctions can be set in substrate 100
Structure does not set isolation structure.
In one embodiment, if above-mentioned semiconductor structure is applied to dynamic random access memory, contact window plug
108 can be capacitor contact window plug.
Figure 1B is according to a kind of diagrammatic cross-section of semiconductor structure of the second embodiment of the present invention, wherein using and
One embodiment identical component symbol represents same or analogous component.
Please refer to Figure 1B, the semiconductor structure in the present embodiment in addition to substrate 100, embedded type word line 102, separation layer 104,
Polysilicon clearance wall 106 and contact window plug 108, the metal of the also one layer surface 106a for being located at polysilicon clearance wall 106
Silicide layer 124, and be in direct contact with contact window plug 108.Wherein, metal silicide layer 124 such as silicon cobalt substrate, nickle silicide
Layer or titanium silicide layer, can further decrease the contact resistance (contact between the region 112 of substrate and contact window plug 108
resistance)。
The making of structure about the present invention, can refer to following manufacturing process, but the present invention is not limited thereto.
Fig. 2A to Fig. 2 E is the manufacturing process sectional view according to a kind of semiconductor structure of the third embodiment of the present invention.
Please also refer to Fig. 2A, the trench isolation structures 202 for defining active area are first produced in a substrate 200, and in ditch
One floor height density plasma oxide layer 204 can be set on road isolation structure 202.Then, using hard mask 206a and thereon
Polysilicon mask 206b etches multiple raceway grooves 208 as etching mask in substrate 200.Above-mentioned hard mask 206a is, for example,
SiN layer.Then, it is formed and is aoxidized on 208 surface of raceway groove using the manufacturing process such as steam generation technology (ISSG) etc of coming personally
Silicon layer 210, while also can form silicon oxide layer 210 on the surfaces polysilicon mask 206b.
Then, Fig. 2 B are please referred to, sequentially form barrier layer 212 and metal layer 214, wherein barrier layer 212 in raceway groove 208
For example Ti/TiN, metal layer 214 for example tungsten (W).Then, it is etched back above-mentioned barrier layer 212 and metal layer 214, to obtain flush type
Wordline 216.
Later, Fig. 2 C are please referred to, using such as atomic layer depositing (ALD) technology layer deposited isolating 218 in raceway groove 208, then
Using the polysilicon mask 206b of Fig. 2 B as etching mask, etch-back separation layer 218, until its top surface 218a is less than substrate 200
Surface 200a (such as range of 30nm~40nm), the separation layer 218 be, for example, SiN.Then, the polysilicon of Fig. 2 B is covered
Film 206b removals recycle wet dip (wet dip) mode such as to remove the next silicon oxide layer 210 exposed above of separation layer 218.
Then, Fig. 2 D are please referred to, one layer of polysilicon layer (not being painted) is deposited, thickness can be controlled in the diameter D of raceway groove 208
1/10~1/3 between (such as the range of 5nm~15nm), clearance wall is subsequently formed with profit.Then, polysilicon layer is carried out such as
The manufacturing process of reactive ion etching (RIE), to form polysilicon clearance wall in 208 side wall of raceway groove on separation layer 218
220。
Then, Fig. 2 E are please referred to, (are such as making grid or bit line) after Subsequent semiconductor manufacturing process, Yu Ji
Dielectric layer 222 on plate 200 re-forms the contact window opening 224 across dielectric layer 222 and the hard mask 206a in part.Then, in
It contacts and forms contact window plug 226 in window opening 224, to be in direct contact in polysilicon clearance wall 220 and substrate 200.Because of polycrystalline
The presence of silicon clearance wall 220, contact window plug 226 and the contact area 228 of substrate 200 will increase polysilicon clearance wall 220
Area, therefore contact resistance therebetween can be reduced.
Fig. 3 A to Fig. 3 C be according to a kind of manufacturing process sectional view of semiconductor structure of the fourth embodiment of the present invention, and
The present embodiment is to connect figure 2 above D, so partial component is identical as 3rd embodiment.
Fig. 3 A are please referred to, after forming polysilicon clearance wall 220, can first carry out the making of other semiconductor structures as schemed
The bit line 400 of 4A, the comprehensively deposited metal layer 300, and the deposited silicon nitride head cover on metal layer 300 on substrate 200
Layer (cap layer) 302, wherein above-mentioned metal layer 300 such as cobalt layers, nickel layer or titanium layer.
Then, Fig. 3 B are please referred to, first time rapid thermal treatment (RTP) manufacturing process are carried out, in polysilicon clearance wall 220
Surface 220a formed metal silicide layer 304 (such as CoSix, NiSix, TiSix), and at this time bit line (Fig. 4 A and Fig. 4 B's
400) surface can also form metal silicide layer.Later, silicon nitride cap layer 302 and remaining metal layer 300 are removed completely.
Then, Fig. 3 C are please referred to, second of rapid thermal treatment (RTP) manufacturing process can be carried out, to reduce resistance value.Then,
In dielectric layer 306 on substrate 200, the contact window opening 308 across dielectric layer 306 and the hard mask 206a in part is re-formed, so
Afterwards in forming contact window plug 310 in contact window opening 308, in metal silicide layer 304, polysilicon clearance wall 220 and substrate
200 are in direct contact.Such as with Fig. 4 B of vertical view from the point of view of, contact window plug 310 can by polysilicon clearance wall 220, and increase and base
Contact area CA between plate 200.
In conclusion the present invention by polysilicon clearance wall, increases the contact area between substrate and contact window plug, and by
This reduces contact resistance between the two.It therefore, needn't when the present invention is applied to the device such as dynamic random access memory
In addition it makes storage node structure and comes connecting substrate and line style contact structure, and be avoided that needed for line style contact structure
During more CMP manufacturing process separate line style contact structure to become each independent contact window, peripheral cell is caused
The possibility of damage.In addition, the present invention can also reduce the metal silicide of resistance value in the formation of above-mentioned polysilicon gap wall surface
Layer.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
In technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore the guarantor of the present invention
Range is protected when subject to appended claims institute defender.
Claims (10)
1. a kind of semiconductor structure, including：
One substrate has most raceway grooves；
Most embedded type word lines, position is in the raceway groove of the substrate, and the top surface of the embedded type word line is less than described
One first distance of surface of substrate；
Most separation layers, are located in the raceway groove on the embedded type word line, and the top surface of the separation layer is less than
One second distance of surface of the substrate；
Most polysilicon clearance walls, the side wall of the raceway groove of the position on the separation layer, to be in direct contact with the substrate；
And
Most contact window plugs, position on the substrate and respectively with the polysilicon clearance wall and the electrical property of substrate phase
Even.
2. semiconductor structure as described in claim 1, wherein the contact window plug includes capacitor contact window plug.
3. semiconductor structure as described in claim 1, wherein the second distance is less than the thickness of the separation layer.
4. semiconductor structure as described in claim 1, wherein the thickness of each polysilicon clearance wall 5nm~15nm it
Between.
5. semiconductor structure as described in claim 1 further includes an insulating layer, it is located at the substrate and each flush type
Between wordline.
6. semiconductor structure as described in claim 1 further includes most metal silicide layers, is located at the polysilicon
The surface of clearance wall, and be in direct contact with the contact window plug.
7. semiconductor structure as claimed in claim 6, wherein the metal silicide layer include silicon cobalt substrate, nickel silicide layer or
Titanium silicide layer.
8. semiconductor structure as described in claim 1 further includes most bit lines, position is buried on the substrate and across described
Enter formula wordline.
9. semiconductor structure as claimed in claim 8 further includes most metal silicide layers, is located at the bit line
Surface.
10. semiconductor structure as claimed in claim 9, wherein the metal silicide layer includes silicon cobalt substrate, nickel silicide layer
Or titanium silicide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410424367.6A CN105374820B (en) | 2014-08-26 | 2014-08-26 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410424367.6A CN105374820B (en) | 2014-08-26 | 2014-08-26 | Semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN105374820A CN105374820A (en) | 2016-03-02 |
| CN105374820B true CN105374820B (en) | 2018-07-17 |
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| CN201410424367.6A Active CN105374820B (en) | 2014-08-26 | 2014-08-26 | Semiconductor structure |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346666B (en) * | 2017-01-23 | 2022-10-04 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN113437070B (en) * | 2021-07-09 | 2023-05-23 | 福建省晋华集成电路有限公司 | Semiconductor device and method for forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN103178019A (en) * | 2011-12-20 | 2013-06-26 | 华邦电子股份有限公司 | Method for manufacturing word lines of embedded flash memory |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
-
2014
- 2014-08-26 CN CN201410424367.6A patent/CN105374820B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN103178019A (en) * | 2011-12-20 | 2013-06-26 | 华邦电子股份有限公司 | Method for manufacturing word lines of embedded flash memory |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
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| CN105374820A (en) | 2016-03-02 |
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