TWI539567B - Semiconductor structure for reducing contact resistance - Google Patents

Description

Semiconductor structure with reduced contact resistance

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure that reduces contact resistance.

Dynamic random access memory faces more and more difficulties as components develop into the nano generation. For example, as the contact area decreases, the component current gradually decreases. Especially when the position of the capacitor contact window is slightly offset, and the contact area with the active area (AA) of the element is reduced, the problem is further deteriorated.

The current improvement method is to adopt a linear contact window structure; that is, the capacitor contact window is changed to a linear structure to increase the contact area. However, in this case, an additional storage node structure is required to connect the line contact window structure, and since more conductive material needs to be removed during the CMP process during the fabrication of the line contact window structure, damage to peripheral components is easily caused.

The invention provides a semiconductor structure capable of reducing a substrate and a contact window plug The resistance between the values and avoiding the problems caused by the linear contact window structure.

The semiconductor structure of the present invention includes at least a substrate having a plurality of trenches, a buried word line located in the trench, an isolation layer on the buried word line, a polysilicon spacer, and a contact window plug, wherein the trench is between A substrate is exposed. The top surface of the buried word line is lower than the surface of the substrate by a first distance, and the top surface of the isolation layer is lower than the surface of the substrate by a second distance. The polysilicon spacer is located on the sidewall of the trench on the isolation layer to be in direct contact with the substrate. The contact window plugs are located on the substrate and are electrically connected to the substrate respectively with the polysilicon spacers.

In an embodiment of the invention, the contact window plug includes a capacitor contact window plug.

In an embodiment of the invention, the second distance is smaller than the thickness of the isolation layer.

In an embodiment of the invention, the thickness of each of the polysilicon spacers is between 5 nm and 15 nm.

In an embodiment of the invention, the semiconductor structure may further include an insulating layer between the substrate and the buried word line.

In an embodiment of the invention, the semiconductor structure may further include a metal telluride layer on the surface of the polysilicon spacer and in direct contact with the contact plug. The metal telluride layer comprises a cobalt antimonide layer, a nickel telluride layer or a titanium telluride layer.

In an embodiment of the invention, the semiconductor structure may further include a bit line on the substrate and across the buried character.

In an embodiment of the invention, the semiconductor structure may further include a metal telluride layer on the surface of the bit line, wherein the metal telluride layer comprises a cobalt antimonide layer, a nickel telluride layer or a titanium telluride layer.

Based on the above, the structure of the present invention increases the contact area between the contact window plug and the substrate by the polysilicon spacer (with the metal germanide layer), so that the resistance between the substrate and the contact plug can be reduced, and the array element can be maintained. The amount of current. In addition, the present invention uses a hole type contact window, so that it does not face the problem of the current line type contact window.

The above described features and advantages of the invention will be apparent from the following description.

100, 200‧‧‧ substrate

100a, 200a, 220a‧‧‧ surface

102, 216‧‧‧ Buried word line

102a, 104a, 218a‧‧‧ top

104, 218‧‧‧ isolation layer

106, 220‧‧‧ Polysilicon spacer

108, 226, 310‧‧‧ contact window plug

110, 208‧‧‧ Ditch

112, 230‧‧‧ areas

114, 212‧‧‧ barrier layer

116, 222, 306‧‧‧ dielectric layer

118‧‧‧Insulation

120, 206a‧‧‧hard mask

122, 202‧‧‧ Ditch isolation structure

124, 304‧‧‧ metal telluride layer

204‧‧‧High-density plasma oxide layer

206b‧‧‧Polysilicon mask

210‧‧‧Oxide layer

214, 300‧‧‧ metal layer

224, 308‧‧‧ contact window

228‧‧‧Contact area

302‧‧‧Nitrided tantalum cap

400‧‧‧ bit line

C _A ‧‧‧Contact area

D1‧‧‧first distance

D2‧‧‧Second distance

T1, t2‧‧‧ thickness

1A is a schematic cross-sectional view of a semiconductor structure in accordance with a first embodiment of the present invention.

1B is a schematic cross-sectional view of a semiconductor structure in accordance with a second embodiment of the present invention.

2A through 2E are cross-sectional views showing a manufacturing process of a semiconductor structure in accordance with a third embodiment of the present invention.

3A through 3C are cross-sectional views showing a manufacturing process of a semiconductor structure in accordance with a fourth embodiment of the present invention.

4A is a top plan view of the semiconductor structure of FIG. 3A.

4B is a top plan view of the semiconductor structure of FIG. 3C.

1A is a schematic cross-sectional view of a semiconductor structure in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, the semiconductor structure of the present embodiment includes at least a substrate 100, a buried word line 102, an isolation layer 104 on the buried word line 102, a polysilicon spacer 106, and a contact window plug 108. The isolation layer 104 is, for example, SiN. There are a plurality of trenches 110 in the substrate 100, and regions 112 between the trenches 110 are exposed. The buried word line 102 is located within the trench 110, and its top surface 102a is lower than the surface 100a of the substrate 100 by a first distance d1, such as between 80 nm and 100 nm. In addition, a barrier layer 114, such as Ti/TiN, may be disposed between the buried word line 102 and the trench 110. The isolation layer 104 is also located in the trench 110, and the top surface 104a of the isolation layer 104 is lower than the surface 100a of the substrate 100 by a second distance d2, such as between 30 nm and 40 nm. In an embodiment, the second distance d2 is smaller than the thickness t1 of the isolation layer 104, but the invention is not limited thereto. As for the polysilicon spacers 106, the sidewalls of the trenches 110 on the isolation layer 104 are in direct contact with the contact plugs 108. In another embodiment, the thickness t2 of the polysilicon spacer 106 is, for example, between about 5 nm and 15 nm, but the invention is not limited thereto. The contact window plugs 108 are located on the substrate 100 and are electrically connected to the polysilicon spacers 106 and the regions 112 of the substrate, respectively, and the contact window plugs 108 are generally located within the dielectric layer 116. In addition, an insulating layer 118 may be disposed between the substrate 100 and each of the buried word lines 102 to reduce interference between the buried word lines 102. A hard mask 120 may be disposed on the substrate 100 between the trenches 110. The etching mask used in the fabrication of the trenches 110 may be retained as part of the semiconductor structure, but the present invention This is not limited to this; that is, the hard mask 120 may also be removed after the formation of the polysilicon spacers 106. Moreover, the hard mask 120 is, for example, a SiN layer.

In FIG. 1A, a trench isolation structure 122 is disposed between two of the buried word lines 102 to separate the substrate 100 into at least two active regions, but the present invention is not limited thereto; in other words, the substrate Other isolation structures may be provided in 100 or no isolation structure.

In one embodiment, if the semiconductor structure described above is applied to a dynamic random access memory, the contact window plug 108 can be a capacitor contact window plug.

1B is a schematic cross-sectional view of a semiconductor structure in accordance with a second embodiment of the present invention, wherein the same reference numerals are used to denote the same or similar components.

Referring to FIG. 1B, in addition to the substrate 100, the buried word line 102, the isolation layer 104, the polysilicon spacer 106, and the contact plug 108, the semiconductor structure in this embodiment has a layer 106a on the surface of the polysilicon spacer 106. The metal telluride layer 124 is in direct contact with the contact plug 108. Among them, the metal telluride layer 124 such as a cobalt antimonide layer, a nickel telluride layer or a titanium telluride layer can further reduce the contact resistance between the region 112 of the substrate and the contact plug 108.

Regarding the production of the structure of the present invention, the following manufacturing flow can be referred to, but the present invention is not limited thereto.

2A through 2E are cross-sectional views showing a manufacturing process of a semiconductor structure in accordance with a third embodiment of the present invention.

Referring first to FIG. 2A, a defined active area is first formed in a substrate 200. The trench isolation structure 202, and a high density plasma oxide layer 204 may be disposed on the trench isolation structure 202. Then, a plurality of trenches 208 are etched into the substrate 200 by using the hard mask 206a and the polysilicon mask 206b thereon as an etching mask. The hard mask 206a is, for example, a SiN layer. Next, a ruthenium oxide layer 210 may be formed on the surface of the trench 208 by a process such as on-site vapor generation (ISSG), and a ruthenium oxide layer 210 may also be formed on the surface of the polysilicon mask 206b.

Then, referring to FIG. 2B, a barrier layer 212 and a metal layer 214 are sequentially formed in the trench 208, wherein the barrier layer 212 is, for example, Ti/TiN, and the metal layer 214 such as tungsten (W). Next, the barrier layer 212 and the metal layer 214 are etched back to obtain the buried word line 216.

Thereafter, referring to FIG. 2C, an isolation layer 218 is deposited in the trench 208 by, for example, atomic layer deposition (ALD), and the spacer 218 is etched back using the polysilicon mask 206b of FIG. 2B as an etch mask until its top surface 218a Below the surface 200a of the substrate 200 (for example, in the range of 30 nm to 40 nm), the isolation layer 218 is, for example, SiN. Then, the polysilicon mask 206b of FIG. 2B is removed, and the yttrium oxide layer 210 exposed above the isolation layer 218 is removed by a wet dip method.

Next, referring to FIG. 2D, a polysilicon layer (not shown) is deposited, and the thickness thereof can be controlled between 1/10 and 1/3 of the diameter D of the trench 208 (for example, a range of 5 nm to 15 nm) for subsequent formation. Clearance wall. Then, a process such as reactive ion etching (RIE) is performed on the polysilicon layer to form a polysilicon spacer 220 on the sidewall of the trench 208 on the isolation layer 218.

Then, please refer to Figure 2E, after the subsequent semiconductor process (such as production) A gate or a bit line, etc., a dielectric layer 222 is deposited over the substrate 200, and a contact via 224 is formed through the dielectric layer 222 and a portion of the hard mask 206a. Subsequently, a contact plug 226 is formed in the contact window 224 to directly contact the polysilicon spacer 220 and the substrate 200. Because of the presence of the polysilicon spacers 220, the contact regions 228 of the contact window plugs 226 and the substrate 200 will increase the area of the polysilicon spacers 220, thereby reducing the contact resistance therebetween.

3A through 3C are cross-sectional views showing a manufacturing process of a semiconductor structure in accordance with a fourth embodiment of the present invention, and the present embodiment is continued from Fig. 2D, so that some of the members are the same as the third embodiment.

Referring to FIG. 3A, after the polysilicon spacers 220 are formed, other semiconductor structures may be fabricated as in the bit line 400 of FIG. 4A, and then the metal layer 300 is deposited on the substrate 200 and deposited on the metal layer 300. A tantalum nitride cap layer 302, wherein the metal layer 300 is, for example, a cobalt layer, a nickel layer or a titanium layer.

Then, referring to FIG. 3B, a first rapid thermal processing (RTP) process is performed to form a metal telluride layer 304 (such as CoSix, NiSix, TiSix, etc.) on the surface 220a of the polysilicon spacer 220, and at this time, the bit line ( The surface of the 400) of FIG. 4 also forms a metal telluride layer. Thereafter, the tantalum nitride cap layer 302 and the remaining metal layer 300 are completely removed.

Next, referring to FIG. 3C, a second rapid thermal processing (RTP) process can be performed to reduce the resistance. Then, a dielectric layer 306 is deposited on the substrate 200, and a contact window 308 is formed through the dielectric layer 306 and a portion of the hard mask 206a. Then, a contact plug 310 is formed in the contact hole 308 to form a metal telluride layer. 304, the polysilicon spacer 220 and the substrate 200 are in direct contact. As seen in plan view of FIG. 4B, the contact window plug 310 can increase the contact area C _A with the substrate 200 by the polysilicon spacers 220.

In summary, the present invention increases the contact area between the substrate and the contact plug by the polysilicon spacer, and thereby reduces the contact resistance between the two. Therefore, when the present invention is applied to a device such as a dynamic random access memory, it is not necessary to separately fabricate a storage node structure to connect the substrate to the line contact window structure, and to avoid more CMP process separation linear contact required for the line contact window structure. The possibility that the window structure will cause damage to peripheral components during the process of becoming individual contact windows. Further, the present invention can also form a metal telluride layer capable of lowering the resistance on the surface of the polysilicon spacer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate

100a‧‧‧ surface

102‧‧‧Blinded word line

102a, 104a‧‧‧ top

104‧‧‧Isolation

106‧‧‧Polysilicon spacers

108‧‧‧Contact window plug

110‧‧‧ Ditch

112‧‧‧Area

114‧‧‧Barrier layer

116‧‧‧Dielectric layer

118‧‧‧Insulation

120‧‧‧hard mask

122‧‧‧ Ditch isolation structure

D1‧‧‧first distance

D2‧‧‧Second distance

T1, t2‧‧‧ thickness

Claims (10)

A semiconductor structure comprising: a substrate having a plurality of trenches; a plurality of buried word lines located in the trenches of the substrate, and a top surface of the buried word line is lower than the a surface of the substrate is a first distance; a plurality of isolation layers are respectively located in the trenches on the buried word line, and a top surface of the isolation layer is lower than a surface of the substrate by a second distance; a polysilicon spacer, a sidewall of the trench on the isolation layer to be in direct contact with the substrate; and a plurality of contact plugs on the substrate and respectively associated with the polysilicon spacer The substrates are electrically connected. The semiconductor structure of claim 1, wherein the contact window plug comprises a capacitor contact window plug. The semiconductor structure of claim 1, wherein the second distance is less than a thickness of the isolation layer. The semiconductor structure of claim 1, wherein each of the polysilicon spacers has a thickness of between 5 nm and 15 nm. The semiconductor structure of claim 1, further comprising an insulating layer between the substrate and each of the buried word lines. The semiconductor structure of claim 1, further comprising a plurality of metal telluride layers respectively located on a surface of the polysilicon spacer and in direct contact with the contact plug. The semiconductor structure of claim 6, wherein the metal telluride layer comprises a cobalt antimonide layer, a nickel telluride layer or a titanium telluride layer. The semiconductor structure of claim 1, further comprising a plurality of bit lines on the substrate and across the buried word line. The semiconductor structure of claim 8 further comprising a plurality of metal telluride layers respectively located on the surface of the bit line. The semiconductor structure of claim 9, wherein the metal telluride layer comprises a cobalt antimonide layer, a nickel telluride layer or a titanium telluride layer.