KR20180018239A - Semiconductor Memory Device - Google Patents

Abstract

The present invention provides a semiconductor memory device having improved reliability and electrical properties. The semiconductor memory device comprises: word lines extended in a first direction on a semiconductor substrate; bit line structures crossing the word lines, and extended in a second direction intersecting the first direction; contact pad structures provided between the word lines and between the bit line structures, in a plan viewpoint; and a spacer structure interposed between the bit line structures and the contact pad structures. The spacer structure includes: a first air gap extended in the second direction along one side walls of the bit line structures; and a second air gap surrounding each of the contact pad structures and connected to the first air gap, in the plan viewpoint.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a spacer structure having an air gap.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, and a hybrid semiconductor element including a memory element and a logic element.

Semiconductor devices in general can include vertically stacked patterns and contact plugs for electrically connecting them. As semiconductor devices become more highly integrated, the spacing between patterns and / or the spacing between patterns and contact plugs is being reduced. This can increase the parasitic capacitance between the patterns and / or between the pattern and the contact plug. The parasitic capacitance may cause deterioration in the performance of the semiconductor device such as a decrease in the operating speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device with improved reliability and electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor memory device including word lines extending in a first direction on a semiconductor substrate; Bit line structures extending in a second direction across the word lines, the bit line structures intersecting the first direction; In a plan view, contact pad structures are provided between the word lines and between the bit line structures; And a spacer structure interposed between the bit line structures and the contact pad structures, the spacer structure comprising: A first air gap extending in the second direction along one side walls of the bit line structures; And a second air gap that surrounds each of the contact pad structures and is connected to the first air gap, from a plan viewpoint.

According to an aspect of the present invention, there is provided a semiconductor memory device including word lines extending in a first direction in a semiconductor substrate; Bit line structures extending in a second direction across the word lines, the bit line structures intersecting the first direction; In plan view, contact pad structures disposed between and between the bit line structures; Insulator patterns disposed on the word lines and disposed between the contact pad structures and between the bit line structures in plan view; And a spacer structure disposed between the bit line structures and the contact pad structures, the spacer structure comprising: a plurality of bit line structures and a plurality of contact pattern structures between the bit line structures and the contact pattern structures, First and second spacers extending between the first and second spacers; A first air gap provided between the first and second spacers and extending in the second direction; And a second air gap extending along the first direction between the insulation patterns and the contact pad structures from the first air gap.

According to an aspect of the present invention, there is provided a semiconductor memory device including first and second bit line structures extending in a first direction on a semiconductor substrate, Each having first and second sidewalls facing each other; Contact pad structures spaced apart from each other in the first direction between the first and second bit line structures; A first spacer structure comprising a first air gap extending along the first sidewall of the first bit line structure; A second spacer structure including a second air gap extending along the second sidewall of the second bit line structure; And a third spacer structure surrounding the contact pad structures and including a third air gap connecting the first air gap and the second air gap.

Embodiments of the present invention may form a first sacrificial spacer extending along one side walls of the bit line structures and a second sacrificial spacer surrounding the bottom of the landing pad and in direct contact with the first sacrificial spacer. Thus, when forming an air gap between the bit line structures and the contact pad structures, it may be easier to remove the first sacrificial spacer obscured by the landing pads.

According to embodiments, the parasitic capacitance between the bit line structures and the contact pad structures can be reduced because an air gap is formed that extends along the sidewalls of the bit line structures and surrounds the bottom of the landing pad. Therefore, the reliability and electrical characteristics of the semiconductor memory device can be further improved.

1A is a plan view of a semiconductor memory device according to embodiments of the present invention.
1B shows a section cut along line AA 'and line BB' in FIG. 1A.
FIG. 1C shows a section cut along the line CC 'and DD' in FIG. 1A.
FIG. 2A is an enlarged view of a portion A in FIG. 1A, and FIG. 2B is an enlarged view of a portion B in FIG. 1B.
Fig. 2c is a diagram showing various embodiments of the present invention, showing part B of Fig. 1b.
Figs. 3A and 3B show various embodiments of the present invention, wherein Fig. 3A shows part A of Fig. 1A, and Fig. 3B shows part B of Fig. 1B.
4A to 14A are plan views illustrating a method of manufacturing a semiconductor memory device according to embodiments of the present invention.
FIGS. 4B to 14B are cross-sectional views illustrating cross-sectional views taken along line AA 'and line BB' in FIGS. 4A to 14A to illustrate a method of manufacturing a semiconductor memory device according to embodiments of the present invention.
FIGS. 4C to 14C are cross-sectional views illustrating cross-sectional views taken along line CC 'and line DD' in FIGS. 4A to 14A to illustrate a method of manufacturing a semiconductor memory device according to embodiments of the present invention.

Hereinafter, a semiconductor memory device according to embodiments of the present invention will be described in detail with reference to the drawings.

1A is a plan view of a semiconductor memory device according to embodiments of the present invention. FIG. 1B shows a section cut along line A-A 'and line B-B' in FIG. 1A, and FIG. 1C shows a section cut along line C-C 'and D-D' in FIG. 1A.

FIG. 2A is an enlarged view of a portion A in FIG. 1A, and FIG. 2B is an enlarged view of a portion B in FIG. 1B. Fig. 2c is a diagram showing various embodiments of the present invention, showing part b of Fig. 1a. Fig.

Figs. 3A and 3B show various embodiments of the present invention, wherein Fig. 3A shows part A of Fig. 1A, and Fig. 3B shows part B of Fig. 1B.

Referring to Figs. 1A, 1B, and 1C, an element isolation film 101 defining active portions ACT in a semiconductor substrate 100 may be disposed. The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

According to one example, the active portions ACT have a rectangular shape (or a bar shape) and extend in a first direction D1 and a second direction D1 (e.g., perpendicular to the first direction D1) Dimensionally along the direction D2. The active portions ACT may be arranged in a zigzag form in plan view and may have a long axis in an oblique direction with respect to the first direction D1 and the second direction D2.

The word lines WL may be disposed in the semiconductor substrate 100 and may extend in the first direction D1 from the plan view so as to traverse the active portions ACT and the device isolation film 101. [

A gate insulating film 103 may be interposed between the word lines WL and the semiconductor substrate 100. The upper surfaces of the word lines WL may be located below the upper surface of the semiconductor substrate 100, The gate hard mask pattern 105 may be disposed on the lines WL.

The first and second impurity regions 1a and 1b may be formed in each of the active portions ACT on both sides of the word lines WL. The lower surfaces of the first and second impurity regions 1a and 1b may be located at a predetermined depth from the upper surface of the active portions ACT. The first impurity region 1a is disposed in each of the active portions ACT between the word lines WL and the second impurity regions 1b are spaced apart from the first impurity region 1a to form active portions ACT. As shown in FIG. The first and second impurity regions 1a and 1b may be doped with dopants having a conductivity type opposite to that of the semiconductor substrate 100.

The bit line structures BLS may extend in the second direction D2 across the word lines WL on the semiconductor substrate 100. In other embodiments, The bit line structures BLS may be provided on the first impurity regions 1a, respectively. According to one example, the bit line structures BLS may include a polysilicon pattern 121, a silicide pattern 122, a metal pattern 123, and a hard mask pattern 125 stacked in sequence. An interlayer insulating film 110 may be interposed between the polysilicon pattern and the semiconductor substrate 100 and a portion of the polysilicon pattern (hereinafter referred to as a bit line contact pattern DC) may contact the first impurity regions 1a . The lower surface of the bit line contact pattern DC may be located below the upper surface of the semiconductor substrate 100 and may be located above the upper surfaces of the word lines WL. In one example, the bit line contact pattern DC may be locally disposed in the recess region 111 formed in the semiconductor substrate 100 to expose the first impurity regions. The recess region 111 may have an elliptical shape and the minimum width of the recess region 111 may have a width greater than the width of each of the bit line structures BLS.

A bit line contact spacer DCP may fill the recess region 111 where the bit line contact pattern DC is formed. In one example, the bit line contact spacers DCP may cover both side walls of the bit line contact pattern DC. As another example, the bit line contact spacers (DCP) may surround the bit line contact patterns DC in the recess region 111. The bit line contact spacer DCP may be formed of an insulating material having etch selectivity with respect to the interlayer insulating film 110. For example, the bit line contact spacer (DCP) may include a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film, and may be formed of a multilayer film. In one example, the top surface of the bit line contact spacer (DCP) may be located at substantially the same level as the top surface of the interlayer insulating film 110.

According to the embodiments, the insulating patterns 143 may be disposed on the interlayer insulating film 110 in the second direction D2 between the bit line structures BLS. The insulating patterns 143 may overlap the word lines WL in plan view and may have a top surface at the same level as the top surfaces of the bit line structures BLS. In embodiments, the insulating patterns 143 may be formed of an insulating material having an etching selectivity to the interlayer insulating film 110.

According to the embodiments, the contact pad structures CPS connected to each of the second impurity regions 1b between the bit line structures BLS may be disposed. Each of the contact pad structures CPS may be disposed between the word lines WL and between the bit line structures BLS, in plan view. Each of the contact pad structures CPS may fill a space defined by the insulating patterns 143 adjacent in the second direction D2 to the adjacent bit line structures BLS in the first direction D1 .

The top surfaces of the contact pad structures CPS may be located above the top surfaces of the bit line structures BLS and some portions of the contact pad structures CPS may be formed in the planar view of the bit line structures BLS, Lt; / RTI > In embodiments, the top width of the contact pad structures CPS may be greater than the distance between the bit line structures BLS or the width of the bit line structures BLS.

In embodiments, each of the contact pad structures CPS may include a contact conductive pattern 153, a contact silicide pattern 155, and a landing pad (LP) in contact with the second impurity region 1b .

The contact conductive pattern 153 may be made of, for example, a polysilicon film doped with an impurity, and may directly contact the second impurity regions 1b through the interlayer insulating film 110. [ In one example, the contact conductive pattern 153 may be located below the top surface of the semiconductor substrate 100 and above the bottom surface of the bit line contact pattern DC. Also, the contact conductive pattern 153 can be insulated from the bit line contact pattern DC by a bit line contact spacer DCP. The upper surface of the contact conductive pattern 153 may be located below the upper surface of the metal pattern 123 of the bit line structure BLS.

The contact silicide pattern 155 covers the top surface of the contact conductive pattern 153 and may include, for example, titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. In another example, the contact silicide pattern 155 may be omitted.

The top surface of the landing pad LP may be located above the top surfaces of the bit line structures BLS and the bottom surface of the landing pad LP may be located below the top surfaces of the bit line structures BLS . For example, the lower surface of the landing pad LP may be located below the upper surface of the metal pattern 123 of the bit line structures BLS.

The landing pad LP may be electrically connected to each of the second impurity regions 1b through the contact silicide pattern 155 and the contact conductive pattern 153. [ The landing pad LP may comprise a metal barrier film pattern 157 and a pad metal pattern 159 stacked in turn.

According to embodiments, the landing pad LP includes a lower portion filled between the bit line structures BLS and the insulating patterns 143, and a portion of the bit line structures BLS at the lower portion. (Not shown). That is, the top of the landing pad LP may overlap with a portion of the bit line structures BLS from a plan viewpoint. In other words, the top width of the landing pad LP may be greater than the distance between the bit line structures BLS or the width of the bit line structures BLS. Thus, since the upper portion of the landing pad LP extends onto the bit line structures BLS, the area of the upper surface of the landing pad LP can be increased.

The upper portion of the landing pad LP may have an elliptical shape having a long axis and a short axis in plan view and an upper portion of the landing pad LP may be formed in the first direction D1 and the second direction D2 ) In the oblique direction. According to embodiments, the top of the landing pad LP may have a round diamond shape, a round trapezoid shape, or a round square shape.

According to embodiments, a spacer structure SS may be interposed between the bit line structures BLS and the contact pad structures CPS. The spacer structure includes a first air gap AG1 extending in a second direction D2 along one side walls of the bit line structures BLS and a second air gap AG2 extending in a planar view And a second air gap AG2 having a ring shape and connected to the first air gap AG1.

In one example, the spacer structure SS includes first and second spacers 131,135 defining the first air gap AG1 and a portion of the contact pad structures CPS between the bit line structures BLS. And a third spacer 139 defining a second air gap AG2 that surrounds the first air gap AG1 and is connected to the first air gap AG1.

2A and 2B, the first and second spacers 131 and 135 are formed on the interlayer insulating layer 110 in the second direction D2 along both side walls of the bit line structures BLS. . The first and second spacers 131 and 135 are formed between the bit line structures BLS and the contact pattern structures CPS and between the bit line structures BLS and the insulation patterns 143 in the second direction D2 As shown in FIG. The first and second spacers 131 and 135 may include an insulating material having an etching selectivity to the interlayer insulating film 110.

The first spacer 131 may be in contact with the sidewalls of the bit line structures BLS and the second spacer 135 may be spaced apart from the first spacer 131 and between the first spacer 131 and the second spacer 135 The first air gap AG1 can be defined. The first spacer 131 may extend to the sidewalls of the bit line contact pattern DC and the second spacer 135 may extend over the upper surface of the bit line contact spacer DCP and the interlayer insulating layer 110 As shown in FIG.

The second spacers 135 may include first portions 135a adjacent the contact pad structures CPS and second portions 135b adjacent to the insulating patterns 143. In some embodiments, . Here, the height of the first portions 135a may be smaller than the height of the second portions 135b. In other words, the upper surfaces of the first portions 135a may be located below the upper surfaces of the second portions 135b. Also, the upper surfaces of the first portions 135a of the second spacers 135 may be located above the upper surface of the contact conductive pattern 153.

The third spacer 139 may surround the lower portion of the landing pad LP on the first portions 135a of the second spacer 135. That is, the third spacer 139 may have a ring shape in plan view, and a portion of the third spacer 139 may be located below the top of the landing pad LP. That is, a portion of the third spacer 139 may overlap with the top of the landing pad LP in plan view.

More specifically, the third spacer 139 having a planar ring shape may include a first portion located below the landing pad LP and a second portion located between the landing pads LP. Here, the height of the second portion may be smaller than the height of the first portion.

In the embodiments, a part of the first air gap AG1 and a part of the second air gap AG2 may overlap with the landing pad LP in plan view.

In one example, a second air gap AG2 may be defined between the first spacer 131 and the third spacer 139, and between the insulating patterns 143 and the third spacer 139. As another example, the second air gap AG2 may be formed between the first spacer 131 and the contact pad structure CPS, and between the insulation patterns 143 and the contact pad structure < RTI ID = 0.0 > CPS).

2A and 2B, the second air gap AG2 has a ring shape in plan view, similar to the third spacer 139, and surrounds the lower portion of the landing pad LP . The second air gap AG2 may be connected to the first air gap AG1 between the bit line structures BLS and the contact pad structures CPS. The second air gap AG2 may extend from the first air gap AG1 along the first direction D1 between the insulating patterns 143 and the contact pad structures CPS. That is, the first air gap AG1 and the second air gap AG2 may be one empty space connected to each other. Further, since the second air gap AG2 extends along the first direction D1 between the contact pad structures CPS and the insulation patterns 143, the first air gap AG2 extends in the second direction D2, Gaps AG1 can be connected. In other words, between the adjacent bit line structures BLS, the first air gaps AG1 and the second air gap AG2 may be connected to each other to form one empty space.

The first air gap AG1 may have a first width defined by the distance between the first and second spacers 131,135 and the second air gap AG2 may have a first width defined by the distance between the first and second spacers & And a second width defined by the distance between the third spacer 131 and the third spacer 139 (or the distance between the insulating pattern and the third spacer 139). Here, the first width may be equal to or greater than the second width.

Further, the first air gap AG1 may include first regions adjacent to the contact pad structures CPS and second regions adjacent to the insulation patterns 143, and the first air gap AG1 The height may be larger in the second areas than in the first areas.

According to embodiments, the pad isolation pattern LPI may fill between the tops of the landing pads LP. The pad insulation pattern LPI may have a rounded bottom surface, and the second air gap AG2 may be closed by the lower surface of the pad insulation pattern LPI. The upper surface of the pad insulation pattern LPI may be coplanar with the upper surfaces of the landing pads LP.

The pad insulation pattern LPI may include a first capping insulation layer 161 and a second capping insulation layer 163 which are sequentially stacked. The first capping insulating film 161 may have a substantially uniform thickness and the second capping insulating film 163 may fill the space between the landing pads LP. The first capping insulating film may directly contact the hard mask patterns 125 of the landing pads LP and the bit line structures BLS. The first capping insulating layer 161 may cover the upper surface of the insulating patterns 143 and may be in direct contact with the second portions 135b of the second spacers 135 and a portion of the third spacers 139 . The first and second capping insulating films 161 and 163 may include a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

According to embodiments, data storage patterns (DSP) may be disposed on contact pad structures (CPS), respectively. The data storage patterns DSP may be electrically connected to the second impurity regions 1b through the contact pad structures CPS, respectively. Each of the data storage patterns DSP may be disposed in alignment with each of the landing pads LP of the contact pad structures CPS and may be in contact with a respective portion of the landing pads LP. In one example, the data storage patterns (DSP) may be arranged in a honeycomb or zigzag shape in plan view.

According to one example, the data storage patterns (DSP) may be capacitors and may include dielectric layers interposed between the lower and upper electrodes therebetween. Alternatively, the data storage patterns DSP can be a variable resistance pattern that can be switched to two resistive states by electrical pulses applied to the memory element. For example, data storage patterns (DSP) may include phase-change materials that vary in crystalline state depending on the amount of current, perovskite compounds, transition metal oxide, Magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

According to the embodiment shown in FIG. 2C, in the semiconductor memory device described with reference to FIGS. 1A, 1B and 1C, a first air gap AG1 is formed perpendicularly along the sidewalls of the bit line contact pattern DC It may be extended.

Referring to the embodiments shown in Figs. 3A and 3B, in the semiconductor memory device described with reference to Figs. 1A, 1B, and 1C, the third spacer 139 may be omitted. The second air gap AG2 may be provided between the first spacer 131 and the contact pad structure CPS and between the insulation pattern and the contact pad structure CPS.

4A to 14A are plan views illustrating a method of manufacturing a semiconductor memory device according to embodiments of the present invention. Figs. 4B to 14B show cross-sections taken along line A-A 'and line B-B' in Figs. 4A to 14A. Figs. 4C to 14C show cross-sections taken along line C-C 'and D-D' in Figs. 4A to 14A.

Referring to FIGS. 4A, 4B, and 4C, a device isolation film 101 may be formed on the semiconductor substrate 100 to define active portions ACT. According to one example, the active portions ACT have a rectangular shape (or a bar shape) and can be two-dimensionally arranged along the first direction D1 and the second direction D2. The active parts ACT may be arranged in a zigzag form in plan view and may have a long axis along the oblique direction with respect to the first direction D1 and the second direction D2.

A plurality of word lines WL extending in a first direction D1 may be disposed on the semiconductor substrate 100. [ In detail, gate recess regions 102 extending in the first direction D1 may be formed by patterning the active portions ACT and the element isolation film 101, and gate recess regions 102 may be formed in the gate recess regions 102 The word lines WL may be formed through the insulating film 103. [ The lower surfaces of the gate recess regions 102 may be located above the lower surface of the device isolation film 101. [ The upper surfaces of the word lines WL may be located below the upper surface of the element isolation film 101. [ Gate hard mask patterns 105 may be formed in the gate recess regions 102 where the word lines WL are formed.

After forming the word lines WL, the first and second impurity regions 1a and 1b may be formed in the active portions ACT on both sides of the word lines WL. The first and second impurity regions 1a and 1b may be formed by performing an ion implantation process and may have a conductivity type opposite to that of the active portion ACT.

Subsequently, an interlayer insulating film 110 may be formed on the entire surface of the semiconductor substrate 100. The interlayer insulating film 110 may include a single film or a plurality of insulating films. The interlayer insulating film 110 may include, for example, a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

The recess regions 111 may be formed by patterning the semiconductor substrate 100 and the interlayer insulating film 110 to expose the first impurity regions 1a respectively. In one example, the recessed regions 111 may have an elliptical shape with a long axis in the second direction D2. Further, the recessed regions 111 can be arranged in a zigzag shape or a honeycomb shape in plan view.

According to one example, in the anisotropic etching process for forming the recessed regions 111, the first impurity regions 1a and portions of the adjacent element isolation film 101 and the gate hard mask patterns 105 are etched together . The lower surfaces of the recess regions 111 may be located above the lower surface of the first impurity regions 1a and portions of the device isolation film 101 and the gate hard mask pattern 105 may be located in the recess regions 111 ). ≪ / RTI >

5A, 5B, and 5C, bit line structures BLS extending in a second direction D2 may be formed on an interlayer insulating film 110 having recessed regions 111 .

Forming the bit line structures BLS includes forming a first conductive film filling the recess regions 111 on the interlayer insulating film 110, forming a second conductive film on the first conductive film, Forming a hard mask film on the second conductive film, forming a bit line mask pattern on the hard mask film, and forming the first conductive film, the second conductive film, and the hard mask film in this order Etch. ≪ / RTI > The bit line mask pattern can then be removed. Here, the first conductive film may be formed of a semiconductor film doped with an impurity (for example, a doped polysilicon film), and the second conductive film may be formed of a metal film such as a tungsten film, an aluminum film, a titanium film or a tantalum film . Furthermore, a metal silicide film may be formed between the first conductive film and the second conductive film.

As the bit line structures BLS are formed, the bit line structures BLS sequentially form the polysilicon pattern 121, the silicide pattern 122, the metal pattern 123, and the hard mask pattern 125 A portion of the polysilicon pattern 121 may be locally formed in the recess regions 111 and a bit line contact pattern 112 in direct contact with the first impurity region < RTI ID = 0.0 > 1a & DC). In addition, the sidewalls of the polysilicon pattern 121 may be spaced apart from the sidewalls of the recess regions 111.

Referring to FIGS. 6A, 6B, and 6C, a first spacer 131 and a first sacrificial spacer 133 may be sequentially formed on the sidewalls of the bit line structures BLS.

More specifically, forming the first spacers 131 includes depositing a spacer film that fills the recessed regions 111 and conformally covers the bit line structures BLS, and anisotropically etching the spacer film. can do. Here, the spacer film may include a first nitride film, an oxide film, and a second nitride film sequentially stacked. When the spacer film is anisotropically etched, the oxide film can be used as an etch stop film, and the oxide film and the second nitride film can locally remain in the recess regions 111, and a bit line contact spacer (DCP) can be formed . The first nitride layer may remain in the recess regions 111 and on the sidewalls of the bit line structures BLS to form a first spacer 131. The first spacer 131 may have recessed regions 111 and a top portion that covers the sidewalls of the bit line structures BLS. The lower portion of the first spacer 131 may constitute a bit line contact spacer (DCP). The spacers 131 may extend in the second direction D2 along both sidewalls of the bit line structures BLS. According to one example, the first spacers 131 may extend in the second direction D2 along both sidewalls of the bit line structures BLS and may fill the recess regions 111. [

After forming the first spacer 131, a first sacrificial layer may be formed covering the entire surface of the resultant conformation. The first sacrificial layer may be anisotropically etched to form a first sacrificial spacer (not shown) on both sidewalls of the bit line structures BLS. (133) may be formed. The first sacrificial spacer 133 may be formed of an insulating material having an etching selectivity with respect to the first spacer 131, and may be formed of, for example, a silicon oxide film. The first sacrificial spacers 133 may extend in the second direction D2 along both sidewalls of the bit line structures BLS on the first spacers 131. [

Subsequently, after the first sacrificial spacer 133 is formed, a second spacer film 134 (not shown) covering the bitline structures BLS, the first sacrificial spacer 133, and the surface of the interlayer insulating film 110 in a conformal manner May be formed. The second spacer film 134 may be formed of an insulating material having an etch selectivity with respect to the first sacrificial spacer 133 and the interlayer insulating film 110, and may be formed of, for example, a silicon nitride film or a silicon oxynitride film .

Referring to FIGS. 7A, 7B, and 7C, the sacrificial patterns 141 and the insulating patterns 143, which are alternately arranged along the second direction D2, may be formed between the bit line structures BLS have. In embodiments, the insulating patterns 143 may be formed on the word lines WL, and the sacrificial patterns 141 may be formed on the second impurity regions 1b.

According to one example, forming the sacrificial patterns 141 and the insulating patterns 143 may include forming a sacrificial film between the bit line structures BLS on the second spacer film 134, Forming mask patterns (not shown) extending in the first direction D1 along the word lines WL on the film, using the bit line structures BLS and the mask pattern as etching masks Forming the sacrificial patterns 141 that expose the second spacer film 134 on the word lines WL by anisotropically etching the film and forming sacrificial patterns 141 between the sacrificial patterns 141 and the bit line structures BLS. And planarizing the insulating film to expose top surfaces of the mask patterns.

The sacrificial patterns 141 are arranged apart from each other in the second direction D2 from a plan view, and can be disposed between the word lines WL, respectively. The sacrificial patterns 141 may be formed of a material having etch selectivity with respect to the second spacer film 134. For example, the sacrificial patterns 141 may be formed of a spin-on-hard mask (SOH) material (ex, SOH silicon oxide). The top surfaces of the bit line structures BLS between the mask patterns may be etched while the sacrificial patterns 141 are formed.

The isolation patterns 143 may fill the void space defined by the sacrificial patterns 141 and the bit line structures BLS and may overlap the word lines WL in plan view. The insulating patterns 143 may be formed of an insulating material having etch selectivity with respect to the sacrificial patterns 141, and may be formed of, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

8A, 8B, and 8C, after forming the insulating patterns 143, etching is performed using the etching recipe having etching selectivity for the insulating patterns 143 and the second spacer film 134, The patterns 141 can be removed. Accordingly, the contact regions can be defined by the bit line structures BLS and the insulating patterns 143, and portions of the second spacer film 134 can be exposed

Subsequently, a portion of the second spacer film 134 exposed in the contact region, a portion of the interlayer insulating film 110, and a portion of the semiconductor substrate 100 (see FIG. 1) are exposed using the insulating patterns 143 and the bit line structures BLS as an etching mask. And a part of the device isolation film 101 may be anisotropically etched to form contact holes 145 exposing the second impurity regions 1b. As the contact holes 145 are formed, the second spacers 135 can be formed on both sidewalls of the bit line structures BLS.

A part of the semiconductor substrate 100 and a part of the element isolation film 101 may be etched when the contact holes 145 are formed. The lower surfaces of the contact holes 145 may be located below the upper surface of the semiconductor substrate 100 and the contact holes 145 may expose a portion of the bit line contact spacers DCP in the recessed regions 111 .

9A, 9B, and 9C, the preliminary contact patterns 151 filling the portions of the contact holes 145 may be formed. According to one example, the top surfaces of the preliminary contact patterns 151 may be located below the top surface of the hard mask patterns 125 of the bit line structures BLS.

The formation of the preliminary contact patterns 151 may be accomplished by depositing a conductive film filling the contact holes 145, planarizing the conductive film to expose the top surfaces of the bit line structures BLS and insulation patterns 143, And recessing the top surface of the conductive film. Thus, as the preliminary contact patterns 151 are formed, the upper portion of the second spacers 135 can be exposed in the contact holes 145.

The preliminary contact patterns 151 may be formed of a conductive material such as, for example, doped semiconductor material (ex, doped silicon, etc.), metal (ex, tungsten, aluminum, titanium, and / or tantalum) Nitride, tantalum nitride and / or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide).

The top surfaces of the insulating patterns 143 and the top surfaces of the bit line structures BLS may be recessed while forming the preliminary contact patterns 151 and the first sacrificial spacers 133 And the upper surfaces of the first and second spacers 131 and 135 may be exposed.

10A, 10B, and 10C, after forming the preliminary contact patterns 151, the second spacers 135 exposed in the contact holes 145 and the upper portions of the first sacrificial spacers 133 Can be etched. More specifically, it may include anisotropically or isotropically etching the second spacers 135 and the first sacrificial spacers 133 exposed in the contact holes 145 in order. The upper surfaces of the recessed first sacrificial spacer 133 and the second spacer 135 may be located at substantially the same level as the upper surfaces of the preliminary contact patterns 151. [ By etching the second spacers 135 and the first sacrificial spacers 133 in this manner, the width of the tops of the contact holes 145 that are not filled with the preliminary contact patterns 151 can be increased. In addition, portions of the hard mask pattern 125 may be etched together while etching the upper portions of the first sacrificial spacer 133 and the second spacers 135, May be reduced.

The second spacers 135 and the first sacrificial spacers 133 thus formed are electrically connected to the first portions 133a and 135a between the preliminary contact patterns 151 and the bit line structures BLS and the insulating patterns 143 And upper portions of the first portions 133a and 135a may include upper portions of the upper portions of the second portions 133b and 135b Can be located lower than. That is, the first portions 133a and 133a may have a height less than the height of the second portions 133b and 135b.

Referring to Figs. 11A, 11B, and 11C, from a plan viewpoint, a second sacrificial spacer 137 having a ring shape can be formed in the contact holes 145. Fig.

Forming the second sacrificial spacers 137 may include forming a second sacrificial spacer film that conformally covers the upper portions of the contact holes 145 and forming the second sacrificial spacer film anisotropically (e.g., etch- etch-back) to expose the top surfaces of the preliminary contact patterns 151. The second sacrificial spacer 137 may be disposed on the first sacrificial spacer 133 and the first portions 133a and 135a of the second spacer 135 and may include the first spacer 131 and the insulating patterns 143, respectively. In embodiments, the thickness of the second sacrificial spacer 137 may be equal to or less than the thickness of the first sacrificial spacer 133. Also, the second sacrificial spacer 137 can directly contact the upper surface of the first sacrificial spacer 133 (for example, upper surfaces of the first portions 133a). Furthermore, the second sacrificial spacers 137 can directly contact the two adjacent first sacrificial spacers 133 in one contact hole 145. The second sacrificial spacer 137 may be formed of the same material as the first sacrificial spacer 133 and may be formed of a material having etch selectivity with respect to the first and second spacers 131 and 135.

Referring to FIGS. 12A, 12B, and 12C, a third spacer 139 may be formed on the second sacrificial spacer 137. The third spacer 139 may be formed by forming a third spacer film conformally in the contact hole 145 in which the second sacrificial spacer 137 is formed, and then etching back the third spacer film. The third spacer 139 may be formed on the preliminary contact pattern 151 and on the first portions 133a and 135a of the first sacrificial spacer 133 and the second spacer 135. The third spacer 139 may be formed of an insulating material having an etch selectivity to the second sacrificial spacer 137 and may be thicker than the second sacrificial spacer 137.

After forming the third spacer 139, the contact conductive patterns 153 may be formed by recessing the upper surfaces of the preliminary contact patterns 151 exposed by the third spacers 139. In one example, the top surfaces of the contact conductive patterns 153 may be located below the top surfaces of the metal patterns 123 of the bit line structures BLS. Portions of the sidewalls of the first portions 135a of the second spacers 135 and portions of the sidewalls of the insulating patterns 143 may be exposed to the contact holes 145. [

Referring to FIGS. 13A, 13B, and 13C, contact silicide patterns 155 are formed on the upper surfaces of the contact conductive patterns 153 exposed by the second sacrificial spacer 137 and the third spacer 139 . The contact silicide patterns 155 may be formed by reacting the upper surface of the contact conductive patterns 153 with a metal material. The contact silicide patterns 155 may be formed of, for example, titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. On the other hand, according to another example, the process of forming the contact silicide pattern 155 may be omitted.

The landing pads LP that fill the contact holes 145 formed with the second sacrificial spacers 137 and the third spacers 139 and are connected to the contact conductive patterns 153 may be formed.

The formation of the landing pads LP may be accomplished by conformally depositing a barrier metal film 157 on the entire surface of the semiconductor substrate 100 and by depositing a metal film 159 on the barrier metal film 157 to fill the contact holes 145 Forming the mask patterns MP on the metal film 159 and forming the metal film 159 and the barrier metal film 157 using the mask patterns MP as an etching mask. And subsequently etching to form pad recess regions RR. Here, the metal film 159 completely fills the contact holes 145 and can completely cover the bit line structures BLS.

The pad recess region RR may have a bottom surface located below the top surface of the bit line structures BLS so that the landing pads LP can be separated from each other. Further, during formation of the pad recess region RR, a portion of the hard mask pattern 125, a portion of the second sacrificial spacers 137, and a portion of the third spacers 139 may be etched. That is, portions of the second sacrificial spacers 137 may be exposed between the landing pads LP by the pad recess region RR. The first portions 133a of the first sacrificial spacer 133 adjacent to the contact pad structures CPS may overlap the upper portion of the landing pad LP and may not be exposed by the pad recess region RR have.

Each of the landing pads LP may include a bottom filling the bottom region of the contact hole 145 and an upper portion extending to the top of the bit line structures BLS. The upper portions of the landing pads LP may have an elliptical shape in plan view and the elliptical landing pads LP may extend along the oblique direction with respect to the first and second directions D1 and D2, As shown in FIG. Since the landing pad LP has a long axis in the oblique direction with respect to the first and second directions D1 and D2 even if the long axis width of the landing pads LP increases in the process of forming the landing pads LP The process margin between the landing pads LP can be secured.

14A, 14B, and 14C, after forming the pad recess region RR, the first and second sacrificial spacers 133 and 137 are removed to form the first and second air gaps AG1 , AG2 may be formed. The first and second air gaps AG1 and AG2 are formed by using isotropic etching using the etch recipe having the etch selectivity for the first, second, and third spacers 131, 135, And then performing an etching process.

The first and second air gaps AG1 and AG2 may be formed by etching the first and second sacrificial spacers 133 and 137 by providing an etchant etchant to the pad recess region RR . That is, the etchant may be provided with a portion of the second sacrificial spacer 137 exposed in the pad recess region RR and the second portions 133b of the first sacrificial spacer 133. A part of the second sacrificial spacer 137 exposed in the pad recess region RR has a ring shape in plan view and is in direct contact with the first portions 133a of the first sacrificial spacer 133 Even if the first portions 133a of the first sacrificial spacers 133 are not exposed in the pad recess region RR, the wet etchant can be removed from the first sacrificial spacers 133 through the empty space from which the second sacrificial spacers 137 are removed, May be provided as the first portions 133a of the second housing 133. In other words, the portions of the first sacrificial spacer 133 (i.e., the first portions 133a adjacent to the contact pad structures CPS) that are obscured by the landing pad LP, The second sacrificial spacers 137 formed in the shape of a ring are removed, as well as the spaces in which the second portions 133b of the first sacrificial spacer 133 are removed.

As described above, by removing the first and second sacrificial spacers 133 and 137, the first air gap AG1 defined between the first and second spacers 131 and 135 (i.e., And a second air gap AG2 defined between the first spacer 131 and the third spacer 139 and between the insulating pattern and the third spacer 139 An empty space from which the spacer 137 is removed) can be formed. Here, the first air gap AG1 and the second air gap AG2 are connected to each other to form one empty space. Further, since the second sacrificial spacer 137 directly contacts the first sacrificial spacers 133 extending in the second direction D2 in one contact hole 145 and adjacent to each other, the second air gap AG2 May be connected to two first air gaps AG1 extending in the second direction D2.

Subsequently, after the first and second air gaps AG1 and AG2 are formed, as shown in Figs. 1A, 1B, and 1C, the first and second air gaps AG1 and AG2 are formed, 1 capping insulating film 161 and a second capping insulating film 163 that completely fills the pad recess region RR may be formed in order.

The first capping insulating film 161 may be deposited using a deposition method having poor step coverage so that the first capping insulating film 161 does not fill the second air gap AG2, 2 It is possible to block the inlet of the air gap AG2.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (20)

Word lines extending in a first direction on the semiconductor substrate;
Bit line structures extending in a second direction across the word lines, the bit line structures intersecting the first direction;
In a plan view, contact pad structures are provided between the word lines and between the bit line structures; And
And a spacer structure interposed between the bit line structures and the contact pad structures,
The spacer structure comprises:
A first air gap extending in the second direction along one side walls of the bit line structures; And
And a second air gap surrounding each of the contact pad structures and connected to the first air gap, in plan view. The method according to claim 1,
Each of the contact pad structures including a lower portion disposed between the bit line structures and an upper portion located on one of the bit line structures extending from the lower portion,
Wherein the second air gap surrounds the lower portion of the contact pad structure and a portion of the second air gap overlaps with the upper portion of the contact pad structure in plan view. The method according to claim 1,
And the second air gap has a smaller width than the first air gap. The method according to claim 1,
The first air gap including first regions adjacent to the contact pad structures and second regions between the contact pad structures,
Wherein a height of the first air gap is larger in the second regions than in the first regions. The method according to claim 1,
The spacer structure comprises:
First and second spacers extending in the second direction and adjacent to each other; And
And a third spacer disposed on the second spacer between the adjacent bit line structures and surrounding a portion of each of the contact pad structures,
Wherein the first air gap is provided between the first and second spacers, and the second air gap is provided between the first spacer and the third spacer. The method according to claim 1,
Further comprising insulating patterns disposed on the word lines and disposed, in plan view, between the contact pad structures and between the bit line structures,
The first air gap extending between the bit line structures and the contact pad structures and between the bit line structures and the insulation patterns,
Wherein the second air gap extends between the contact pad structures and the insulation patterns between the bit line structures and the contact pad structures. The method according to claim 6,
Each of the contact pad structures includes:
A contact conductive pattern in contact with the semiconductor substrate; And
A landing pad coupled to the contact conductive pattern and covering a portion of the spacer structure and a portion of the bit line structures,
The landing pad including a bit line structure, a bottom portion surrounded by the insulation patterns, and an upper portion covering a portion of the bit line structures,
And the second air gap surrounds the lower portion of the landing pad. 8. The method of claim 7,
And a pad insulation pattern filling between the landing pads,
Wherein the second air gap includes a first region overlapping with the landing pad and a second region overlapping with the pad insulating pattern in plan view. 9. The method of claim 8,
And the height of the second air gap is smaller in the second region than in the first region. Word lines extending in a first direction in the semiconductor substrate;
Bit line structures extending in a second direction across the word lines, the bit line structures intersecting the first direction;
In plan view, contact pad structures disposed between and between the bit line structures;
Insulator patterns disposed on the word lines and disposed between the contact pad structures and between the bit line structures in plan view; And
And a spacer structure disposed between the bit line structures and the contact pad structures,
The spacer structure comprises:
First and second spacers extending between the bit line structures and the insulation patterns between the bit line structures and the contact pad structures;
A first air gap provided between the first and second spacers and extending in the second direction; And
And a second air gap extending along the first direction between the insulation patterns and the contact pad structures from the first air gap. 11. The method of claim 10,
And the second air gap has a smaller width than the first air gap. 11. The method of claim 10,
The first air gap including first regions adjacent to the contact pad structures and second regions between the contact pad structures,
Wherein a height of the first air gap is larger in the second regions than in the first regions. 11. The method of claim 10,
The spacer structure further comprising a third spacer disposed on the second spacer between the bit line structures and surrounding a portion of each of the respective contact pad structures,
And the second air gap is provided between the first spacer and the third spacer and between the insulating patterns and the third spacer. 11. The method of claim 10,
Each of the contact pad structures includes:
A contact conductive pattern in contact with the semiconductor substrate; And
A landing pad coupled to the contact conductive pattern and covering a portion of the spacer structure and a portion of the bit line structures,
The landing pad including a bit line structure, a bottom portion surrounded by the insulation patterns, and an upper portion covering a portion of the bit line structures,
And the second air gap surrounds the lower portion of the landing pad. 15. The method of claim 14,
Further comprising a pad isolation pattern to fill between the landing pads of the contact pad structures,
Wherein the second air gap includes a first region overlapping with the landing pad and a second region overlapping with the pad insulating pattern in plan view. 16. The method of claim 15,
And an upper surface of the second spacer adjacent to the contact pad structures is spaced apart from a lower surface of the pad insulating pattern. First and second bit line structures extending in a first direction on a semiconductor substrate, each of the first and second bit line structures having first and second sidewalls facing each other;
Contact pad structures spaced apart from each other in the first direction between the first and second bit line structures;
A first spacer structure comprising a first air gap extending along the first sidewall of the first bit line structure;
A second spacer structure including a second air gap extending along the second sidewall of the second bit line structure; And
A third spacer structure surrounding the contact pad structures and including a third air gap connecting the first air gap and the second air gap. 18. The method of claim 17,
Wherein the first spacer structure comprises first and second spacers extending along the first sidewall of the first bit line structure, the first air gap being provided between the first and second spacers,
Wherein the second spacer structure comprises third and fourth spacers extending along the second sidewall of the second bit line structure and the second air gap is provided between the third and fourth spacers,
Wherein each of the second and fourth spacers includes first portions adjacent to the contact pad structures and second portions between the first portions, the height of the first portion being less than the height of the second portion Semiconductor memory device. 19. The method of claim 18,
And the third spacer structure is disposed on the first portions of the second and fourth spacers to surround a portion of the contact pad structures. 18. The method of claim 17,
Each of the contact pad structures including a lower portion disposed between the first and second bit line structures and an upper portion located on one of the bit line structures extending from the lower portion,
Wherein the third word gap surrounds the lower portion of each of the contact pad structures and wherein a portion of the third air gap overlaps the top portion of each of the contact pad structures in plan view.

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