CN110957318A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN110957318A CN110957318A CN201811122777.XA CN201811122777A CN110957318A CN 110957318 A CN110957318 A CN 110957318A CN 201811122777 A CN201811122777 A CN 201811122777A CN 110957318 A CN110957318 A CN 110957318A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims description 53
- 238000005530 etching Methods 0.000 claims description 44
- 230000008569 process Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 125000004437 phosphorous atom Chemical group 0.000 claims description 3
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 230000006870 function Effects 0.000 description 25
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, an isolation groove, a plurality of word line grooves, a grid and a conducting layer, wherein the isolation groove is formed in the substrate to define a plurality of active areas in the substrate, and the lower part of the isolation groove is sequentially filled with a first dielectric layer and a second dielectric layer; a plurality of word line grooves are formed in the substrate, and each word line groove comprises a grid groove passing through the active region, a conductive groove passing through the isolation groove and micro grooves which are positioned on two sides of the bottom of the conductive groove and are communicated with the conductive grooves; the grid is formed in the grid groove; the conductive layer is formed on the upper part of the isolation trench and fills the micro-trench. The width of the conductive groove is increased by the conductive layer filled in the micro groove, and the conductive layer of the micro groove is connected with the conductive layer of the grid electrode to form a conductive area. The invention ensures the increase of the width of the conducting channel without increasing the size of the transistor, and is beneficial to improving the driving current and the conducting current of the access transistor.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to a semiconductor structure and a manufacturing method thereof.
Background
In the current semiconductor industry, memory devices represent a large percentage of integrated circuit products. The memory typically includes a plurality of memory cells, such as access transistors.
With the continuous development of semiconductor technology, the integration level of semiconductor devices is higher and higher, the sizes of corresponding elements are smaller and smaller, and the width of a conductive channel of an access transistor is reduced, so that the driving current and the conducting current of the access transistor are reduced. The magnitude of the drive current and the conduction current of the conduction channel has a direct effect on the performance of the access transistor. When the driving current and the on-current are reduced, the data access speed is reduced, and the performance of the memory is affected.
Therefore, it is very critical to increase the driving current and the on-state current of the access transistor with higher and higher integration.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor structure and a method for fabricating the same, which can solve the problem of the prior art that the driving current and the on-current of the access transistor are reduced.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a substrate, and defining a plurality of active regions and isolation regions positioned at the periphery of the active regions on the substrate;
forming an isolation groove in the substrate, and sequentially forming a first dielectric layer and a second dielectric layer in the isolation groove, wherein the position of the isolation groove corresponds to the position of the isolation region;
forming a plurality of word line grooves in the active region and the isolation groove, wherein the word line grooves comprise a gate groove penetrating through the active region, a conductive groove penetrating through the isolation groove and micro grooves which are positioned at two sides of the bottom of the conductive groove and are communicated with the conductive groove;
and sequentially forming a gate dielectric layer, a work function layer and a gate electrode layer in the word line groove, wherein the gate dielectric layer, the work function layer and the gate electrode layer are all filled in the micro groove.
Optionally, the method for manufacturing the semiconductor structure further includes the following steps:
after the first dielectric layer and the second dielectric layer are formed, forming a well region in the substrate, wherein the depth of the well region is greater than that of the micro groove;
forming a source electrode doped region and a drain electrode doped region in the active region after the word line trench is filled with the gate dielectric layer, the work function layer and the gate electrode layer, wherein the source electrode doped region and the drain electrode doped region are respectively positioned at two sides of the gate trench;
and back-etching the gate electrode material in the gate trench to make the gate electrode layer lower than the substrate surface corresponding to the source doped region and the drain doped region, wherein the gate electrode layer protrudes out of the work function layer.
Optionally, the gate dielectric layer, the work function layer and the gate electrode layer in the gate trench together form a gate, and the source doped region and the drain doped region are at least partially overlapped with the gate in the height direction.
Optionally, the depth of the source doped region and the drain doped region is less than the depth of the well region.
Optionally, forming the isolation trench in the substrate comprises:
sequentially forming a pad oxide layer and a pad nitride layer on the surface of the substrate;
forming a patterned hard mask layer on the substrate to cover the active region and expose the substrate of the isolation region;
carrying out dry etching on the substrate by taking the patterned hard mask layer as a mask to obtain the isolation trench;
and removing the hard mask layer.
Optionally, the forming the first dielectric layer and the second dielectric layer in the isolation trench includes:
forming the first dielectric layer on the side wall and the bottom of the isolation trench structure;
forming the second dielectric layer on the first dielectric layer until the isolation groove is filled, and carrying out annealing treatment;
removing the dielectric layer on the top surface of the substrate by using a planarization process;
optionally, the thickness of the first dielectric layer is 10% to 40% of the width of the isolation trench.
Optionally, the first dielectric layer includes borophosphosilicate glass, and the second dielectric layer includes silicon oxide.
Optionally, the number of B and P atoms in the borophosphosilicate glass each account for 4%.
Optionally, the forming the word line trench includes the steps of:
forming a patterned mask layer on the substrate with the isolation groove to expose the word line groove area;
forming the conductive trench, the micro-trench, and the gate trench in the substrate;
optionally, the etching selection ratio of the first dielectric layer to the second dielectric layer is greater than 1, and the micro-groove is formed by self-alignment of a one-step etching process.
Optionally, at a position where the isolation trench is penetrated by the word line trench, the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer, the top surface of the second dielectric layer is lower than the top surface of the substrate, and at a position where the isolation trench is not penetrated by the word line trench, the top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.
Optionally, the depth of the micro groove is 3% -40% of the depth of the conductive groove.
Optionally, a top surface of the work function layer located in the gate trench is lower than a top surface of the gate electrode layer located in the gate trench.
The present invention also provides a semiconductor structure comprising:
a substrate;
the isolation trench is formed in the substrate to define a plurality of active regions in the substrate, and a first dielectric layer and a second dielectric layer are sequentially filled at the lower part of the isolation trench;
a plurality of word line trenches formed in the active region and the isolation trench, the word line trenches including a gate trench passing through the active region, a conductive trench passing through the isolation trench, and micro trenches located at both sides of a bottom of the conductive trench and communicating with the conductive trench;
a gate formed in the gate trench;
and the conductive layer is formed on the upper part of the isolation groove and is filled into the micro groove.
Optionally, an etching selection ratio of the first dielectric layer to the second dielectric layer is greater than 1.
Optionally, the material of the first dielectric layer includes borophosphosilicate glass, the material of the second dielectric layer includes silicon oxide,
optionally, the first dielectric layer is formed on the sidewall and the bottom of the isolation trench, and the second dielectric layer is formed above the first dielectric layer.
Optionally, at a position where the isolation trench is penetrated by the word line trench, the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer, the top surface of the second dielectric layer is lower than the top surface of the substrate, and at a position where the isolation trench is not penetrated by the word line trench, the top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.
Optionally, the thickness of the first dielectric layer is 10% to 40% of the width of the isolation trench.
Optionally, the micro trench is defined by the substrate, the first dielectric layer and the second dielectric layer, and the depth of the micro trench is 3% -40% of the depth of the conductive trench. .
Optionally, the semiconductor structure further includes a source doped region and a drain doped region, where the source doped region and the drain doped region are located on two sides of the gate trench.
Optionally, the top surface of the gate is lower than the substrate surfaces corresponding to the source doped region and the drain doped region.
Optionally, the gate includes a gate dielectric layer, a work function layer, and a gate electrode layer from bottom to top, and the gate dielectric layer, the work function layer, and the gate electrode layer are all filled in the micro trench.
Optionally, an etching selection ratio of the work function layer to the gate electrode layer is greater than 1, and a top surface of the work function layer is lower than a top surface of the gate electrode layer.
As described above, the semiconductor structure and the manufacturing method thereof of the present invention have the following advantages: in the process of forming the semiconductor structure, the micro-groove formed in the isolation region close to the active region can form a conductive region after the conductive layer connected with the grid electrode is filled subsequently, so that the width of the conductive channel is further increased, and the driving current and the conducting current of the access transistor are favorably improved. In the process of forming the semiconductor structure, the used first dielectric layer BPSG is softer than the second dielectric layer oxide layer, so that the etching selection ratio of the first dielectric layer BPSG to the second dielectric layer silicon dioxide is larger than 1, and a micro-groove attached to the silicon substrate of the active region is formed in a self-alignment manner by only using one etching process, thereby reducing the production cost. In the process of forming the semiconductor structure, the high-temperature annealing treatment is carried out after the isolation trench oxide layer is formed, so that the density of the dielectric material can be improved, and the mechanical strength of the first dielectric layer and the second dielectric layer can be increased. After the isolation trench is filled with the medium, the pad oxide layer and the pad nitride layer on the surface are removed, so that the subsequent injection difficulty is reduced. According to the invention, the etching selection ratio of the work function layer to the grid electrode layer is larger than 1 by adjusting the etching agent, so that the grid electrode layer protrudes out of the work function layer after back etching, and the contact area of the grid electrode layer is favorably increased.
Drawings
Fig. 1 is a plan view of the active area and isolation area of the semiconductor structure of the present invention.
Fig. 2 is a cross-sectional view of the isolation trench along the XX' direction after the step of forming the isolation trench in the substrate according to the method for manufacturing the semiconductor structure of the invention.
Fig. 3 is a cross-sectional view of the isolation trench along the YY' direction after the step of forming the isolation trench in the substrate according to the method for fabricating the semiconductor structure of the present invention.
Fig. 4 is a cross-sectional structure view along the XX' direction after the isolation trench is filled with the first dielectric layer and the second dielectric layer in the method for manufacturing the semiconductor structure of the invention.
Fig. 5 is a cross-sectional view of the isolation trench in the YY' direction after the isolation trench is filled with the first dielectric layer and the second dielectric layer in the method for fabricating the semiconductor structure of the present invention.
Fig. 6 is a plan view of a semiconductor structure after word line trenches are formed in a method of fabricating the semiconductor structure according to the present invention.
FIG. 7 is a cross-sectional view along XX' after forming a word line trench in the method for fabricating a semiconductor structure of the present invention.
Fig. 8 is an enlarged view of a portion of the semiconductor structure of fig. 7 in accordance with the present invention.
FIG. 9 is a cross-sectional view taken along the YY' direction after the step of forming a word line trench in the method for fabricating a semiconductor structure according to the present invention.
Fig. 10 is a plan view of a semiconductor structure of the present invention after filling the word line trench.
Fig. 11 is a cross-sectional structure view along the XX' direction after the steps of filling the gate dielectric layer, the work function layer and the gate electrode layer in the word line trench in the method for manufacturing the semiconductor structure of the present invention.
Fig. 12 is an enlarged view of a portion of the semiconductor structure of the present invention shown in fig. 11.
Fig. 13 is a cross-sectional structure view along the YY' direction after the step of filling the word line trench with the gate dielectric layer, the work function layer, and the gate electrode layer in the method for fabricating a semiconductor structure according to the present invention.
FIG. 14 is a cross-sectional view along the AA' direction after the gate electrode material is etched back in the method for fabricating a semiconductor structure according to the present invention.
Description of the element reference numerals
1 substrate
10 active region
101 source doped region
102 doped drain region
103 grid
1031 gate dielectric layer
1032 work function layer
1033 Gate electrode layer
20 isolation region
201 isolation trench
202a first dielectric material
202b second dielectric material
30 well region
40 word line trench
401 gate trench
402 conductive trench
403 micro-groove
50 conductive layer
60 word line
Z1 isolation trench depth
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 14, the present invention provides a semiconductor structure comprising: the semiconductor device comprises a substrate 1, an isolation trench 201, a plurality of word line trenches 40, a gate 103 and a conductive layer 50, wherein the isolation trench 201 is formed in the substrate 1 to define a plurality of active regions 10 in the substrate 1, and a first dielectric layer 202a and a second dielectric layer 202b are sequentially filled at the lower part of the isolation trench 201; a plurality of word line trenches 40 are formed in the active region 10 and the isolation trench 201, the word line trenches 40 including a gate trench 401 passing through the active region 10, a conductive trench 402 passing through the isolation trench 201, and micro trenches 403 located at both sides of the bottom of the conductive trench 402 and communicating with the conductive trench 402; the gate 103 is formed in the gate trench 401; the conductive layer 50 is formed on the upper portion of the isolation trench 201 and filled into the micro trench 403.
Specifically, a plurality of active regions 10 are arranged in an array form, a plurality of isolation regions 20 are defined, and the active regions 10 are isolated by the isolation regions 20, so that mutual influence between the active regions 10 is avoided. Further, a gate 103, a source doped region 101 and a drain doped region 102 are included in the active region 10. The source doped region 101 and the drain doped region 102 are respectively located at two sides of the gate 103.
The isolation trench 201 is formed in the isolation region 20 in the substrate 1, the bottom and the sidewall of the lower half region of the isolation trench 201 located in the word line trench 40 are filled with a first dielectric layer 202a, and a second dielectric layer 202b is filled above the first dielectric layer 202 a. The etching selection ratio of the first dielectric layer 202a to the second dielectric layer 202b is greater than 1, the top surface of the first dielectric material 202a is lower than the top surface of the second dielectric material 202b, and a micro-trench 403 is formed between the portion of the second dielectric material 202b higher than the first dielectric material 202a and one sidewall of the gate 103 on the active region 10. The whole area of the isolation trench 201 outside the word line trench 40 is sequentially filled with a first dielectric layer 202a and a second dielectric layer 202b from bottom to top, and the first dielectric layer 202a and the second dielectric layer 202b are flush.
The semiconductor structure further comprises a plurality of word line trenches 40, wherein the word line trenches 40 comprise a gate trench 401 penetrating through the active region 10, a conductive trench 402 penetrating through the isolation trench 201, and micro trenches 403 located at two sides of the bottom of the conductive trench 402 and communicated with the conductive trench 402. The word line trenches 40 are arranged at an angle to the active regions 10, which is beneficial to increase the number of active regions 10 on the word line trenches 40, thereby improving the integration level of the semiconductor structure.
Specifically, the first dielectric layer 202a is formed on the sidewall and the bottom of the isolation trench 201, the thickness of the first dielectric layer 202a is 10% -40% of the width of the isolation trench 201, the second dielectric layer 202b is formed on the first dielectric layer 202a, and the isolation trench 201 is filled with the first dielectric layer 202a and the second dielectric layer 202b together. In this embodiment, the first dielectric layer 202a and the second dielectric layer 202b respectively include, but are not limited to, borophosphosilicate glass (BPSG) and silicon oxide, which is beneficial to reducing the influence of the stress between the first dielectric layer 202a and the second dielectric layer 202b on the device, and the etching rates of the two dielectric layers are different, the etching rate of the first dielectric layer 202a is greater than the etching rate of the second dielectric layer 202b, that is, the etching selectivity of the first dielectric layer 202a to the second dielectric layer 202b is greater than 1, so that the micro-trench 403 attached to the active area substrate 1 is formed by self-aligning only one etching process. Boron Phosphorus Silicon Glass (BPSG) and silicon oxide are respectively used as the materials of the first dielectric layer 202a and the second dielectric layer 202b, so that the problems of mechanical reliability and electrical performance of a device caused by the fact that silicon nitride with harder material and large residual stress is used are solved, and the capability of solving the problem of reduction of the driving current and the conduction current of a transistor is improved. In addition, the depth of the micro-groove 403 can be adjusted by adjusting the material selection of the first dielectric layer 202a and the second dielectric layer 202b, and by adjusting the thickness of the first dielectric layer and the second dielectric layer.
The gate 103 is located in the gate trench 401 in the word line trench 40, and includes the gate dielectric layer 1031, the work function layer 1032, and the gate electrode layer 1033. The etching selection ratio of the work function layer 1032 to the gate electrode layer 1033 is greater than 1, and the top surface of the work function layer 1032 in the finally obtained gate trench 401 is lower than the top surface of the gate electrode layer 1033, which is favorable for improving the contact area of the gate electrode layer. The top surface of the gate 103 is lower than the surface of the substrate 1 corresponding to the source doped region 101 and the drain doped region 102.
Specifically, the gate dielectric layer 1031 is made of, but not limited to, silicon dioxide, the work function 1032 is made of, but not limited to, titanium nitride, and the gate electrode layer 1033 is made of, but not limited to, tungsten.
The conductive layer 50 is located in the conductive trench 402 in the word line trench 40, and the conductive layer 50 is also filled in the micro-trench 403, i.e. the gate electrode layer 1033 in the micro-trench 403 is connected to the conductive layer 50 above the conductive trench 402 in the word line trench 40, thereby increasing the width of the conductive channel of the access transistor in the height direction. When the access transistor is turned on, the increase of the width of the conductive trench 402 caused by the micro trench 403 is beneficial to increase the driving current and the on-current of the access transistor, thereby effectively improving the performance of the access transistor without changing the size of the access transistor.
The depth of the micro-trench 403 is 3% to 40% of the depth of the conductive trench 402, and specifically, may be adjusted according to the actually formed semiconductor structure.
By way of example, the conductive layer 50 includes, but is not limited to, tungsten (W).
When the access transistor is turned on, a first conductive region in the horizontal direction is formed in the substrate 1 below the gate 103, and a second conductive region in the depth direction is formed in the substrate 1 at one side of the conductive trench 402 and the micro-trench 403 to constitute a conductive channel of the access transistor, and the lowest point in the depth direction of the conductive trench 402 is higher than the lowest point of the isolation trench 201, which will have an insulating isolation using a conductive region and a non-conductive region, and in particular, the isolation trench depth Z1 can be adjusted according to the actually formed semiconductor structure.
In the semiconductor structure, the micro groove is formed at the bottom of the isolation groove close to the active region, and the micro groove forms a conductive region after a conductive layer connected with the grid electrode is filled subsequently, so that the width of the conductive channel is further increased, the driving current and the conducting current of the access transistor are improved, and the problem of reduction of the driving current and the conducting current of the access transistor in the prior art is solved.
Example two
The present invention also provides a method of fabricating the above semiconductor structure, comprising the steps of:
referring to fig. 1, step S1 is executed: a substrate 1 is provided on which a plurality of active regions 10 for forming access transistors and isolation regions 20 located at the periphery of the active regions are defined. As an example, an etching barrier layer is formed on the substrate 1 by using a Chemical Vapor Deposition (CVD) method or other deposition methods, in this embodiment, the etching barrier layer may be formed by depositing a pad oxide layer first and then depositing a pad nitride layer, and the pad nitride layer may prevent over-etching in subsequent etching process steps and may protect the substrate 1.
Then, referring to fig. 2-5, step S2 is executed: forming an isolation trench 201 in the substrate 1, and sequentially forming a first dielectric layer 202a and a second dielectric layer 202b in the isolation trench 201, where the position of the isolation trench 201 corresponds to the position of the isolation region 20.
In the present embodiment, please refer to fig. 2-3, step S2-1 is executed: a pad oxide layer and a pad nitride layer (not shown) are deposited on the surface of the substrate 1, then a patterned hard mask layer is formed on the surface on which the pad oxide layer and the pad nitride layer are deposited, the patterned hard mask layer covers the active region 10 and exposes the isolation region 20, then an isolation trench 201 is formed in the isolation region 20 by adopting an etching process, and finally the hard mask layer is removed. Fig. 2 is a cross-sectional structure view along the XX' direction after the step of forming the isolation trench 201 in the substrate 1. Fig. 3 is a cross-sectional view along the YY' direction after the step of forming the isolation trench 201 in the substrate 1.
Referring to fig. 4-5, step S2-2 is executed: the first dielectric layer 202a and the second dielectric layer 202b are formed in the off-trench 201, and the etching selection ratio of the first dielectric layer 202a to the second dielectric layer 202b is greater than 1, so that the micro-trench 403 can be conveniently formed in a self-aligned manner by adopting a one-step etching process in a subsequent process. Fig. 4 is a cross-sectional structure view along the XX' direction after the isolation trench 201 is filled with the first dielectric layer 202a and the second dielectric layer 202 b. Fig. 5 is a cross-sectional structure view along the XX' direction after the isolation trench 201 is filled with the first dielectric layer 202a and the second dielectric layer 202 b.
Specifically, in this embodiment, a first dielectric layer 202a is formed on the sidewall and the bottom of the isolation trench 201 by using a Chemical Vapor Deposition (CVD) method or other deposition techniques, then a second dielectric layer 202b is deposited on the first dielectric layer 202a and fills the isolation trench 201 by using the Chemical Vapor Deposition (CVD) method or other deposition techniques, and then the substrate 1 on which the second dielectric layer 202b is deposited is subjected to high-temperature annealing, so that not only can the density of the dielectric material be improved, but also the mechanical strength of the first dielectric layer 202a and the second dielectric layer 202b can be increased. Then, a planarization process is performed, specifically, in this embodiment, a chemical mechanical polishing method may be used to perform a planarization process on the substrate 1 on which the first dielectric layer 202a and the second dielectric layer 202b are deposited until the pad nitride layer is formed, and remove the excess first dielectric layer 202a and the excess second dielectric layer 202 b. And then removing the pad oxide layer and the pad nitride layer, thereby reducing the difficulty of the subsequent injection process.
Specifically, the material of the first dielectric layer 202a includes, but is not limited to, borophosphosilicate glass (BPSG), the material of the second dielectric layer includes, but is not limited to, silicon oxide, and the borophosphosilicate glass (BPSG) is softer than the silicon oxide.
Specifically, the thickness of the borophosphosilicate glass (BPSG) is 10% to 40% of the width of the isolation trench 201.
In this embodiment, the numbers of B and P atoms in the borophosphosilicate glass (BPSG) each account for 4%.
Step S3 is then executed: a well region 30 is formed in the substrate 1, and the depth of the well region 30 is greater than the depth of the micro-trench 403. Specifically, the well region 30 is formed by implanting impurities into the substrate 1 through an ion implantation process.
Referring next to fig. 6-9, step S4 is performed: forming a plurality of word line trenches 40 in the active region 10 and the isolation trench 201, wherein the word line trenches 40 include a gate trench 401 passing through the active region, a conductive trench 402 passing through the isolation trench 201, and micro trenches 403 located at both sides of the bottom of the conductive trench 402 and communicating with the conductive trench 402.
Referring to fig. 7, in the present embodiment, step S4 is executed: forming a patterned mask layer on the substrate 1 having the isolation trench 201 to expose the word line trench 40 region, and then forming the conductive trench 402, the micro trench 403, and the gate trench 401 in the substrate 1.
A patterned mask layer (not shown) is formed on the substrate 1 having the isolation trench 201 to expose the conductive word line trench 40, and the conductive trench 402 and the micro-trench 403 are formed on the substrate 1 having the word line pattern in a self-aligned manner by a one-step etching process. Specifically, the conductive trench 402 and the micro-trench 403 are obtained by etching the isolation trench 201 filled with the first dielectric layer BPSG and the second dielectric layer silicon oxide in the word line pattern region by a one-step method, and since the BPSG is softer than the silicon oxide, when etching is performed by an etching process, the etching selection ratio of the first dielectric layer 202a to the second dielectric layer 202b is greater than 1, that is, the first dielectric layer BPSG has a faster etching rate than the second dielectric layer silicon oxide, so that when an etching end point is reached, the top surface of the second dielectric layer is higher than the top surface of the first dielectric layer. The groove is formed by the first dielectric layer 202a, the second dielectric layer 202b and the substrate 1 below the gate groove 401 to form a groove structure, which is a micro groove 403, that is, the micro groove 403 is located at the bottom of the conductive groove 402, is communicated with the conductive groove 402, and is tightly attached to the substrate 1 below the gate groove. The gate trench 401 is also obtained by an etching process. The conductive trench 402, the micro trench 403 and the gate trench 401 may be simultaneously obtained by a one-step etching process or may be obtained by a step-by-step etching process.
Referring to fig. 9, in particular, at a position where the isolation trench 201 is not penetrated by the word line trench 40, a top surface of the second dielectric layer 202b is flush with a top surface of the first dielectric layer 202 a.
Specifically, the depth of the micro trench 403 is 3% to 40% of the depth of the conductive trench 402, and is smaller than the doping depth of the impurity when the well region 30 is formed.
Referring next to fig. 10-13, step S5 is performed: a gate dielectric layer 1031, a work function layer 1032 and a gate electrode layer 1033 are sequentially formed in the word line trench 40.
Specifically, an atomic deposition method, a chemical vapor deposition method, and a thermal oxidation process are used to form a gate dielectric layer 1031 on the sidewall and the bottom of the word line trench 40. Then, an atomic deposition method or a chemical vapor deposition method is used to form the work function layer 1032, and finally, the gate electrode layer 1033 is filled, and then the filled word line 60 is subjected to a planarization process, so that the heights of the word line materials filled in the word line trenches 40 are consistent or nearly consistent. The gate electrode layer 1033 located above the isolation region 20 in the word line trench 40 is a conductive layer 50. In this step, the micro trench 403 is also filled with the gate dielectric layer 1031, the work function layer 1032 and the gate electrode layer 1033, so that a conductive region is formed at the overlapping portion of the micro trench 403 and the active region 10, that is, the width of the conductive trench 402 is increased, which is beneficial to improving the driving current and the on-state current of the transistor.
By way of example, the gate dielectric layer 1031 includes, but is not limited to, silicon dioxide, the work function layer 1032 includes, but is not limited to, titanium nitride, and the gate electrode layer 1033 includes, but is not limited to, tungsten.
Step S6 (not shown) is executed, the gate dielectric layer 1031 on the surface of the silicon substrate 1 is removed, a pad oxide layer is formed, then the source doped region 101 and the drain doped region 102 are formed in the well region 30 in the active region 10, the source doped region 101 and the drain doped region 102 are respectively located at two sides of the gate trench 401, the depth of the formed source doped region 101 and the drain doped region 102 is smaller than that of the well region 30, and at least a part of the formed source doped region 101 and the formed drain doped region 102 is overlapped with the gate 103 in the height direction to ensure the performance of the transistor.
Finally, referring to fig. 14, step S7 is executed: and etching the gate electrode material in the gate trench 401 by using a back etching technology, so that the gate electrode layer 1033 is lower than the surface of the substrate 1 corresponding to the source doped region 101 and the drain doped region 102. By adjusting the etchant, the etching selection ratio of the work function layer 1032 to the gate electrode layer 1033 is greater than 1, so that the gate electrode layer 1033 protrudes out of the work function layer 1032 after etching back, which is beneficial to increasing the contact area of the gate electrode layer 1033.
The manufacturing method of the semiconductor structure can form the micro-groove attached to the silicon substrate of the active area in a self-alignment way through an etching process, is convenient for manufacturing the access transistor with the width of the conductive channel increased without increasing the size of a device, and improves the driving current and the conducting current of the access transistor.
In summary, in the semiconductor structure of the present invention, the micro trench is formed at the bottom of the isolation trench close to the active region, and the micro trench forms a conductive region after the conductive layer connected to the gate is subsequently filled, so as to further increase the width of the conductive channel, which is beneficial to improving the driving current and the on-state current of the access transistor, and solve the problem of reducing the driving current and the on-state current of the access transistor in the prior art. The manufacturing method of the semiconductor structure can form the micro-groove attached to the silicon substrate of the active area in a self-alignment way through an etching process, is convenient for manufacturing the access transistor with the width of the conductive channel increased without increasing the size of a device, and improves the driving current and the conducting current of the access transistor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A method for manufacturing a semiconductor structure is characterized by comprising the following steps:
providing a substrate, and defining a plurality of active regions and isolation regions positioned at the periphery of the active regions on the substrate;
forming an isolation groove in the substrate, and sequentially forming a first dielectric layer and a second dielectric layer in the isolation groove, wherein the position of the isolation groove corresponds to the position of the isolation region;
forming a plurality of word line grooves in the active region and the isolation groove, wherein the word line grooves comprise a gate groove penetrating through the active region, a conductive groove penetrating through the isolation groove and micro grooves which are positioned at two sides of the bottom of the conductive groove and are communicated with the conductive groove;
and sequentially forming a gate dielectric layer, a work function layer and a gate electrode layer in the word line groove, wherein the gate dielectric layer, the work function layer and the gate electrode layer are all filled in the micro groove.
2. The method of claim 1, further comprising:
after the first dielectric layer and the second dielectric layer are formed, forming a well region in the substrate, wherein the depth of the well region is greater than that of the micro groove;
forming a source electrode doped region and a drain electrode doped region in the active region after the word line trench is filled with the gate dielectric layer, the work function layer and the gate electrode layer, wherein the source electrode doped region and the drain electrode doped region are respectively positioned at two sides of the gate trench;
and back-etching the gate electrode material in the gate trench to make the gate electrode layer lower than the substrate surface corresponding to the source doped region and the drain doped region, wherein the gate electrode layer protrudes out of the work function layer.
3. The method of claim 1, wherein sequentially forming the first dielectric layer and the second dielectric layer in the isolation trench comprises:
forming the first dielectric layer on the side wall and the bottom of the isolation trench structure;
forming the second dielectric layer on the first dielectric layer until the isolation groove is filled, and carrying out annealing treatment;
removing the dielectric layer on the top surface of the substrate by using a planarization process;
4. the method of claim 1, wherein: the thickness of the first dielectric layer is 10% -40% of the width of the isolation trench.
5. The method of claim 1, wherein: the first dielectric layer comprises borophosphosilicate glass, and the second dielectric layer comprises silicon oxide.
6. The method of claim 5, wherein: the numbers of B and P atoms in the boron-phosphorus-silicon glass respectively account for 4 percent.
7. The method of claim 1, wherein: and the etching selection ratio of the first dielectric layer to the second dielectric layer is more than 1, and the micro-groove is formed by self-alignment by adopting a one-step etching process.
8. The method of claim 1, wherein: the depth of the micro groove is 3% -40% of the depth of the conductive groove.
9. A semiconductor structure, comprising:
a substrate;
the isolation trench is formed in the substrate to define a plurality of active regions in the substrate, and a first dielectric layer and a second dielectric layer are sequentially filled at the lower part of the isolation trench;
a plurality of word line trenches formed in the active region and the isolation trench, the word line trenches including a gate trench passing through the active region, a conductive trench passing through the isolation trench, and micro trenches located at both sides of a bottom of the conductive trench and communicating with the conductive trench;
a gate formed in the gate trench;
and the conductive layer is formed on the upper part of the isolation groove and is filled into the micro groove.
10. The semiconductor structure of claim 9, wherein: and the etching selection ratio of the first dielectric layer to the second dielectric layer is more than 1.
11. The semiconductor structure of claim 9, wherein: the first dielectric layer comprises borophosphosilicate glass, and the second dielectric layer comprises silicon oxide.
12. The semiconductor structure of claim 9, wherein: the first dielectric layer is positioned on the side wall and the bottom of the isolation groove, and the second dielectric layer is formed above the first dielectric layer.
13. The semiconductor structure of claim 9, wherein: and at the position where the isolation trench is penetrated by the word line trench, the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer, the top surface of the first dielectric layer is lower than the top surface of the substrate, and at the position where the isolation trench is not penetrated by the word line trench, the top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.
14. The semiconductor structure of claim 9, wherein: the thickness of the first dielectric layer is 10% -40% of the width of the isolation groove.
15. The semiconductor structure of claim 9, wherein: the micro groove is formed by limiting the substrate, the first dielectric layer and the second dielectric layer, and the depth of the micro groove is 3% -40% of that of the conductive groove.
16. The semiconductor structure of claim 9, wherein: the grid electrode comprises a grid dielectric layer, a work function layer and a grid electrode layer from bottom to top, and the grid dielectric layer, the work function layer and the grid electrode layer are all filled in the micro-groove.
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