KR20140046526A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate, edge active pillars which protrude from the upper surface of the semiconductor substrate in a vertical direction, a center active pillar between the edge active pillars, a burying word lines which are arranged between the center active pillar and the edge active pillars, and a burying bit line which is arranged in the center active pillar and arranged in a diagonal direction to the burying word lines. The upper surface of the burying bit line is lower than the upper surface of the center active pillar. The lower surface of the burying bit line is higher than the upper surface of the burying word lines.

Description

Semiconductor device and method of fabricating same

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a vertical channel transistor and a manufacturing method thereof.

In the semiconductor industry, transistors, bit lines, and the like are formed by various manufacturing techniques. One such fabrication technique is to form a MOS field effect transistor with a horizontal channel. 2. Description of the Related Art As the design rule of a semiconductor device is reduced, a manufacturing technique is being developed in a direction of improving the degree of integration of a semiconductor device and improving an operation speed and a yield. A transistor having a vertical channel has been proposed to enlarge the integration degree, resistance, current driving ability, and the like of a transistor having a conventional horizontal channel.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having improved electrical characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device with improved electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, edge active pillars protruding in a vertical direction from an upper surface of the semiconductor substrate, and a central active pillars between the edge active pillars, the central active pillars and the edge active pillars And a buried bit line disposed in the central active column and disposed diagonally with respect to the buried word lines, wherein an upper surface of the buried bit line is greater than an upper surface of the central active column And the lower surface of the buried bit line is disposed above the upper surface of the buried word lines.

First impurity regions disposed in the edge active columns on the buried word lines and a second impurity region disposed in the central active column between a bottom surface of the buried bit line and an upper surface of the buried word lines .

Spacers covering the sidewalls of the buried bit line, and an isolation pattern disposed on the buried bit line in the central active column.

A gate insulating layer covering the central active column and the edge active columns, and a buffer insulating pattern covering the gate insulating layer and disposed on the upper surface of the buried word lines. Capacitors disposed on the edge active pillars, and contact plugs disposed between the edge active pillars and the capacitors.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes forming device isolation layers defining active portions in a semiconductor substrate, forming word line trenches across the active portions to form active columns protruding from the semiconductor substrate Forming buried word lines to fill a lower portion of the word line trenches by placing a gate insulating layer on an inner wall of the word line trenches, forming active word lines between the buried word lines with respect to the buried word lines Forming a bit line trench extending in a diagonal direction; forming a buried bit line to fill a bottom portion of the bit line trench, wherein a bottom surface of the bit line trenches is disposed above a bottom surface of the word line trenches .

After forming the wordline trenches, the method may further comprise forming impurity regions in the active pillars.

After forming the bit line trenches, forming contact plugs on the edge active pillars, and forming capacitors on the contact plugs.

The method may further include forming spacers to cover the sidewalls of the bit line trenches before forming the bit line trenches.

And after forming the buried word lines, forming buried insulation patterns filling between the active columns.

According to an embodiment of the present invention, in a semiconductor device in which a buried word line and a buried bit line are embedded in an active column, the buried word line may be formed to be disposed below the buried bit line. Thus, the channel region of the vertical channel transistor can be prevented from being electrically floated. Therefore, a semiconductor device with improved electrical characteristics can be provided.

1 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
2A to 8A are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figs. 2B to 8B and 6C are cross-sectional views taken along the AA 'direction in Figs. 2A to 8A.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1 is a perspective view showing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device 10 includes a vertical channel transistor. The semiconductor substrate 100 may include a central active column 120a protruding in the Z axis direction and edge active columns 120b spaced apart from both sides of the central active column 120a. The central active column 120a and the edge active columns 120b may be adjacent in the x direction.

Word line trenches 113 may be formed between one edge active column 120b and the central active column 120a and between the central active column 120a and the other edge active column 120b. Embedded word lines 131 extending in the Y direction may be disposed in the word line trenches 113. The buried word lines 131 in the word line trenches 113 may be arranged parallel to each other.

The central active column 120a may include a bit line trench 143. The bit line trench 143 may be provided with a buried bit line 151 extending in the C direction. The buried bit lines 151 may be disposed at an angle of 90-a with the buried word lines 131 to cross the buried word lines 131 in an oblique direction.

The word line trenches 113 may be formed deeper than the bit line trenches 143. The buried word lines 131 disposed in the word line trenches 113 may be spaced apart from the buried bit lines 151 disposed in the bit line trenches 143. [ The upper surface of the buried bit line 151 is disposed below the upper surface of the central active column 120a. Thus, the buried bit line 151 may be buried in the bit line trench 143.

A second impurity region 147 is disposed in the central active column 120a adjacent to the buried bit line 151 and a second impurity region 147 is formed in the edge active columns 120b adjacent to the buried word lines 131 The first impurity regions 115 may be disposed.

The buried bit lines 151 may be formed above the buried word lines 131 so that the first impurity regions 115 may be formed in each of the edge active columns 120b And the second impurity region 147 may be formed in the central active column 120a. Therefore, when a voltage is applied to the gate electrode, a part of the channel region may be formed horizontally on the semiconductor substrate 100 below the lower surface of the buried word lines 131. Therefore, it is possible to prevent the channel region between the first impurity regions 115 and the second impurity region 147 from floating even when no voltage is applied to the gate electrode.

2A to 9A are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 2B to 9B are cross-sectional views taken along the line A-A 'in FIGS. 2A to 9B. FIG.

Referring to FIGS. 2A and 2B, a plurality of active portions 120 may be defined by forming isolation films 103 on a semiconductor substrate 100. The active portions 120 may protrude vertically from the semiconductor substrate 100. The active portions 120 may have a rectangular shape extending in the X-axis direction.

The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

The semiconductor substrate 100 is anisotropically etched to a predetermined depth using the hard mask patterns 104 formed on the semiconductor substrate 100 to form the trenches 107. A planarization process (e.g., a chemical mechanical polishing process) is performed on the insulating material formed on the hard mask patterns 104 after filling the trenches 107 with an insulating material (e.g., oxide or nitride) The device isolation films 103 can be formed. The active portions 120 may be arranged in a zigzag form in plan view by the device isolation films 103.

3A and 3B, the word line trenches 113 may be formed in the semiconductor substrate 100 in which the active portions 120 and the isolation layers 103 are formed.

In detail, the word line trenches 113 form first photoresist patterns 111 on the semiconductor substrate 100, and the first photoresist patterns 111 exposed on the first photoresist patterns 111 100) may be formed by anisotropically etching to a predetermined depth. The first photoresist patterns 111 may be formed so that two word line trenches 113 are disposed in one active portion 120. [ The word line trenches 113 may extend in the Y-axis direction. One active portion 120 may be divided into the central active column 120a and the edge active columns 120b formed on both sides of the central active column 120a by the word line trenches 113. [ The word line trenches 113 may be formed across the active portions 120. After the word line trenches 113 are formed, the first photoresist patterns 111 may be removed by an ashing process.

Referring to FIGS. 4A and 4B, gate insulating films 122 may be formed on the inner walls of the word line trenches 113.

The gate insulating layers 122 may be conformally formed along the inner walls of the word line trenches 113. [ The gate insulating films 122 may be a thermal oxide film formed by a thermal oxidation process. Alternatively, the gate insulating films 122 may include an oxide, a nitride, an oxynitride, or a high-dielectric material (for example, hafnium oxide, aluminum oxide).

Referring to FIGS. 5A and 5B, buried word lines 131 may be formed in the word line trenches 113 in which the gate insulating layers 112 are formed.

In detail, the buried word lines 131 are formed by forming a buried conductive film (not shown) in the word line trenches 113 in which the gate insulating films 122 are formed, Or the like. Accordingly, the buried word lines 131 may be formed to fill a lower portion of the word line trenches 113. The gate insulating films 122 may be exposed to the inner walls of the word line trenches 113 in which the buried word lines 131 are not filled. The buried word lines 131 may be formed of, for example, polysilicon, metal materials, or metal suicide materials.

The buffer insulating patterns 133 may be formed to fill the word line trenches 113 on the buried word lines 131. The buffer insulating patterns 133 are formed to fill the word line trenches 113 and then the buffer insulating layer and the hard mask pattern are formed to expose the upper surface of the semiconductor substrate 100, And then performing a planarization process with respect to the semiconductor layers 104. The buffer insulating patterns 133 may include silicon oxide, silicon nitride, or silicon oxynitride.

After the hard mask patterns 104 are removed, an ion implantation process may be performed to form the first impurity regions 115 and the second impurity regions 147 in the active portions 120. The first impurity regions 115 may be formed in the edge active pillars 120b and the second impurity region 147 may be formed in the central active pillars 120a. The first impurity regions 115 and the second impurity region 147 may be formed to have a shallower depth than the word line trenches 113.

Referring to FIGS. 6A to 6C, a bit line trench 143 may be formed by etching a portion of the central active column 120a.

In detail, the second photoresist patterns 141 may be formed on the semiconductor substrate 100 so that a part of the central active column 120a may be etched. Then, the central active pillars 120a exposed to the second photoresist patterns 141 may be anisotropically etched to form the bit line trenches 143 extending in the C direction. That is, one bit line trench 143 extending in the C direction may be formed by etching a part of the plurality of the central active columns 120a. The bit line trenches 143 may be formed to have a shallower depth than the word line trenches 113. The bottom surface of the bit line trench 143 may be disposed on the upper surface of the buried word lines 131. Thus, the second impurity region 147 may remain under the bit line trench 143.

Spacers 149 may be formed on the sidewalls of the bit line trenches 143. The spacers 149 may be formed such that a bottom surface of the bit line trench 143 is exposed. The spacers 149 may be formed by uniformly depositing an insulating layer (not shown) on the inner wall of the bit line trench 143 and then performing an etch-back process on the insulating layer. The spacers 149 may be made of an insulating material (e.g., silicon oxide, or silicon nitride). The spacers 149 may be formed to prevent the buried bit line 151 formed in the next step from contacting the edge active pillars 120b.

Referring to FIG. 6C, as the angle between the active pillars 120 and the bit line trenches 143 increases, the spacers 149 may not be formed. This is because the bit line trenches 143 are formed sufficiently away from the edge active pillars 120b.

Referring to FIGS. 7A and 7B, a buried bit line 151 may be formed to fill a lower portion of the bit line trench 143 where the spacers 149 are formed.

In detail, the buried bit line 151 may be formed by depositing the bit line trench 143 sufficiently to fill the conductive film, and then performing an etch-back process. The buried bit lines 151 may be embedded in the central active column 120a and extend in the C direction. The buried bit line 151 may be formed of, for example, polysilicon, metal materials, or a metal suicide material.

An insulative pattern 153 may be formed to completely fill the bit line trenches 143 on the buried bit lines 151. The insulating pattern 153 is formed so as to fill the bit line trench 143 and then is patterned to expose the upper surface of the semiconductor substrate 100. The insulating film 153 and the second photoresist patterns 141 ) Can be formed by performing a planarization process. Accordingly, the upper surface of the active portions 120 can be exposed. The insulating pattern 153 may include silicon oxide, silicon nitride, or silicon oxynitride.

8A and 8B, capacitors 170 may be formed on the edge active pillars 120b and a contact plug may be formed between the capacitors 170 and the edge active pillars 120b. (155) may be disposed. Accordingly, the capacitors 170 may be electrically connected to the edge active pillars 120b.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

10: Semiconductor device
100: semiconductor substrate
113: word line trenches
115: first impurity region
120a: central active column
120b: edge active column
131: Buried word lines
143: bit line trench
147: second impurity region
151: buried bit line

Claims (10)

A semiconductor substrate;
A central active column between the edge active columns protruding vertically from the top surface of the semiconductor substrate and the edge active columns;
Buried word lines disposed between the central active column and the edge active columns; And
A buried bit line disposed in the central active column and disposed diagonally with respect to the buried word lines,
Wherein an upper surface of the buried bit line is disposed below an upper surface of the central active column and a lower surface of the buried bit line is disposed above an upper surface of the buried word lines. The method according to claim 1,
First impurity regions disposed in the edge active columns on the buried word lines; And
And a second impurity region disposed in the central active column. The method according to claim 1,
Spacers covering sidewalls of the buried bit line; And
And an insulating pattern disposed on the buried bit line in the central active column. The method according to claim 1,
A gate insulating layer covering the central active column and the edge active columns; And
And a buffer insulating pattern covering the gate insulating film and disposed on the upper surface of the buried word lines. The method according to claim 1,
Capacitors disposed on the edge active pillars; And
Further comprising contact plugs disposed between the edge active pillars and the capacitors. Forming device isolation films defining active portions in a semiconductor substrate;
Forming wordline trenches across the active portions to form active columns protruding from the semiconductor substrate;
Forming buried word lines to fill the bottom portion of the word line trenches by placing a gate insulating layer on the inner walls of the word line trenches;
Forming a bit line trench extending in an oblique direction relative to the buried word lines in an active column between the buried word lines;
Forming a buried bit line filling the bottom portion of the bit line trench,
Wherein a bottom surface of the bit line trenches is disposed above a bottom surface of the word line trenches. The method according to claim 6,
Further comprising forming impurity regions in the active columns after forming the word line trenches. The method according to claim 6,
After forming the bit line trenches,
Forming contact plugs on the edge active pillars; And
And forming capacitors on the contact plugs. The method according to claim 6,
Further comprising forming spacers to cover sidewalls of the bit line trenches before forming the bit line trenches. The method according to claim 1,
Further comprising forming buried insulation patterns filling the spaces between the active columns after forming the buried word lines.

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