KR960006721B1 - Stacked capacitor fabrication process - Google Patents

Abstract

The method includes the steps of forming a MOSFET, first, second and third insulating layers(6,7,8), fourth planarizing insulating layer(9) and fifth insulating layer(10) on the substrate and forming a first conductive layer(12) for a storage node thereon, laminating a sixth insulating layer(13), second conductive layer(14) for the storage node, seventh insulating layer(15) and third conductive layer(16) for the storage node on the first conductive layer(12) and selectively etching the third conductive layer(16) and sixth insulating layer(13), dry-etching predetermined portions of the third conductive layer(16), seventh insulating layer(15), second conductive layer(14) and sixth insulating layer(13) using a storage node mask pattern and wet-etching the sixth and seventh insulating layers to create undercut the lower portion of the edges of the third and second conductive layers(16,14), and forming a fourth conductive layer for the storage node on the substrate and blanket-etching the fourth, third conductive layer and first conductive layer.

Description

Stack Capacitor Manufacturing Method

1 is a layout diagram of a DRAM cell manufactured according to the present invention.

2A through 2G are cross-sectional views illustrating the steps produced by the present invention along A-A of FIG.

3A through 3G are cross-sectional views illustrating the steps of manufacturing by the present invention along B-B in FIG.

* Explanation of cold protection symbols in the main parts of the drawings

1: Silicon Substrate 2: Device Oxide

3: gate oxide film 4: word line

5: source / drain 6: first insulating film

7: second insulating film 8: third insulating film

9: fourth insulating film 10: fifth insulating film

11: bit line 12: first conductive layer

13: sixth insulating film 14: second conductive layer

15: seventh insulating film 16: bit line

80,90: contact.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a stack capacitor of a highly integrated semiconductor memory device. In particular, a storage electrode of a predetermined type is formed to increase the capacity of a capacitor, and then a capacitor dielectric film is formed on the lower, inner and outer surfaces of the storage electrode, and then a plate. The present invention relates to a stack capacitor manufacturing method for forming an electrode.

As the integration degree of DRAM increases, the cylindrical structure and the fin structure have been developed as well as practical use as a capacitor structure to secure sufficient capacitor capacity in a small area. However, these structures are difficult to manufacture and must be considered in mass production. There were problems in productivity, simplicity and reliability.

Accordingly, an object of the present invention is to provide a stack capacitor manufacturing method capable of maximizing a capacitor capacity in a small area while minimizing the above problems.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 1 is a schematic layout diagram of a DRAM cell manufactured according to the present invention. The word lines 50 are arranged at a predetermined interval in the vertical direction, and the bit lines 60 are spaced at a predetermined interval in the horizontal direction. Arrange a storage electrode 70 having a predetermined width in the space between the bit lines 60, and arrange a contact 80 in the center of the storage electrode 70 to contact the storage electrode 70 to the silicon substrate, Arrangement of the contact 90 which contacts the bit line 60 to a silicon substrate shows the position of each area | region.

2A through 2G illustrate the AA cross section of FIG. 1 and FIG. 3A through 3G illustrate the process steps of manufacturing the stack capacitor according to the present invention along the BB cross section of FIG. 1 for convenience. Shall be.

2A and 3A are cross-sectional views illustrating the formation of a MOSFET having a fold bit line DRAM cell structure by a known technique and contacting the first conductive layer for storage electrodes to the drain of the MOSFET. A MOSFET including the device isolation oxide film 2, the gate oxide film 3, the word line 4, the insulating spacer 6A, and the source / drain 5 is formed, and at the same time, the word line is formed on the device isolation oxide film 2. 4) and an insulating spacer 6A are formed, and then a first insulating film 6 and a planarizing second insulating film 7 are laminated on the entire structure, and the bit line 11 is contacted to the source / drain 5. Then, the third insulating film 8, the planarizing fourth insulating film 9, and the fifth insulating film 10 are laminated on the entire structure, and then the first conductive charge 12 for the storage electrode is deposited to form a contact hole. It is sectional drawing of the state which contacted the source / drain 5 via.

The fourth insulating film 9 and the fifth insulating film 10 should be made of a material having a different etching selectivity from a predetermined wet etchant. 2B and 3B show a sixth insulating layer 13, a second conductive layer 14 for a storage electrode 14, a seventh insulating layer 15, and a third for a storage electrode on the first conductive charge 12 for the storage electrode. After the conductive layer 16 is sequentially deposited, the cross-sectional view of forming the first photoresist layer pattern 20 for the storage electrode contact mask is performed. The sixth insulating layer 13 and the seventh insulating layer 15 may be formed of oxide, and the first, second, and third conductive layers 12, 14, and 16 for the storage electrode may be formed of polysilicon. Can be.

2C and 3C sequentially dry-etch the third conductive layer 16 and the seventh insulating layer 15 for the storage electrode using the first photoresist pattern 20 as a mask, and then the first photoresist pattern 20 Is a cross-sectional view of removing the second photoresist film pattern 22 for the storage electrode mask.

2D and 3D show a third conductive layer 16 for a storage electrode, a seventh insulating layer 15, a second conductive layer 14 for a storage electrode 14 and a sixth insulating layer using the second photoresist pattern 22 as a mask. After sequentially etching (13), the second photoresist layer pattern 22 is removed, and the seventh insulating layer 15 and the sixth insulating layer 13 are wet-etched to form second and third conductive layers for storage electrodes ( 14, 16) undercut is generated on the edge.

2E and 3E show the fourth conductive layer 17 for the storage electrode on the entire structure, and the fourth electrode for the storage electrode until the seventh insulating layer 15 is exposed by the blanket etch back. And dry etching the third conductive layers 17 and 14 to form a fourth conductive layer spacer 17A for the storage electrode, wherein the second and first conductive layers 14 and 12 for the storage electrode are the fourth for the storage electrode. The storage electrode pattern is interconnected by the conductive layer spacers 17A, and the fourth conductive layer spacers 17A for the storage electrodes are partially formed on the second conductive layer 14 for the storage electrodes.

2F and 3F completely remove the fifth, sixth, and seventh insulating layers 10, 13, and 15 by wet etching to expose the surface of the storage electrode 30.

2G and 3G show that a capacitor dielectric film 18 is formed on the surface of the storage electrode 30, and a conductive layer 19 for plate electrodes is formed.

According to the present invention, as the degree of integration of the device is increased and the unit cell area is reduced, the technology capable of photo-etching to 0.4 μm or less, which is essential for realizing high integration of 64 Mega DRAM or more, can secure sufficient capacity in a small area. It is a technology that can.

Claims (5)

In the DRAM stack capacitor manufacturing method, a MOSFET is formed on a silicon substrate, first, second and third insulating films and a fourth insulating film for planarization are formed on the entire structure, and a fifth insulating film is formed thereon. Forming a first conductive layer for the storage electrode by contacting the source / drain on the upper portion, a sixth insulating layer, a second conductive layer for the storage electrode, a seventh insulating layer, and a third conductive layer for the storage electrode on the first conductive layer Stacking and etching a predetermined portion of the third conductive layer on the storage electrode contact portion and the sixth insulating film on the lower portion thereof, and using the photosensitive film pattern for the storage electrode mask, the third conductive layer, the seventh insulating film, Dry etching the second conductive layer and the sixth insulating layer sequentially to form a pattern, and then wet etching the sixth and seventh insulating layers to undercut the edges of the third and second conductive layers; A fourth conductive layer for storage electrodes is placed on the entire structure Then, the fourth conductive layer spacer is formed by etching the fourth conductive layer and the third conductive layer exposed through the blanket dry etching to form the pattern by etching the first conductive layer until the seventh insulating layer and the fifth insulating layer are exposed. (A) connecting the first conductive layer pattern to the second conductive layer pattern, forming a storage electrode pattern having a fourth conductive layer spacer formed on the second conductive layer pattern, and completely wet etching the seventh insulating layer and the sixth insulating layer. And wet etching the fifth insulating layer under the first conductive layer to expose the surface of the storage electrode, forming a capacitor dielectric layer on the surface of the storage electrode, and depositing a conductive layer for a plate electrode thereon. Stack capacitor manufacturing method. The method of claim 1, wherein the planarization insulating layer and the fifth insulating layer are formed of a material having a different etching selectivity. The method of claim 1, wherein the first photoresist pattern for the storage electrode contact mask is used to remove a portion of the third conductive layer and the sixth insulating layer on the storage electrode contact. The method of claim 1, wherein the fifth, sixth, and seventh insulating layers are formed of an oxide film. The method of claim 1, wherein the first, second, and third conductive layers for the storage electrodes are formed of polysilicon.