KR960011662B1 - Stack capacitor manufacturing method - Google Patents
Stack capacitor manufacturing method Download PDFInfo
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- KR960011662B1 KR960011662B1 KR1019930008766A KR930008766A KR960011662B1 KR 960011662 B1 KR960011662 B1 KR 960011662B1 KR 1019930008766 A KR1019930008766 A KR 1019930008766A KR 930008766 A KR930008766 A KR 930008766A KR 960011662 B1 KR960011662 B1 KR 960011662B1
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- conductive layer
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- 239000003990 capacitor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 26
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 2
- 238000009736 wetting Methods 0.000 claims description 2
- 238000003763 carbonization Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
제1도는 디램셀의 레이아웃도.1 is a layout diagram of a DRAM cell.
제2a도 내지 제2g도는 본 발명의 실시예에 의해 스택캐패시터를 제조하되 제1도의 Ⅰ-Ⅰ를 따라 도시한 단면도.2A to 2G are cross-sectional views taken along the line I-I of FIG. 1 to manufacture a stack capacitor according to an embodiment of the present invention.
제3a도 내지 제3g도는 본 발명의 실시예에 의해 스택캐패서터를 제조하되 제1도의 Ⅱ-Ⅱ를 따라 도시한 단면도.3A to 3G are cross-sectional views taken along line II-II of FIG. 1 to manufacture a stack capacitor according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
3 : 워드라인 6 : 비트라인3: word line 6: bit line
8 : 평탄화용 제4절연층 9 : 제5절연층8: fourth insulating layer for planarization 9: fifth insulating layer
10 : 제1도전층 11 : 제6절연층10: first conductive layer 11: sixth insulating layer
12 : 제2도전층 13 : 제3도전층 스페이서12: second conductive layer 13: third conductive layer spacer
14 : 제4도전층 15 : 제7절연층 스페이서14: fourth conductive layer 15: seventh insulating layer spacer
17 : 캐패시터 유전체막 18 : 플레이트전극용 도전층17 capacitor dielectric film 18 conductive layer for plate electrode
20, 70 : 저장전극 30 : 제1감광막패턴20, 70: storage electrode 30: the first photosensitive film pattern
33 : 제2감광막패턴 50 : 워드라인33: second photoresist pattern 50: word line
60 : 비트라인 80 : 비트라인콘택60: bit line 80: bit line contact
90 : 저장전극콘택90: storage electrode contact
본 발명은 고집적 반도체 소자의 디램셀에 적용되는 스택캐패시터 제조방법에 관한 것으로, 특히 집적도가 높은 64메가 디램 및 256메가 디램에서도 적용이 가능한 스택캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack capacitor manufacturing method applied to a DRAM cell of a highly integrated semiconductor device. In particular, the present invention relates to a stack capacitor manufacturing method applicable to a high integration 64 mega DRAM and 256 mega DRAM.
최근에는 반도체 소자의 소자가 높아지고 단위셀의 면적이 축소됨에 따라서 64메가급 이상의 고집적 소자를 실현하기 위하여 필수불가결한 핵심기술은 0.4㎛ 이하로 선폭을 제조할 수 있는 리소그라피 기술과 더불어 좁은 면적에서 충분한 값의 용량을 확보하는 것이 관건이다.In recent years, as the number of semiconductor devices increases and the area of unit cells decreases, the core technology that is indispensable for realizing more than 64 mega-level integrated devices is lithography technology capable of manufacturing line widths of 0.4 µm or less, and sufficient in a small area. The key is to secure the capacity of the value.
따라서, 본 발명은 64메가 이상의 고집적 반도체 소자의 디램셀에 적용할 수 있는 스택캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a stack capacitor manufacturing method that can be applied to DRAM cells of 64 mega or more high-density semiconductor devices.
본 발명에 의하면 디램셀의 스택캐패시터 제조방법에 있어서, 실리콘기판 상부에 워드라인과 비트라인을 각각 절연된 구조로 형성하고, 그 상부에 절연층을 형성하는 공정과, 평탄화된 절연층 상부에 절연층을 형성하고, 절연층 상부에 저장전극용 제1도전층, 절연층 및 저장전극용 제2도전층을 각각 예정된 두께로 적층하는 공정과, 제2도전층 상부에 저장전극용 콘택마스크용 제2감광막패턴을 도포하고, 콘택영역의 제2도전층, 절연층 및 제1도전층을 순차적으로 건식식각하는 공정과, 제2감광막패턴을 제거한 다음, 습식식각공정으로 평탄화용 절연층이 노출되기까지 제1도전층 상부 및 하부의 절연층을 식각하고, 절연층, 제1도전층, 절연층, 및 제2도전층 측벽에 제3도전층 스페이서를 형성하는 공정과, 제2도전층과 제3도전층 스페이서를 마스크로 하여 하부의 평탄화용 절연층을 식각하여 실리콘기판이 노출되는 콘택홀을 형성하는 단계와, 저장전극용 제4도전층을 예정된 두께로 증착하고 그 상부에 저장전극 마스크용 제3감광막패턴을 형성하고, 건식식각 공정으로 노출된 제4도전층의 예정된 두께를 식각하여 단차를 형성하는 단계와, 제4도전층의 단차에 절연층 스페이서를 형성하고 절연층 스페이서를 마스크로 하여 제4도전층을 식각하고 노출되는 그 하부의 제2도전층을 식각하는 공정과, 노출되는 절연층을 건식식각하고, 계속하여 제4절연층이 노출되기까지 제1도전층을 식각하여 제1도전층, 제2도전층, 제3도전층 및 제4도전층이 전기적으로 접속된 저장전극을 형성하는 공정과, 제1도전층 상,하부에 있는 절연층을 식각한 다음, 저장전극 표면에 캐패시터 유전체막 플레이트 전극용 도전층을 적층하여 캐패시터를 형성하는 공정을 특징으로 한다.According to the present invention, in the method for manufacturing a stack capacitor of a DRAM cell, a process of forming a word line and a bit line in an insulated structure on an upper part of a silicon substrate, and forming an insulating layer thereon, and insulating the upper part of the planarized insulating layer Forming a layer, and laminating the first conductive layer for the storage electrode, the insulating layer, and the second conductive layer for the storage electrode to a predetermined thickness on the insulating layer, and the contact mask for the storage electrode on the second conductive layer. 2) applying a photoresist pattern, sequentially dry etching the second conductive layer, the insulating layer, and the first conductive layer of the contact region; removing the second photoresist pattern; and then wetting the substrate to expose the planarization insulating layer. Etching the insulating layers above and below the first conductive layer, and forming a third conductive layer spacer on the sidewalls of the insulating layer, the first conductive layer, the insulating layer, and the second conductive layer, and the second conductive layer and the second conductive layer. 3 Conductive layer spacer as mask Etching the lower planarization insulating layer to form a contact hole exposing the silicon substrate, depositing a fourth conductive layer for the storage electrode to a predetermined thickness, and forming a third photoresist pattern for the storage electrode mask thereon; Etching the predetermined thickness of the fourth conductive layer exposed by the dry etching process to form a step; forming an insulating layer spacer on the step of the fourth conductive layer and etching the fourth conductive layer using the insulating layer spacer as a mask. And etching the second conductive layer under the exposed portion, dry etching the exposed insulating layer, and subsequently etching the first conductive layer until the fourth insulating layer is exposed, thereby etching the first conductive layer and the second conductive layer. Forming a storage electrode electrically connected to the layer, the third conductive layer, and the fourth conductive layer; and etching the insulating layer on the upper and lower portions of the first conductive layer, and then, on the surface of the storage electrode, for a capacitor dielectric film plate electrode. Conductive layer It characterized by the step of lamination to form a capacitor.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도는 본 발명에 의한 디램셀의 주요부분을 도시한 레이아웃도로서, 워드라인(50)을 종방향으로 다수개 배치하고, 비트라인(60)을 횡방향으로 다수개 배치하고, 저장전극(70)을 비트라인(60) 사이의 액티브영역에 배치하고, 비트라인 콘택영역(80)과 저장전극 콘택(90)을 각각 액티브영역에 배치한 것이다.FIG. 1 is a layout diagram showing main parts of a DRAM cell according to the present invention, wherein a plurality of word lines 50 are disposed in a longitudinal direction, a plurality of bit lines 60 are disposed in a horizontal direction, and a storage electrode ( 70 is disposed in the active region between the bit lines 60, and the bit line contact region 80 and the storage electrode contact 90 are respectively disposed in the active region.
제2a도 내지 제2g도는 본 발명의 실시예에 의해 디램셀의 스택캐패시터를 형성하는 단계를 제1도의 Ⅰ-Ⅰ를 따라 도시한 단면도이며, 제3a도 내지 제3g도는 본 발명의 실시예에 의해 디램셀의 스택캐패시터를 형성하는 단계를 제1도의 Ⅱ-Ⅱ를 따라 도시한 단면도로서 편의상 공정단계에 따라 함께 설명하기로 한다.2A to 2G are cross-sectional views illustrating the steps of forming a stack capacitor of a DRAM cell according to an embodiment of the present invention, taken along the line I-I of FIG. 1, and FIGS. 3A to 3G illustrate embodiments of the present invention. The step of forming the stack capacitor of the DRAM cell by the cross-sectional view along II-II of FIG. 1 will be described together according to the process steps for convenience.
제2a도 및 제3a도는 공지의 기술로 실리콘기판(1)의 예정된 부분에 소자 분리 산화막(2)을 형성하고, 종방향으로 도전층으로된 워드라인(3)을 형성하고, 그 상부에 제1절연층(4) 예를 들어 산화막을 얇은 두께로 증착하고, 그 상부에 평탄화용 제2절연층(5) 예를 들어 BPSG층을 형성한 다음, 횡방향으로 도전층으로 된 비트라인(6)을 형성하고, 전체적으로 제3절연층(7) 예를 들어 산화막을 얇게 형성한 다음, 그 상부에 평탄화용 제4절연층(8)으로 예를 들어 BPSG층과 그 상부에 제5절연층(9)으로 예를 들어 산화막을 적층하고, 그 상부에 저장전극용 제1도전층(10), 제6절연층(11), 저장전극용 제2도전층(12)을 각각 예정된 두께로 적층한 다음(여기서 제1도전층(10) 및 제2도전층(12)은 폴리실리콘층으로 형성하고 제6절연층(11)은 산화막을 형성한다), 제2도전층(12) 상부에 저장전극 콘택마스크용 제1감광막패턴(30)을 형성한 다음, 노출되는 부분의 제2도전층(12) 및 제6절연층(11), 및 제1도전층(10)을 순차적으로 건식식각하여 제5절연층(9)을 노출시킬 상태의 단면도이다.2A and 3A show a device isolation oxide film 2 in a predetermined portion of the silicon substrate 1 by a known technique, forming a word line 3 of a conductive layer in the longitudinal direction, and 1 Insulating layer 4, for example, an oxide film is deposited to a thin thickness, and a planarizing second insulating layer 5, for example, a BPSG layer is formed thereon, and then a bit line 6 made of a conductive layer in the transverse direction. ) To form a third insulating layer (7), for example, an oxide film as a whole, and then to the fourth insulating layer (8) for planarization thereon, for example, a BPSG layer and a fifth insulating layer (top). 9), for example, an oxide film is stacked, and a first conductive layer 10 for storage electrodes, a sixth insulating layer 11, and a second conductive layer 12 for storage electrodes 12 are stacked to have a predetermined thickness thereon. Next (where the first conductive layer 10 and the second conductive layer 12 are formed of a polysilicon layer and the sixth insulating layer 11 forms an oxide film), on the second conductive layer 12. After forming the first photoresist pattern 30 for the long electrode contact mask, the second conductive layer 12, the sixth insulating layer 11, and the first conductive layer 10 of the exposed portion are sequentially dry-etched. 5 is a cross-sectional view of the state in which the fifth insulating layer 9 is exposed.
제2b도 내지 제3b도는 제1감광막패턴(30)을 제거한 다음, 습식식각으로 제4절연층(8)이 노출되기까지 제6절연층(11)과 제5절연층(9)을 식각한 후, 전체 구조 상부에 3도전층 예를 들어 폴리실리콘층을 증착하고 이방성 건식식각으로 제3도전층을 에치백하여 제3도전층 스페이서(13)를 제5절연층(9), 제6절연층(11), 제1도전층(10)과 제2도전층(12) 패턴측벽에 형성한 다음, 제2도전층(12)과 제3도전층 스페이서(13)를 마스크로 하여 저장전극 콘택영역의 제4절연층(8), 제3절연층(7), 제2절연층(5), 제1절연층(4)을 식각하여 실리콘기판(1)이 노출된 콘택홀(25)을 형성한 단면도이다.2B through 3B illustrate the removal of the first photoresist pattern 30 and etching the sixth insulating layer 11 and the fifth insulating layer 9 until the fourth insulating layer 8 is exposed by wet etching. After that, a third conductive layer, for example, a polysilicon layer is deposited on the entire structure, and the third conductive layer spacer 13 is etched back by anisotropic dry etching to form the third conductive layer spacer 13 as the fifth insulating layer 9 and the sixth insulating layer. After the layer 11, the first conductive layer 10 and the second conductive layer 12 are formed on the sidewalls of the pattern, the storage electrode contacts with the second conductive layer 12 and the third conductive layer spacer 13 as masks. The fourth insulating layer 8, the third insulating layer 7, the second insulating layer 5, and the first insulating layer 4 of the region are etched to form the contact hole 25 where the silicon substrate 1 is exposed. It is formed section.
제2c도 및 제3c도는 전체구조 상부에 저장전극용 제4도전층(14) 예를 들어 폴리실리콘층을 예정된 두께(제1도전층(10)과 제2도전층(12)의 합한 두께보다 큰 두께)로 증착한 후 저장전극용 마스크용 제2감광막 패턴(33)을 형성한 단면도이다.2C and 3C show the fourth conductive layer 14 for the storage electrode, for example, the polysilicon layer on the entire structure, than the predetermined thickness (the combined thickness of the first conductive layer 10 and the second conductive layer 12). The second photosensitive film pattern 33 for a storage electrode mask is formed after the deposition with a large thickness).
제2d도 및 제3d도는 제2감광막패턴(33)을 마스크로하여 제4도전층(14)의 일정두께(제1도전층(10)과 제2도전층(12)의 두께를 합한 두께 정도)를 식각하여 제4도전층(14)에 단차를 형성하고, 제2감광막패턴(33)을 제거한 후 단차가 형성된 제4도전층(14)의 상부에 제7절연층 예를 들어 산화막을 형성한 후 블란켓 식각공정을 실시하여 제7절연층 스페이서(15)를 제4도전층(14)의 단차부위에 형성한 단면도이다.2D and 3D show a thickness of the fourth conductive layer 14 (the thickness of the first conductive layer 10 and the second conductive layer 12, which is the total thickness of the fourth conductive layer 14 using the second photosensitive film pattern 33 as a mask). ) To form a step on the fourth conductive layer 14, remove the second photoresist pattern 33, and then form a seventh insulating layer, for example, an oxide layer on the fourth conductive layer 14 on which the step is formed. After that, a blanket etching process is performed to form a seventh insulating layer spacer 15 on the stepped portion of the fourth conductive layer 14.
제2e도 및 제3e도는 제7절연층 스페이서(15)를 마스크로한 블란켓 식각공정으로 제4도전층(14)과 제2도전층(12)을 식각하여 원통형 구조의 제4도전층(14) 패턴을 형성하고, 노출되는 제6절연층(11)을 건식식각하고, 계속하여 제5절연층(9)이 노출되기까지 제1도전층(10)을 식각하여 제1, 제2 및 제3, 제4도전층(10,12,13,14)이 전기적으로 접속된 저장전극(20)을 도시한 단면도이다.2E and 3E illustrate a fourth conductive layer having a cylindrical structure by etching the fourth conductive layer 14 and the second conductive layer 12 by a blanket etching process using the seventh insulating layer spacer 15 as a mask. 14) forming a pattern, dry etching the exposed sixth insulating layer 11, and subsequently etching the first conductive layer 10 until the fifth insulating layer 9 is exposed, thereby etching the first, second and 3 is a cross-sectional view illustrating the storage electrode 20 to which the third and fourth conductive layers 10, 12, 13, and 14 are electrically connected.
제2f도 및 제3f도는 습식식각 공정으로 남아있는 제7절연층 스페이서(15)와 제6절연층(11) 및 제5절연층(9)을 완전히 제거한 단면도로서, 예정된 습식식각 용액에서 제4절연층(8)은 제5, 제6, 제7절연층에 대해 식각베리어로 작용하는 것과, 제4절연층(8) 상부에 있는 저장전극(20)의 표면은 완전히 노출됨을 도시한다.2F and 3F are cross-sectional views completely removing the seventh insulating layer spacer 15, the sixth insulating layer 11, and the fifth insulating layer 9 remaining in the wet etching process. The insulating layer 8 acts as an etch barrier for the fifth, sixth and seventh insulating layers, and the surface of the storage electrode 20 on the fourth insulating layer 8 is completely exposed.
제2g도 및 제3g도는 저장전극(20) 표면에 캐패시터 유전체막(17)을 형성한 후 그 상부에 플레이트 전극용 도전층(18)을 증착한 단면도이다.2G and 3G are cross-sectional views of forming a capacitor dielectric film 17 on the storage electrode 20 and then depositing a conductive layer 18 for plate electrodes thereon.
상기한 본 발명에 의하면 비교적 간단한 공정으로 토폴로지(Topology)를 최소화하면서 64메가급 이상에 필요한 캐패시터 용량을 얻을 수 있는 스택캐패시터를 제조할 수 있다.According to the present invention described above, it is possible to manufacture a stack capacitor capable of obtaining a capacitor capacity necessary for 64 megabytes or more while minimizing topology in a relatively simple process.
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| KR1019930008766A KR960011662B1 (en) | 1993-05-21 | 1993-05-21 | Stack capacitor manufacturing method |
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