KR940011806B1 - Dram cell and fabricating method thereof - Google Patents

Abstract

The method includes the steps of depositing a 1st conducting layer (11) on the semiconductor structure to connect the layer (11) with the poly-Si pad (8A) to form a 1st insulating layer (12) thereon to remove the layer (12) portion on the drain, depositing a 2nd conducting layer (14) thereon to connect the layer (14) with the lower layer (12) to form a 2nd insulating layer (15) thereon to remove the layer (15) portion except the drain upper portion, depositing a 3rd conducting layer (17) on the layer (15) to connect the layer (17) with the lower layer (14), and etching the layers (17,14,15,12) to form a charge storage electrode with the 1st, 2nd and 3rd conductive patterns (11A,14A,17A).

Description

DRAM cell and manufacturing method thereof

1 is a layout cross section of a DRAM cell.

2 (a) to 2 (h) are cross-sectional views taken along the line AA ′ of FIG. 1 showing a manufacturing step of a DRAM cell according to an embodiment of the present invention.

3 (a) to 3 (h) are cross-sectional views taken along the line BB ′ of FIG. 1 showing the manufacturing steps of a DRAM cell according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 device isolation oxide film

3: gate oxide film 4: gate electrode (word line)

5: mask oxide 6A: spacer oxide

6B: BPSG layer 7A and 7B: source and drain

8B: Bitline 8A: Polysilicon Pat

10 spacer oxide 11 first conductive layer for charge storage electrode

12: first insulating layer 13A: first photosensitive film pattern

14A: second conductive layer pattern for charge storage electrode 15: second insulating layer

16A: second photosensitive film pattern 17A: third conductive layer pattern for charge storage electrode

18: third photosensitive film pattern 19: dielectric film

20A: conductive layer for plate electrode 25: charge storage electrode

35: groove 45: tunnel-shaped through hole

50: active mask 60: wordline mask

70: bit line mask 80: bit line contact mask

90: charge storage electrode mask 100: charge storage electrode contact mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell of a highly integrated semiconductor memory device and a method of manufacturing the same. In particular, in order to increase the capacity of a capacitor, a tunnel-type charge storage electrode is formed, and then a capacitor is formed on the lower and inner surfaces of the tunnel-type charge storage electrode. The present invention relates to a stack capacitor in which a plate electrode is formed after a dielectric film is formed, and a method of manufacturing the same.

As DRAM integration increases, new types of charge storage electrode structures that can be applied to next-generation DRAMs have been developed and announced. Representative stacked cell structures disclosed above are roughly classified into cylindrical structures, fin structures, and the like. However, these structures are difficult to manufacture and have a lot of unit processes. Therefore, these structures may have many problems such as productivity, simplicity, and reliability in consideration of mass production of DRAM products.

Accordingly, an object of the present invention is to provide a stack capacitor and a method of manufacturing the same, which can maximize the capacitor capacity in a narrow cell area while minimizing the above problems.

According to the present invention, a polysilicon pad is formed in each of the source and the drain of the MOS transistor, and the bit line is electrically connected to the source through the polysilicon pad, and the charge storage electrode is provided as the first, second and third conductive layers. Is electrically connected to the drain through the polysilicon pad, and is formed inside the tunnel-shaped through hole and the third conductive layer formed at a predetermined lower portion of the edge of the second conductive layer of the charge storage electrode and between the second and third conductive layers. A dielectric film is formed on a predetermined upper surface of the upper and first conductive layer edges, and a conductive layer for plate electrodes is formed on the entire upper surface of the dielectric film, but also inside the tunnel-shaped through hole of the second and third conductive layers of the charge storage electrode. A structure in which the conductive layer for plate electrodes is filled is formed.

According to the present invention, there is formed a MOSFET including an isolation layer, a gate electrode, a source and a drain on a silicon substrate, and then forming a polysilicon pad on the source and the drain, and a bit on the polysilicon pad on the source. Forming a line and forming an insulating layer around the bit line, depositing a first conductive layer for the charge storage electrode on the entire structure, connecting the polysilicon pad on the drain, and coating the first insulating layer on the upper portion of the drain structure. And removing the first insulating layer on the drain by the charge storage contact mask process on the first insulating layer, and depositing a second conductive layer for the charge storage electrode on the first insulating layer. And a second insulating layer on the upper portion, and then patterning the second insulating layer on the upper portion of the drain by a predetermined pattern mask process. Depositing a third conductive layer for the charge storage electrode on the interconnection and interconnecting the second conductive layer on both sides of the second insulating layer, and etching the predetermined portion of the third conductive layer and the second conductive layer by the charge storage electrode mask process. Forming a second and a third conductive layer pattern, completely removing the second insulating layer between the second and third conductive layer patterns and the second insulating layer on the first conductive layer by wet etching, and plasma etching. Etching the first conductive layer to form a charge storage electrode provided with the first, second, and third conductive layer patterns; and a tunnel between the exposed portion of the charge storage electrode and the second and third conductive layer patterns. Another aspect is a step of forming a dielectric film on the surface of the through-hole of the type, and forming a conductive layer for plate electrodes on the dielectric film.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 1 is a layout diagram in which respective masks are arranged in order to manufacture DRAM cells according to the present invention, and includes an active mask 50, a word line mask 60, a bit line mask 70, and a bit line contact mask 80. As shown in FIG. The charge storage electrode mask 90 and the charge storage electrode contact mask 100 are arranged.

2 (a) to 2 (h) are cross-sectional views illustrating a process step of manufacturing a DRAM cell according to the first embodiment of the present invention by cutting along the line A-A 'of FIG.

FIG. 2 (a) shows a device isolation oxide film 2, a gate oxide film 3, a gate electrode 4, a mask oxide 5, a spacer oxide 6A, a source and the like on a silicon substrate 1 by a known technique. It is sectional drawing of the state which formed the drain 7A and 7B, respectively.

FIG. 2 (b) shows that the groove 30 on the device isolation oxide film 2 is filled with the BPSG layer 6B to a predetermined thickness, and the silicon 40 is exposed in the groove 40 where the source and drains 7A and 7B are exposed. Filled to form a polysilicon pad 8A, a bit line 8B and a microphone oxide 9 are formed on the polysilicon pad 8A connected to the source 7A, and a spacer oxide is formed on the sidewalls of the bit line 8B. After forming (10), it is sectional drawing of the state connected with the polysilicon pad 8A connected to the drain 7B by depositing the 1st electrically conductive layer 11 for electric charge storage electrodes as a whole.

In FIG. 2 (c), the first oxide layer 12 is coated on the first conductive layer 11 for the charge storage electrode to a predetermined thickness, and then the first photosensitive layer 13 is coated on the charge storage electrode contact. An upper portion of the drain 7B using the mask is a cross-sectional view in which the first photosensitive film pattern 13A is formed by removing the photosensitive film 13.

In FIG. 2 (d), the exposed first oxide film 12 is removed and the first photoresist film pattern 13A is removed. Then, the second conductive layer 14 for charge storage electrodes is deposited on the entire structure, and the upper portion of the first oxide film 12 is removed. The second oxide film 15 is applied to a predetermined thickness, and then the photoresist film 16 is applied on the second oxide film 15, and a predetermined width is formed on the drain 7B in the word line direction using a predetermined pattern mask. It is sectional drawing of the state which formed the 2nd photosensitive film pattern 16A which left 2nd photosensitive film 16. FIG.

In FIG. 2E, the exposed second oxide layer 15 is removed, the second photoresist layer pattern 16A is removed, and the charge storage electrode agent is disposed on the entire structure including the remaining second oxide layer pattern 15A. The third conductive layer 17 is deposited to interconnect the second conductive layer 14 and the third conductive layer 17 on both sides of the second oxide layer pattern 15A, and to form a third layer on the third conductive layer 17. The photosensitive film 18 is apply | coated, and sectional drawing of the state which formed the 3rd photosensitive film pattern 18A which removed the 3rd photosensitive film 18 on the source 7A using the charge storage electrode mask was formed.

FIG. 2 (f) shows the second and third conductive layer patterns 14A and 17A by removing the third conductive layer 17 and the second conductive layer 14 of the exposed area to form the second oxide layer pattern 15A. ) And the first oxide film 12 are completely removed by wet etching, and the through-hole 45 having a tunnel form in the word line direction between the third conductive layer pattern 17A and the second conductive layer pattern 14A. Is formed and the groove 35 is formed at the bottom of the edge of the second conductive layer pattern 14A.

In FIG. 2 (g), the predetermined portion of the remaining first conductive layer 11 is etched using the third photoresist pattern 18A to form the first conductive layer pattern 11A, and the third photoresist pattern ( A cross-sectional view of the state in which the charge storage electrode 25 provided with the first, second, and third conductive layer patterns 11A, 14A, and 17A is formed by removing 18A).

FIG. 2 (h) shows a tunnel-shaped through hole between the exposed surfaces of the first and third conductive layer patterns 11A and 17A of the charge storage electrode 25 and the second and third conductive layers 14A and 17A. (45) A cross-sectional view of a dielectric film 19 formed on an inner surface and a plate electrode conductive layer 20 deposited on a surface of the dielectric film 19, wherein the first and second conductive layer patterns 11A and The conductive layer 20 for plate electrodes is filled with the through hole 45 between the groove 35 between 14A) and the second and third conductive layers 14A and 17A.

3 (a) to 3 (h) are cross-sectional views illustrating a process step of fabricating a DRAM cell according to the present invention by cutting B-B 'of FIG. 1 to facilitate understanding of the present invention. The process proceeds to the same process sequence as each process step of FIG.

3 (a) is a cross-sectional view of the device isolation oxide film 2 and the drain 7B formed on the silicon substrate 1 by a known technique.

In FIG. 3 (b), the BPSG layer 6B is applied over the device isolation oxide film 2 and the drain 7B as a whole, and then the BPSG layer 6B on the drain 7B is removed and then the drain 7B. 8) a polysilicon pad 8A is formed on the upper part, a bit line conductive layer and a mask oxide 9 are laminated on the BPSG layer 6B, and a mask part 9 and the bit line of the predetermined part are formed by a bit line mask process. The conductive layer is removed to form the bit line 8B, the spacer oxide 10 is formed on the sidewalls of the bit line, and then the first conductive layer 11 for the charge storage electrode is deposited on the entire structure. ) Is a cross-sectional view of the state in which electrical contact is made through the polysilicon pad 8A.

3 (c) is a cross-sectional view of a state in which the first insulating layer 12 is formed on the first conductive layer 11 to a predetermined thickness, and the first photoresist layer pattern 13A is formed on the bit line 8B. to be.

FIG. 3 (d) removes the first photoresist layer pattern 13A, deposits the second conductive layer 14 for the charge storage electrode as a whole, and the second insulating layer 15 on the second conductive layer 14. After forming to a predetermined thickness, it is a cross-sectional view of the second photosensitive film pattern 16A is formed thereon.

3 (e) is a cross-sectional view of removing the second photoresist pattern 16A, depositing the third conductive layer 17 for the charge storage electrode as a whole, and forming the third photoresist pattern 18A thereon. to be.

In FIG. 3 (f), the exposed third conductive layer 17 is etched to form the third conductive layer pattern 17A, and then the second conductive insulating layer 15 and the lower portion of the third conductive layer pattern 17A are formed. 2 is a cross-sectional view of the first insulating layer 12 under the conductive layer 14 completely removed by wet etching.

In FIG. 3 (g), the second conductive layer 14 and the first conductive layer 11 on the bit line 8B are etched using the third photosensitive film pattern 18A, respectively, and the third photosensitive film pattern 18A is a cross sectional view showing the charge storage electrode 25 formed of the first, second and third conductive layer patterns 11A, 14A and 17A.

FIG. 3 (h) shows the dielectric film 19 on the exposed surface of the top, bottom and side surfaces of the charge storage electrode 25 after the process of FIG. 3 (g), and the plate electrode on the dielectric film 19. It is sectional drawing of the state in which the conductive layer 20 was formed.

According to the present invention, when the bit line and the charge storage electrode are contacted to the source and drain of the lower portion, the contact gap can be reduced by using the polysilicon pad, and the surface area of the charge storage electrode can be increased to increase the capacitance of the capacitor. DRAM cells can be manufactured.

Claims (11)

In a DRAM cell, a polysilicon pad is formed at a source and a drain of a MOS transistor, respectively, and a bit line is electrically connected to a source through a polysilicon pad, and the charge storage is provided as first, second, and third conductive layers. The electrode is electrically connected to the drain through the polysilicon pad, and is formed in the tunnel-shaped through hole and the third conductive layer formed between the lower portion of the edge of the second conductive layer of the charge storage electrode and the second and third conductive layers. A dielectric film is formed on the entire upper surface and a predetermined upper surface of the edge of the first conductive layer, and a conductive layer for plate electrodes is formed on the entire upper surface of the dielectric film, but the tunnel-shaped penetrating through the second and third conductive layers of the charge storage electrode. A DRAM cell comprising a structure in which a conductive layer for a plate electrode is filled in a hole. The DRAM cell of claim 1, wherein a BPSG layer is filled on the device isolation oxide to form a substantially flat surface with the polysilicon pad. The method of claim 1, wherein the second conductive layer for the charge storage electrode and the third conductive layer are connected at both ends and a tunnel-shaped through hole is formed in the word line direction inside the second and third conductive layers. DRAM cell. 2. The DRAM cell of claim 1, wherein the pattern line widths of the first, second, and third conductive layers of the charge storage electrode are formed in line widths between the outer ends of the gate electrodes adjacent to the drain in the bit line direction. . The DRAM cell of claim 1, wherein the bit line is formed on a lower surface of the charge storage electrode. The conductive layer of claim 1, wherein the conductive layer for the plate electrode is filled in the tunnel-shaped through hole between the second and third conductive layers of the charge storage electrode, A DRAM cell interconnected with the formed conductive layer for plate electrodes. In the DRAM manufacturing method, forming a MOSFET comprising an isolation layer, a gate electrode, a source and a drain on the silicon substrate, respectively, and then forming a polysilicon pad on the source and the drain, and a polysilicon pad on the source Forming a bit line on the bit line and forming an insulating layer around the bit line, depositing a first conductive layer for the charge storage electrode on the entire structure, and connecting the polysilicon pad on the drain to the first insulating layer thereon. And removing the first insulating layer on the drain by the charge storage contact mask process on the first insulating layer, and depositing the second conductive layer for the charge storage electrode on the first insulating layer. After connecting to the conductive layer, and applying a second insulating layer thereon, leaving the second insulating layer of the predetermined portion on the drain by a predetermined pattern mask process and removing the rest Depositing a third conductive layer for the charge storage electrode on the second insulating layer as a whole and interconnecting the second conductive layer on both sides of the second insulating layer; and forming the third conductive layer and the third conductive layer by the charge storage electrode mask process. A predetermined portion of the second conductive layer is etched to form second and third conductive layer patterns, and the second insulating layer between the second and third conductive layer patterns and the second insulating layer over the first conductive layer are wet-etched. Completely removing, etching the first conductive layer by plasma etching to form a charge storage electrode provided with the first, second and third conductive layer patterns, and exposing the second portion and the second portion of the charge storage electrode. And forming a dielectric film on the surface of the tunnel-shaped through hole between the third conductive layer patterns, and forming a conductive layer for plate electrodes on the dielectric film. The method of claim 7, wherein the MOSFETs are respectively formed, and then a BPSG layer is formed on the entire structure to form a flat surface, and the BPSG layers on the source and the drain are etched to form grooves where the source and drain are exposed. Forming a polysilicon pad in the DRAM cell manufacturing method characterized in that. The method of claim 7, wherein the insulating layer is formed around the bit line, and the bit line is removed by stacking the bit line conductive layer and the mask oxide, and then removing the mask oxide and the bit line conductive layer of the portion scheduled by the bit line mask process. Forming a spacer oxide on a side of the bit line; 8. The method of claim 7, wherein after applying the second insulating layer, a predetermined pattern mask process is performed to form tunnel-shaped through-holes with a predetermined interval in the word line direction between the second conductive layer and the third conductive layer. A method of manufacturing a DRAM cell, wherein the DRAM cell has a predetermined width so as to remain long in the word line direction. The method of claim 7, wherein when etching the first conductive layer by plasma etching, a third conductive layer pattern formed by a charge storage electrode mask process is used as a mask layer.