JPS60107854A - Capacitor - Google Patents

Capacitor

Info

Publication number
JPS60107854A
JPS60107854A JP21397383A JP21397383A JPS60107854A JP S60107854 A JPS60107854 A JP S60107854A JP 21397383 A JP21397383 A JP 21397383A JP 21397383 A JP21397383 A JP 21397383A JP S60107854 A JPS60107854 A JP S60107854A
Authority
JP
Japan
Prior art keywords
capacitor
film
silicide
substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21397383A
Other languages
Japanese (ja)
Inventor
Noriyuki Sakuma
憲之 佐久間
Taijo Nishioka
西岡 泰城
Kiichiro Mukai
向 喜一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21397383A priority Critical patent/JPS60107854A/en
Publication of JPS60107854A publication Critical patent/JPS60107854A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the capacitor of large capacity occupying a small area by a method wherein insulating films for interelement isolation are provided on the circumferential part of an Si substrate, a lower electrode is formed on the region ranging from the substrate surface to the film edge part exposed between said interelement isolation insulating films, and when the capacitor is formed by providing an upper electrode on the whole area including the lower electrode through the intermediary of a Ta2O5 film, these electrodes are constituted by W, Mo, W-silicide, Mo-silicide and the like. CONSTITUTION:Insulating films 32 for interelement isolation are formed on the circumferential part of an Si substrate 31, a lower electrode 33 of approximately 1,000Angstrom in thickness, consisting of W, Mo, W-silicide, Mo-silicide and the like, is deposited on the region ranging from the surface of the substrate 31, exposed between the insulating film 32, and the film 32. Then, the entire surface including said lower electrode 33 is covered by a Ta2O5 film 34 of approximately 300Angstrom in thickness, and an upper electrode 35 of the same composition as the electrode 33 is coated on the film 34. As a result, an excellent capacitor having the capacitance density of 7.26fF/mum<2> and the characteristics wherein leak current will be maintained at 10<-6>A/cm<2> can be obtained.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は大規模集積回路に係り、特に大規模集積回路の
実現に必要な小面積かつ大容量のキャパシタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to large-scale integrated circuits, and more particularly to small-area, large-capacity capacitors necessary for realizing large-scale integrated circuits.

〔発明の背景〕[Background of the invention]

近年、LSIの高集積化が進んでいる。特にダイナミッ
クメモリ(D−RAM)ではその集積度が1チップ当り
1メガビツト(IMb)のものまで実用化研究が進んで
いる。そのさいの高集積化に伴い個々の素子′は微細化
の一途をたどっている。
In recent years, the integration of LSIs has been increasing. In particular, research into the practical use of dynamic memory (D-RAM) is progressing to the point where the degree of integration is 1 megabit (IMb) per chip. As the integration becomes higher, the individual elements' are becoming increasingly finer.

ダイナミックメモリのメモリセルにおりては、その記憶
作用を行なう電荷積用キャパシタの面積の縮小がIMb
ダイナミックメモリの実現の鍵となってbることか、た
とえば1日経エレクトロニクス誌1983.7.18発
行196項″などによって示されている。
In dynamic memory memory cells, the reduction in the area of the charge product capacitor that performs the storage function is important for IMb.
This is the key to realizing dynamic memory, as shown in, for example, Nikkei Electronics Magazine 1983.7.18, Issue 196''.

同誌に示されているように、IMbダイナミックメモリ
においても、メモリセルは1個のトランジスタと1個の
キャパシタによって$/4’成するととができる。しか
し、このキャパシタには、メモリが信号雑音やα線の入
射による誤動作の発生を防止するため、1個当り少なく
とも60fFの静電容量が必要である。
As shown in the same magazine, even in the IMb dynamic memory, a memory cell can be made up of one transistor and one capacitor at a cost of $/4'. However, each capacitor needs to have a capacitance of at least 60 fF in order to prevent the memory from malfunctioning due to signal noise or incidence of alpha rays.

一方、IMbのメモリセルを約1c4の面積のチップ内
に収めるためには、1個のキャパシタの面積は10μm
2程度以下にする必要がある。
On the other hand, in order to fit the IMb memory cell into a chip with an area of about 1c4, the area of one capacitor is 10μm.
It is necessary to keep it below about 2.

したがって、キャパシタの単位面積当りの静電容量は6
1F/μm2以上である必要がある。
Therefore, the capacitance per unit area of the capacitor is 6
It needs to be 1F/μm2 or more.

ところが、従来のダイナミックメモリでm−られてきた
キャパシタの誘電体の熱酸化シリコンではLSIに適用
するために十分低い欠陥密度を有するためにはその膜厚
を150Å以上にする必要があるとされているが、その
さい容量は21F/μm2以下となり、従来のキャパシ
タではIMbダイナミックメモリの実現は困難である。
However, in order to have a sufficiently low defect density for application to LSI, thermally oxidized silicon, which is the dielectric material of capacitors used in conventional dynamic memories, needs to have a film thickness of 150 Å or more. However, the capacitance is less than 21F/μm2, making it difficult to realize an IMb dynamic memory using conventional capacitors.

したがって、IMbダイナミックメモリを実現するため
に積み上げ!51(S T C: 5tacked c
apactor )や溝型キャパシタ部/’ (CCC
: corrugatedcapaetor cell
 )などが検討されているが、これらのセルに対して以
下に示す短所がある。
Therefore, stack up to realize IMb dynamic memory! 51 (S T C: 5 tacked c
apactor ) and trench capacitor section /' (CCC
: corrugated capetor cell
) are being considered, but these cells have the following disadvantages.

STCでは、 1、キャパシタの電極用の多結晶Siが積層されるため
段差が高く、加工が比較的離しい。
In STC, 1. Polycrystalline Si for capacitor electrodes is laminated, so the steps are high and processing is relatively difficult.

2、上記多結晶Siの距離の合わせマージンが必要で期
待よりは集積度が上らない。
2. A margin for adjusting the distance of the polycrystalline Si is required, and the degree of integration is not as high as expected.

また、CCCでは深溝を形成するため、1、製造工程が
複雑になり、コストの低減が難しも。
In addition, since deep grooves are formed in CCC, the manufacturing process becomes complicated, making it difficult to reduce costs.

2、深溝の端部に応力が集中して転位などの欠陥が生じ
やすい。
2. Stress is concentrated at the end of the deep groove, which tends to cause defects such as dislocations.

3、深溝が近接すると碑の下端部でパンチスルー電流が
流れ蓄積情報を失すがちになる。
3. When the deep grooves are close together, a punch-through current flows at the bottom end of the monument and stored information tends to be lost.

以上のセルの欠点を防ぐためには、やはり下地が10μ
m2の平坦なSi表面に6fF/μm2以上の容量密度
を持つ誘電体も形成することが必要である。また、メモ
リセルが記憶情報を保持するためにはメモリの動作電圧
5vにおいてキャパシタのリーク電流密度は10−’A
/cnl以下であることが必要である。
In order to prevent the above cell defects, the base layer must be 10 μm thick.
It is also necessary to form a dielectric material having a capacitance density of 6 fF/μm 2 or more on a flat Si surface of m 2 . In addition, in order for the memory cell to retain stored information, the leakage current density of the capacitor is 10-'A at a memory operating voltage of 5V.
/cnl or less.

第1図は従来のダイナミックメモリのキャパシタ部の一
断面を示したものである。ここで1はSi基板、2は素
子間分離絶縁膜、3はTa205膜で61F/μm2以
上の容量密度を保つため100Aの膜厚のもの、4はw
t極である。このキャパシタの電流−電圧特性を第2図
に示す。このキャパシタの容量密度は7.51F/μm
2であるが、IMbダイナミックメモリに適用されるた
めには、5Vの動作電圧で10−6A/cd1以下のリ
ーク電流であることが必要である。第1図では5Vのメ
モリの動作電圧にてリーク電流は0.IA/crl程度
でダイナミックメモリに適用することは難しい。したが
って上記W/ T a 205 / S ! 型のキャ
パシタではダイナミックメモリの要求特性を満足できな
い。
FIG. 1 shows a cross section of a capacitor portion of a conventional dynamic memory. Here, 1 is a Si substrate, 2 is an isolation insulating film, 3 is a Ta205 film with a film thickness of 100A to maintain a capacitance density of 61F/μm2 or more, and 4 is w
It is the t-pole. The current-voltage characteristics of this capacitor are shown in FIG. The capacitance density of this capacitor is 7.51F/μm
However, in order to be applied to IMb dynamic memory, it is necessary that the leakage current be less than 10 −6 A/cd1 at an operating voltage of 5 V. In Figure 1, the leakage current is 0.0 at the memory operating voltage of 5V. It is difficult to apply it to dynamic memory at IA/crl level. Therefore, the above W/Ta 205/S! type capacitor cannot satisfy the required characteristics of dynamic memory.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記従来技術の欠点に鑑み、特に高集積
ダイナミックメモリの実現に必要な小面積かつ大容量の
キャパシタを提供することにある。
SUMMARY OF THE INVENTION In view of the above drawbacks of the prior art, it is an object of the present invention to provide a small-area, large-capacity capacitor that is particularly necessary for realizing a highly integrated dynamic memory.

〔発明の概要〕[Summary of the invention]

上記目的を達成するための本発明の構成は、第2の電極
はW、Mo、Wシリサイド、および、MOシリサイドか
らなる群の少なくとも一考によって構成することにある
The structure of the present invention for achieving the above object is that the second electrode is made of at least one of the group consisting of W, Mo, W silicide, and MO silicide.

本発明では平坦なSi表面上に比誘電率の大きいTa2
05膜などを用いたキャパシタを形成するがそのさいS
iとTa205の界面にW、Mo等の高誘点金属あるい
はW、Moのシリサイドを用いることによって、小面積
かつ大容量かつ絶縁耐圧の良好なキャパシタを形成する
ことができる。
In the present invention, Ta2, which has a large dielectric constant, is placed on a flat Si surface.
When forming a capacitor using 05 film etc., S
By using a high-attractive metal such as W or Mo or a silicide of W or Mo at the interface between i and Ta205, a capacitor with a small area, large capacity, and good dielectric strength can be formed.

〔発明の実施例〕[Embodiments of the invention]

示す。3工はSi基板、32は素子間分離絶縁膜、33
は1000人の膜厚のW膜、34は300人の膜厚のT
a205膜、35はW電極である。このキャパシタの容
量密度は7.26fF/μm2である。
show. 3 is a Si substrate, 32 is an isolation insulating film between elements, 33
is a W film with a thickness of 1000 people, and 34 is a T film with a thickness of 300 people.
A205 film, 35 is a W electrode. The capacitance density of this capacitor is 7.26 fF/μm2.

第4図には同キャパシタの電流−1に正特性を示す。FIG. 4 shows a positive characteristic for the current -1 of the same capacitor.

この図よりリーク電流が10−’A/crAでの電圧は
10V以上であり、5vの動作電圧に対して充分なマー
ジンを持つ。したがって本発明によるW/T a 20
s / Wキャパシタによってダイナミックメモリを実
現するに必要なキャパシタを得られることがわかる。
From this figure, when the leakage current is 10-'A/crA, the voltage is 10V or more, which has a sufficient margin for the operating voltage of 5V. Therefore, W/T a 20 according to the invention
It can be seen that the s/W capacitor provides the capacitor necessary to realize a dynamic memory.

ここで、前者のW/ T 3205 (95人)/Si
とW/ T a 20s (300人)/W キャパシ
タの特性を比較すると両者の容量密既はほぼ等しいにも
かかわらず耐圧は前者が2■、後者がIOVであるので
後者のキャパシタは前者のキャパシタの5倍の電荷を蓄
積できることがわかる。ここで耐圧をリーク電流が10
−’ A/c4になる場合の電圧と定義した。このよう
に、誘電体として同じTa205膜を用いているのに特
性の著しい差異の現れる原因は前者のキャパシタはT 
ages を反応性スパッタ法等を用いて酸化性雰囲気
中で形成するためTa21lsとSiの界面に誘電体の
低いSjO*が出来て容量密度を下げており、かつ、S
iがTa205中に拡散しTa205の絶縁性を低下さ
せているものと考えられる。一方、本発明のキャパシタ
ではTa205 形成のさいWの表面には酸化物が形成
されていないし、かつ、Si基板からのSiの拡散を防
いでいると考えられる。また、WとTa205の反応性
は比較的小さいため、上部電極にWなどを用いれば耐熱
性の良好なキャパシタを得ることができる。
Here, the former W/T 3205 (95 people)/Si
and W/Ta 20s (300 people)/W When comparing the characteristics of the capacitors, even though the capacitance density of both is almost the same, the former has a breakdown voltage of 2■ and the latter has IOV, so the latter capacitor is better than the former capacitor. It can be seen that five times as much charge can be stored. Here, the breakdown voltage and leakage current are 10
-' A/c4 was defined as the voltage. In this way, the reason for the remarkable difference in characteristics even though the same Ta205 film is used as the dielectric is that the former capacitor has T
Since SjO* is formed in an oxidizing atmosphere using a reactive sputtering method or the like, SjO* with a low dielectric material is formed at the interface between Ta21ls and Si, lowering the capacitance density.
It is thought that i diffuses into Ta205 and reduces the insulation properties of Ta205. On the other hand, in the capacitor of the present invention, no oxide is formed on the surface of W during the formation of Ta205, and it is thought that this prevents the diffusion of Si from the Si substrate. Furthermore, since the reactivity between W and Ta205 is relatively small, a capacitor with good heat resistance can be obtained by using W or the like for the upper electrode.

本実施例ではキャパシタの電極としてWを用いて説明し
たが、発表者らはW以外に少なくともMO,Wシリサイ
ド+Moシリサイドも同様の効果を得ることができた。
Although this embodiment has been described using W as the electrode of the capacitor, the presenters were able to obtain similar effects using at least MO, W silicide + Mo silicide, in addition to W.

また、絶縁膜として酸化タンタルの他に、酸化ニオビウ
ム、酸化ハフニウム、酸化チタン、酸化アルミニウム、
窒化シリコンなどを用めても良い。
In addition to tantalum oxide, niobium oxide, hafnium oxide, titanium oxide, aluminum oxide,
Silicon nitride or the like may also be used.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、IMbダイナミックメモリの実現に必
要な小面積かつ大容量のキャパシタを平坦なコンタクト
ホール上に形成できる。
According to the present invention, a small-area, large-capacity capacitor required for realizing an IMb dynamic memory can be formed on a flat contact hole.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のキャパシタの断面図、第2図は従来のキ
ャパシタの電流−電圧特性、第3図は本発明の一実施例
としてのキャパシタの断面図、第4図は本発明のキャパ
シタの電流−4EE特性である。 1.31・・・Si基板、2,32・・・素子間分離絶
縁膜、3・・・Ta205膜、4・・・電極、33・・
・下部W電第 1 口 / 第3 図 5 夏 2 図 Y4− 図
Fig. 1 is a cross-sectional view of a conventional capacitor, Fig. 2 is a current-voltage characteristic of a conventional capacitor, Fig. 3 is a cross-sectional view of a capacitor as an embodiment of the present invention, and Fig. 4 is a cross-sectional view of a capacitor of the present invention. This is a current-4EE characteristic. 1.31...Si substrate, 2,32...Inter-element isolation insulating film, 3...Ta205 film, 4...electrode, 33...
・Lower W power station 1st/3rd Figure 5 Summer 2 Figure Y4- Figure

Claims (1)

【特許請求の範囲】 1、第1の電極/絶縁膜/第2め電極/基板がそれぞれ
積層されているキャパシタにおいて、該第2の電極はW
、Mo、Wシリサイド、およびMOシリサイドからなる
群の少なくとも一考によって構成されていることを特徴
とするキャパシタ。 2、特許請求の範囲第1項において、前記第1の電極は
W、Mo、Wシリサイド、およびMOシリサイドからな
る群の少なくとも一考によって構成されていることを特
徴とするキャパシタ。 3、特許請求の範囲第1項において、前記絶縁膜は酸化
タンタル、酸化ニオビウム、酸化ハフニウム、酸化チタ
ン、酸化アルミニウム、窒化シリコンによって構成され
ていること全特徴とするキャパシタ。 4、特許請求の範囲第1項において、前記基板はSjで
あること全特徴とするキャパシタ。
[Claims] 1. In a capacitor in which a first electrode/insulating film/second electrode/substrate are laminated, the second electrode is made of W.
, Mo, W silicide, and MO silicide. 2. The capacitor according to claim 1, wherein the first electrode is made of at least one member of the group consisting of W, Mo, W silicide, and MO silicide. 3. The capacitor according to claim 1, wherein the insulating film is made of tantalum oxide, niobium oxide, hafnium oxide, titanium oxide, aluminum oxide, or silicon nitride. 4. The capacitor according to claim 1, wherein the substrate is Sj.
JP21397383A 1983-11-16 1983-11-16 Capacitor Pending JPS60107854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21397383A JPS60107854A (en) 1983-11-16 1983-11-16 Capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21397383A JPS60107854A (en) 1983-11-16 1983-11-16 Capacitor

Publications (1)

Publication Number Publication Date
JPS60107854A true JPS60107854A (en) 1985-06-13

Family

ID=16648126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21397383A Pending JPS60107854A (en) 1983-11-16 1983-11-16 Capacitor

Country Status (1)

Country Link
JP (1) JPS60107854A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258670A (en) * 1985-09-09 1987-03-14 Hitachi Ltd Manufacture of semiconductor device
JPS62133748A (en) * 1985-12-05 1987-06-16 Matsushita Electronics Corp Manufacture of semiconductor device
JPS62195133A (en) * 1985-12-05 1987-08-27 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Semiconductor device
JPH0260157A (en) * 1988-08-25 1990-02-28 Nec Corp Semiconductor device
JPH02284470A (en) * 1989-04-26 1990-11-21 Hitachi Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758349A (en) * 1980-09-24 1982-04-08 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS57167669A (en) * 1981-03-27 1982-10-15 Fujitsu Ltd Capacitor and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758349A (en) * 1980-09-24 1982-04-08 Semiconductor Energy Lab Co Ltd Semiconductor device
JPS57167669A (en) * 1981-03-27 1982-10-15 Fujitsu Ltd Capacitor and manufacture thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258670A (en) * 1985-09-09 1987-03-14 Hitachi Ltd Manufacture of semiconductor device
JPS62133748A (en) * 1985-12-05 1987-06-16 Matsushita Electronics Corp Manufacture of semiconductor device
JPS62195133A (en) * 1985-12-05 1987-08-27 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Semiconductor device
JPH0260157A (en) * 1988-08-25 1990-02-28 Nec Corp Semiconductor device
JPH02284470A (en) * 1989-04-26 1990-11-21 Hitachi Ltd Semiconductor device

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