JPH0330467A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To lessen high melting metal in scattering at the processing of a gate electrode so as to enable the improvement of a MISFET and other semiconductor elements in characteristics by a method wherein the gate electrode is formed into a three-layered structure composed of a polycrystalline silicon film, a high melting point metal silicide film, and a polycrystalline silicon laminated in this order. CONSTITUTION:In a semiconductor circuit device, where a gate electrode, a drain electrode, and a source electrode are formed on a semiconductor substrate to constitute a MISFET 4, the gate electrode concerned is formed into a three- layered structure composed of a polycrystalline silicon film 11, a high melting point metal silicide film 2, and a polycrystalline silicon film 13 laminated in this order. For instance, in a Bi.CMOS semiconductor integrated circuit device on which a MISFET 4 and a bipolar transistor are formed, the gate electrode of the MISFET element 4 is formed as mentioned above. By this setup, the high melting point metal contained in the high melting point metal silicide is lessened in scattering at the processing of the gate electrode and in a following manufacturing process, so that a formed semiconductor element can be restrained from being contaminated and consequently improved in performance.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to metal
or 3emiconductor) Regarding semiconductor integrated circuit devices configured with FETs, especially MISFETs
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device that can improve the characteristics of a semiconductor element formed when a bipolar transistor and a bipolar transistor are formed on the same semiconductor substrate.

[Prior Art] As a semiconductor integrated circuit device in which a MISFET is configured, a semiconductor region and an impurity diffusion layer are formed on a semiconductor substrate, and polycrystalline silicon (Poly-crystalline silicon) is formed, for example.
A gate electrode is formed by stacking a gate layer such as a Si) film, and a drain electrode and a source electrode are formed by stacking a wiring layer such as aluminum (Ai') on an impurity diffusion layer. There is.

It is generally said that higher integration and higher speed of semiconductor integrated circuit devices are achieved by miniaturization of semiconductor elements formed on semiconductor substrates.

For example, in MOS memory, the high resistance value of the gate electrode formed from a polycrystalline silicon film is a major factor that hinders high integration, miniaturization, and speedup. metal silicide is used.

Further, polycrystalline silicon films are also required from the viewpoint of direct contact with semiconductor substrates and stability of MO3 characteristics. Therefore, for example,
As described in Publication No. 3-281456, MISF
The gate electrode structure of the ET is formed in a two-layer structure in which the first layer is a polycrystalline silicon film and the second layer is a high melting point metal silicide film such as tungsten silicide (WS12).

[Problems to be Solved by the Invention] However, in the conventional technology as described above, the high melting point metal of the high melting point metal silicide film is blown off during gate electrode processing and in the subsequent manufacturing process, and it adheres to the semiconductor substrate. There is a drawback that the surface recombination level increases due to contamination by the attached high melting point metal. Therefore, in bipolar transistors, the current amplification factor decreases due to an increase in recombination current, and in MISFETs, there is a problem that junction leakage current between the well and drain increases.

Furthermore, even when an insulating film such as SiO is laminated on the surface of a high melting point metal silicide film, although the scattering of the high melting point metal is reduced, when processing the gate electrode, the laminated insulating film is first processed. This is a two-step process in which the polycrystalline silicon film is then processed, which poses the problem of complicating the manufacturing process. In this case, there is also the problem that the step of the gate electrode itself is increased, which greatly affects subsequent processing steps.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device in which scattering of high-melting point metal during processing of electrodes is reduced and the characteristics of MISFETs and other semiconductor elements can be improved. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device constituting a MISFET in which a gate electrode, a drain electrode, and a source electrode are formed on a semiconductor substrate, wherein the gate bridge is made of polycrystalline silicon from a lower layer. It is formed in a three-layer structure consisting of a film, a high melting point metal silicide film, and a polycrystalline silicon film.

Further, the MISFET and the bipolar transistor are formed on the same semiconductor substrate.

[Function] According to the semiconductor integrated circuit device described above, the gate electrode of the MISFET is formed in the three-layer structure of the polycrystalline silicon film, the high melting point metal silicide film, and the polycrystalline silicon film from the bottom layer, so that the gate electrode is formed in the top layer. The refractory metal silicide film can be covered with the stacked polycrystalline silicon film.

Thereby, it is possible to reduce scattering of the high melting point metal of the high melting point metal oxide film during processing of the gate electrode and subsequent manufacturing steps.

Furthermore, when a MISFET and a bipolar transistor are formed on the same semiconductor substrate, the influence of the bipolar transistor board, which is particularly sensitive to contamination, is reduced, making it possible to form a bipolar transistor with ideal characteristics. can.

Furthermore, when processing the gate electrode, the polycrystalline silicon film and the refractory metal silicide film can be processed using the same etching gas, so that the gate electrode can be formed by simultaneous processing.

[Example 1] Fig. 1 is a sectional view showing a gate electrode of a semiconductor integrated circuit device according to an embodiment of the present invention, and Fig. 2 is a sectional view showing a main part of a part of the semiconductor integrated circuit device according to this embodiment. be.

First, the configuration of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.

The semiconductor integrated circuit device of this embodiment is, for example, MISFE.
T and B i where the bipolar transistor is formed
-CM OS (Bipolar Complemen)
A p-type buried semiconductor region 2 and an n-type buried semiconductor region 3 are formed on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon (Sl).
is formed, and an n-type M+ is formed on the main surface of the p-type buried semiconductor region 2.
5FET element 4, np on the main surface of the n-type buried semiconductor region 3
An n-type bipolar transistor element 5 is configured.

The n-type MISFET element 4 and the npn-type bipolar transistor element 5 are separated from each other by the element isolation insulation 1I5i! 6
, p-type channel stopper region #c7, p-type well region 8
The region is defined by and n-type well region 9 and is electrically isolated from other regions.

The n-type MISFET element 4 has an MIS structure and a source
The MIS structure is formed by a drain region, and as shown in FIG. The gate electrode is formed in a three-layer structure by a high melting point metal silicide film 12 such as tungsten silicide (WSi□) and a polycrystalline silicon film 13. On the other hand, the source and drain regions of the n-type MISFET element are defined by the gate electrode. n-
n-type semiconductor region 14 and an n-type semiconductor region 16 defined by the sidewall spacer 15 on the side wall of the gate electrode.
It is made up of.

The npn type bipolar transistor element 5 has a collector,
The collector region is formed by the base and emitter regions, and the collector region is an n″″ formed on the n″ type buried semiconductor region 3.
It is constituted by a type semiconductor region 17 and an n-type semiconductor region 18.

The base region of the npn-type bipolar transistor element 50 is constituted by the p-type semiconductor region 19, and is formed on the main surface of the n-type well region Fa9, which is the collector region. is stipulated.

Furthermore, a base extraction electrode 20 formed of a polycrystalline silicon film is connected to the p-type semiconductor region 19 of the base region. A p-type impurity is introduced into this polycrystalline silicon film to reduce the resistance value.

Further, the emitter region of the npn type bipolar transistor element 5 is constituted by an n" type semiconductor region °21,
It is formed at the center of the main surface of the p-type semiconductor region 19, which is the base region.

Further, in the n° type semiconductor region 21 of the emitter region, an emitter lead-out electrode 22 formed of a polycrystalline silicon film is connected to a connection hole defined by a sidewall spacer 23 formed on the side wall of the base lead-out electrode 20. connected through. And, this emitter extraction electrode 22 has
An n-type impurity is introduced.

Moreover, the side wall spacer 23 is an n-type MISFE
It is formed simultaneously with the sidewall spacer 15 of the T element 4 by self-alignment.

The source/drain regions of the n-type MISFET element 4 and the emitter region and collector region of the npn-type bipolar transistor element 5 configured as described above are connected to each other through connection holes formed by opening the interlayer insulating film 24. A lead-out wiring 25, an emitter lead-out wiring 26, and a collector lead-out wiring 27 are connected. These lead-out wirings 25, 26, and 27 are made of, for example, aluminum, silicon (Sl), or copper (C).
It is made of an aluminum alloy containing additives such as u).

Next, the operation of this embodiment will be explained.

In the semiconductor integrated circuit device of this embodiment configured as described in Moeki, the gate electrode of the n-type MISFET element 4 is
As shown in FIG. 1, it is formed into a three-layer structure of a polycrystalline silicon film 111, a high melting point metal silicide film 12, and a polycrystalline silicon film 13, and the gate electrode is processed by laminating the polycrystalline silicon film 13 on the top layer. This reduces scattering of high-melting point metal during the manufacturing process and subsequent manufacturing processes, and contamination of the semiconductor integrated circuit device is significantly suppressed. As a result, the recombination current in the semiconductor element formed on the semiconductor substrate, particularly the npn bipolar transistor element 5, is reduced.
It is possible to form an npn type bipolar transistor element 5 that can reduce variations in the current amplification factor of the bipolar transistor element 5 and at the same time obtain a high current amplification factor over a wide collector current range.

Furthermore, even if the polycrystalline silicon film 13 is laminated as the top layer, a gate electrode having the same cross-sectional area as a conventional gate electrode can be formed by adjusting the thickness of the lower polycrystalline silicon film 11. As a result, it is possible to form an n-type MISFET element 4 having the same level difference as the conventional one and having the same low resistance.

Furthermore, when processing the gate electrode, it is possible to simultaneously process the polycrystalline silicon films 13 and 11 laminated as the top and bottom layers and the high melting point metal silicide film 12 as the intermediate layer using the same etching gas. The gate electrode can be formed in the same manufacturing process as conventional ones.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above, a case has been described in which the device is a Bi-CMO3 semiconductor integrated circuit device in which an n-type MISFET element 4 and an npn-type bipolar transistor element 5 are formed. However, the present invention is not limited to the above embodiment, and・C
The present invention can be widely applied to semiconductor integrated circuit devices configured with MISFETs such as MOS memories, and is particularly effective for semiconductor integrated circuit devices configured with bipolar transistors that are sensitive to contamination. In this case, for example, M
When applied to a semiconductor integrated circuit device of an OS memory, wiring resistance is reduced, miniaturization and high density integration are possible, and at the same time, the semiconductor integrated circuit device can be manufactured in a clean process.

Furthermore, regarding the semiconductor integrated circuit device of this embodiment, p-
n-type MISFET Utsuko 4 and np type semiconductor substrate 1
Although the case where the n-type bipolar transistor element 5 is formed has been described, the present invention is not limited to the above embodiment, and for example, it is also possible to form the semiconductor element on an n-type semiconductor substrate. It is also applicable to semiconductor integrated circuit devices.

Furthermore, regarding the gate electrode of the n-type MISFET element 4, although the case where tungsten silicide (WSi2) was exemplified as the high melting point metal silicide film 12 was explained, it is not limited to this, and for example, molybdenum (Mo), molybdenum (Mo),
It is also widely applicable to high melting point metal silicide films such as titanium (Ti) and tantalum (Ta).

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

(1) The gate electrode of the MISFET is formed in a three-layer structure consisting of a polycrystalline silicon film, a high-melting point metal silicide film, and a polycrystalline silicon film from the bottom. Since it can be coated with a melting point metal silicide film, it is possible to significantly suppress the effects of high melting during processing of the gate electrode and subsequent manufacturing steps and contamination on the formed semiconductor element.

(2), Item (1) reduces the risk of blowing out the high melting point metal on which the gate electrode of the MISFET is formed, making it possible to manufacture MISFETs and other semiconductor devices such as bipolar transistors in a clean manufacturing process. Therefore, it is possible to improve the performance of the formed semiconductor element. In particular, when a MISFET and a bipolar transistor are formed on the same semiconductor substrate, the influence of contamination on the bipolar transistor is reduced, so that a bipolar transistor with ideal characteristics can be formed.

(3) According to (1) and (2) above, a high-performance semiconductor element can be formed, so that a high-performance, highly reliable semiconductor integrated circuit device with small variations in characteristics can be obtained.

(4) According to (1) above, in the gate electrode processing process, it is possible to simultaneously process a polycrystalline silicon film, a refractory metal silicide film, and a doe-etching gas, so that semiconductor integration can be achieved in the same manufacturing process as before. It is possible to manufacture circuit devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a gate electrode of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part showing a part of the semiconductor integrated circuit device according to the present embodiment. ■... Semiconductor substrate (p-type), 2... Buried semiconductor region (p" type), 3... Buried semiconductor region (n" type), 4
・-- MISFET element (n type), 5... Bipolar transistor element (npn type), 6... Inter-element isolation insulating film, 7... Channel stopper region (p type), 8...
- Well region (p-type), 9... Well region (n-type), 10... Gate oxide film, 11... Polycrystalline silicon film, 12... High melting point metal silicide film, 13. ...Polycrystalline silicon film, 14...Semiconductor region (n-type), 15...
・Side wall spacer, 16...semiconductor region (n
” shape), 17... semiconductor region (n゛ shape), 18...
Semiconductor region (n” type), 19... semiconductor region (p type)
, 20... Base extraction electrode, 21... Semiconductor region (n'' type), 22... Emitter extraction electrode, 23...
・Side wall spacer, 24... interlayer insulating film, 2
5... Source/drain lead-out wiring, 26... Emitter lead-out wiring, 27... Collector lead-out wiring.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device constituting a MISFET in which a gate electrode, a drain electrode, and a source electrode are formed on a semiconductor substrate, wherein the gate electrode is formed of a polycrystalline silicon film, a high melting point metal, etc. from the bottom layer. A semiconductor integrated circuit device characterized in that it is formed in a three-layer structure of a silicide film and a polycrystalline silicon film. 2. The semiconductor integrated circuit device according to claim 1, wherein the MISFET and the bipolar transistor are formed on the same semiconductor substrate.