JPH0794596A - Semiconductor integrated circuit device and fabrication thereof - Google Patents

Abstract

PURPOSE:To shorten the gate length of a stack DRAM and to decrease the resistance through silicification of titanium. CONSTITUTION:The inventive stack DRAM is essentially different from conventional stack DRAM in the following points. (1). Titanium silicide 263 is deposited on the surface in the N-type heavily doped region 273 of a MOS transistor for selection. (2). Titanium silicide 264 is deposited on a common electrode 23 of polysilicon at a capacitor part. In other words, the second storage electrode at the capacitor part has a double layer structure of a polysilicon layer and a silicide layer of high melting point metal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a one-transistor type dynamic RAM and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a one-transistor type dynamic RAM, a stack type dynamic RAM (hereinafter referred to as a stack type dynamic RAM) is provided in which an extraction electrode is provided on one impurity diffusion layer of a selection MOS type transistor and electric charges accumulated in this transistor are extracted from the extraction electrode. "Stack type DRAM") (for example, Japanese Patent Laid-Open No. 3-292767).

FIGS. 7A, 7B and 8A,
(B) is a diagram for explaining a conventional example of a method of manufacturing such a stack type DRAM, respectively.

[0004] Field oxide films 202 ₁ to 202 _3, 7
As shown in (A), it is formed at a predetermined position on the P-type silicon substrate 201. Subsequently, gate oxide films 203 ₁ and 203 ₂ having a film thickness of 200 Å are formed between the field oxide film 202 ₁ and the field oxide film 202 ₂ on the P-type silicon substrate 201 and between the field oxide film 202 ₂ and the field oxide film 202 _{3 respectively.} Is formed in the region between and.

After that, a polycrystalline silicon film having a thickness of 3000 Å is formed on the entire surface of the P-type silicon substrate 201,
By performing phosphorus diffusion, this polycrystalline silicon film becomes an N-type conductive layer. Subsequently, by the polycrystalline silicon film is etched by photo-etching, a gate electrode 204 serving as a word line is formed in the central portion of the region where the gate oxide film 203 illustrated _second right is formed, The gate electrode 205 of the transistor in the peripheral circuit
Is formed in the center portion of the gate oxide film 203 ₁ of the left side is formed regions.

[0006] Then, a gate electrode 204, 205 and the field oxide film 202 _{1-202 3} as a mask, the energy 40K
Phosphorus is ion-implanted under the conditions of eV and a dose amount of 2 × 10 ¹³ cm ⁻² , whereby four N-type low concentration regions 20 are formed.
6 _{1-206 4,} between the field oxide film 202 ₁ and the gate electrode 205, between the gate electrode 205 and the field oxide film 202 _2,
It is formed in a self-aligned manner between the field oxide film 202 ₂ and the gate electrode 204 and between the gate electrode 204 and the field oxide film 202 ₃ . Then, a first silicon oxide film 207 having a thickness of 1500 Å is formed on the entire surface of the P-type silicon substrate 201 by C.
It is formed by the VD method.

After that, the first silicon oxide film 207 is anisotropically etched to leave only the first silicon oxide film 207 on the side wall of the gate electrode 205 and the side wall of the gate electrode 204, so that FIG. as shown in), four side walls 208 _{1-208 4} is formed. Subsequently, a gate electrode 204, 205 and side walls 208 _{1-208 4} and the field oxide film 202 _{1-202 3} as a mask, the energy 70K
By implanting arsenic under the conditions of eV and a dose amount of 5 × 10 ¹⁵ cm ^-2 , four N-type high concentration regions 20 are formed.
9 _{1-209 4,} field oxide films 202 ₁ and the side walls 20
8 ₁ and between the side walls 208 ₂ and the field oxide film 202 ₂
Between the field oxide film 202 ₂ and the side wall 208 ₃ and between the side wall 208 ₄ and the field oxide film 202 ₃
Are formed in a self-aligned manner between and. Then, the film thickness 300
The 0Å second silicon oxide film 210 is the P-type silicon substrate 201.
850 ° C after being formed on the entire upper surface by the CVD method
Annealing is performed for 40 minutes in the nitrogen atmosphere. Subsequently, the second silicon oxide film 210 by being etched by a photo-etching method using a mask member 211, the contact hole 212 is shown left N-type high-concentration region 209 ₄
Formed on.

After that, the mask material 211 is removed, and a polycrystalline silicon layer having a film thickness of 3000 Å is formed on the P-type silicon substrate 201.
After being formed on the entire upper surface by the CVD method, the polycrystalline silicon layer is made into an N-type conductor layer by phosphorus diffusion. Subsequently, this polycrystalline silicon layer is etched by the photoetching method, so that the extraction electrode 213 is formed as shown in FIG.
(A), a is formed so as to be electrically connected to the N type high concentration region 209 ₄ via a contact hole 212.

After that, the silicon nitride film having a film thickness of 80 Å is C
After being formed by the VD method, a silicon oxide film having a film thickness of 10 Å is formed on the surface of the silicon nitride film by a heat treatment for 15 minutes in an oxygen atmosphere at 900 ° C., so that the capacitor film 214 is formed on the extraction electrode 213. And formed on the periphery thereof. Subsequently, a polycrystalline silicon layer having a film thickness of 1500 Å is grown by the CVD method, and then the polycrystalline silicon layer is made into an N-type conductor layer by phosphorus diffusion. Subsequently, the polycrystalline silicon layer is etched into a predetermined pattern by a photo-etching method to form a common electrode 215 which serves as a counter electrode of the capacitor.

After that, a film thickness 50 containing boron and phosphorus is obtained.
After the third silicon oxide film 216 of 00Å is formed on the entire surface of the P-type silicon substrate 201 by the CVD method, 90
It is flattened by heat treatment for 20 minutes in a nitrogen atmosphere at 0 ° C. Then, as shown in FIG. 8B, a predetermined portion of the third silicon oxide film 216 is removed by a photoetching method, so that a contact hole for connecting a signal wiring is formed.
217, while being opened from the leftward on the second N-type high-concentration region 209 _3, two contact holes 218 ₁ for the peripheral portion wiring connection, 218 _2, the illustrated right N-type high concentration region 209 ₁ An opening is formed on the N-type high concentration region 209 _{2 which} is the second from the top and the right in the figure. Then, the aluminum film with a film thickness of 9000Å is
A signal wiring 219 and two peripheral wirings 220 ₁ and 220 ₂ are formed by being formed on the entire surface of the type silicon substrate 201 by a sputtering method and then etched into a predetermined pattern to form a stacked DRAM. Will be completed.

As the one-transistor dynamic RAM, in addition to the above-mentioned stack type DRAM, a trench dynamic RAM (hereinafter referred to as "trench type DRA") in which a groove formed by etching a substrate is used as an electrode
"M". ) Is also available.

FIGS. 9A, 9B and 9C respectively show
It is a figure for explaining one conventional example of a manufacturing method of such a trench type DRAM.

[0013] A field oxide film 302 _{1-302 3,} 9
As shown in (A), it is formed at a predetermined position on the P-type silicon substrate 301. Then, grooves 303, the left side of the field oxide film ₃₀₂₃ of the left side of the P-type silicon substrate 301, is formed by photo-etching. Subsequently, phosphorus is selectively ion-implanted around the trench 303 under the conditions of energy of 70 KeV and dose amount of 5 × 10 ¹³ cm ⁻² , whereby the N-type impurity region 304 is formed.

After that, the silicon nitride film having a film thickness of 80 Å is C
After being formed by the VD method, a silicon oxide film having a film thickness of 10Å is formed on the surface of the silicon nitride film by a heat treatment for 10 minutes in an oxygen atmosphere at 900 ° C. Formed on the surface of 304. Then, after the polycrystalline silicon layer is grown by the CVD method, the polycrystalline silicon layer is made into an N-type conductor layer by phosphorus diffusion. Then, the polycrystalline silicon layer is etched into a predetermined pattern by a photoetching method using the mask material 306, thereby forming a common electrode 307 serving as a counter electrode of the capacitor.

After that, as shown in FIG. 9B, a first silicon oxide film 308 is formed on the upper portion of the common electrode 307 and its side wall, and then the gate oxide film 30 having a film thickness of 200 Å is formed.
9 ₁ and 30 9 ₂ are provided in a predetermined region between the field oxide film 302 ₁ and the field oxide film 302 ₂ on the P-type silicon substrate 301 and a predetermined region between the field oxide film 302 ₂ and the field oxide film 302 ₃ . Formed in the area.

After that, a polycrystalline silicon film having a film thickness of 3000 Å is formed on the entire surface of the P-type silicon substrate 301 by the CVD method, and then phosphorus diffusion is performed, so that the polycrystalline silicon film becomes an N-type conductive layer. To be done. Then, the polycrystalline silicon film is etched by a photoetching method, so that the gate electrode 310 to be a word line is
Together is formed on the gate oxide film 309 illustrated _second right,
The gate electrode 315 of the transistor of the peripheral circuit is formed on the gate oxide film 309 ₁ of the left side. Subsequently, the silicon oxide film 308 gate electrode 310, 311 and the field oxide film 302 _{1-302 3} as a mask, under the conditions of energy 40KeV and a dose of 2 × 10 ¹³ cm ^-2, the phosphorus is ion-implanted the three N-type low concentration region 312 _{1-312 3}
Are formed in a self-aligned manner between the field oxide film 302 ₁ and the gate electrode 311, between the gate electrode 311 and the field oxide film 302 _2, and between the field oxide film 302 ₂ and the gate electrode 310.

After that, a silicon oxide film having a thickness of 1500 Å is formed on the entire surface of the P-type silicon substrate 301 by the CVD method, and then this silicon oxide film is anisotropically etched to form side walls of the gate electrode 311 and the gate electrode 310. by being only left on the side walls of the four side walls 313 ₁
～313 ₄ is formed. Next, a titanium film with a film thickness of 800Å
314 is formed on the entire surface of the P-type silicon substrate 301 by the sputtering method.

[0018] After that, by in a nitrogen atmosphere at 700 ° C. is 10 minutes anneal is performed, the four titanium silicide film 315 _{1-315 4,} as shown in FIG. 9 (C), in direct contact with the titanium film 314 N-type low concentration region 312 it is _{1-312 3}
After being formed on the gate electrode 310 on the upper side and the right side in the figure, the unreacted titanium film 314 is removed. This allows
N-type low concentration region 312 _{1-312 3} and the low resistance of the gate electrode 310 as a word line can be reduced. Then, the gate electrode 31
0,311 a sidewall 313 _{1-313 4} and the field oxide film
302 as _{1-302 3} and silicon oxide film 308 a mask, under the conditions of energy 70KeV and a dose of 5 × 10 ¹⁵ cm ^-2, by arsenic is ion-implanted, three N
The type high concentration region 316 _{1-316 3,} between the field oxide film 302 ₁ and the side walls 313 _1, and between the field oxide film 302 ₂ and the sidewall 313 _third sidewall 313 ₂ and the field oxide film 302 ₂ Formed in a self-aligned manner.

After that, a second silicon oxide film 317 containing boron and phosphorus is formed on the entire surface of the P-type silicon substrate 301 by the CVD method, and then heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 10 minutes. Be flattened by. Subsequently, the second silicon oxide film 317 of a predetermined portion by being removed by photo-etching, with the contact holes for signal wires connected is opened on the N-type high concentration region 316 ₃ shown left, 2 One of the contact holes for the peripheral portion wiring connection is opened N type illustrated right from the high concentration region 316 ₁ and shown right on the second N-type high-concentration region 316 _2. continue,
Aluminum film with a thickness of 9000Å is a P-type silicon substrate
The signal wiring 31 is formed on the entire surface of 301 by sputtering and then etched into a predetermined pattern.
8 and two peripheral portions wiring 319 _1, 319 ₂ is formed, a trench-type DRAM is completed.

[0020]

The two types of structures of the conventional one-transistor type dynamic RAM described above are for ensuring the maximum area of the capacitance portion in a fine memory cell region. A stack type DRAM has a lead electrode extended to the upper side of one of the impurity diffusion layers of the selection MOS type transistor to secure the area, and a trench type D has a groove formed in the silicon substrate to secure the area.
RAM.

Stack type DRAM and trench type DR
Comparing AM, stacked DRAM is
Since the capacitance portion is formed after forming the impurity diffusion layers to be the source region and the drain region of the S-type transistor, for the purpose of forming an insulating film between this transistor and the capacitance portion, and phosphorus diffusion and capacitance film formation of the capacitance portion. However, it is difficult to reduce the gate length of the selection MOS transistor as compared with the trench type DRAM which does not require these heat treatments. On the other hand, in the trench type DRAM, on the impurity diffusion layer and the upper part of the gate electrode, titanium silicide is formed to reduce the resistance, but there is a problem that it cannot be applied to the stack type DRAM which takes a long heat treatment time for the following reason. . (1) Since the titanium silicide layer is thermally unstable, the layer resistance of titanium silicide is as shown in FIG.
It increases as the heat treatment time increases. (2) When the heat treatment time becomes long, the interface resistance between the titanium silicide layer and the N-type diffusion layer increases, and the characteristics of the triode region of the transistor deteriorate, as shown in FIG. 10B.

In the trench type DRAM, it is impossible in principle to detect the end point of the etching for forming the groove in the silicon substrate, and it is difficult to control the depth and shape of the groove. Further, since all the charges in the capacitance portion are accumulated in the N-type impurity region formed around the groove via the capacitance film, the charges generated in the silicon substrate due to the incidence of alpha rays can easily be stored in the capacitance portion. Reachable,
There is a problem that the frequency of causing loss of stored information is higher than that of a stack DRAM.

It is an object of the present invention to provide a semiconductor integrated circuit device relating to a stack type DRAM and a method of manufacturing the same for reducing the gate length and reducing the resistance by using titanium silicide.

[0024]

A semiconductor integrated circuit device according to the present invention comprises a low-concentration impurity diffusion layer of another conductivity type and a high-concentration impurity diffusion layer of another conductivity type formed on a semiconductor substrate of one conductivity type. Select MOS transistor having a layer and a gate electrode, a first insulating film formed on the low-concentration impurity diffusion layer and the gate electrode, and a first insulating film formed by opening the first insulating film. A first storage electrode electrically connected to the low-concentration impurity diffusion layer through a first contact hole;
A second storage electrode formed on the first storage electrode via a capacitor insulating film and having a two-layer structure of a polycrystalline silicon layer and a refractory metal silicide layer; and a second storage electrode on the second storage electrode. And a second insulating film formed on the high-concentration impurity diffusion layer and a second contact hole formed by opening the second insulating film to electrically connect with the high-concentration impurity diffusion layer. A silicide of refractory metal is formed on the surface of the high-concentration impurity diffusion layer including the connected signal wiring.

Here, the impurity concentration of the high concentration impurity diffusion layer may be 10 ²⁰ cm ^-3 or more, and the impurity concentration of the low concentration impurity diffusion layer may be 10 ¹⁹ cm ^-3 or less.

Further, the impurity concentration of the polycrystalline silicon layer forming the second storage electrode may be 10 ¹⁸ cm ^-3 or more.

The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a first step of forming a gate electrode of a MOS transistor for selection on a semiconductor substrate of one conductivity type, and another conductivity type in the semiconductor substrate. Second low-concentration impurity region and a low-concentration impurity diffusion layer of another conductivity type, which becomes a source region or a drain region of the selection MOS type transistor, sandwiching the gate electrode, and on the semiconductor substrate. A third step of forming a first insulating film, a fourth step of opening the first insulating film to form a first contact hole on the low concentration impurity diffusion layer, A fifth step of forming a first storage electrode electrically connected to the low-concentration impurity diffusion layer through a first contact hole, and a step of forming a capacitor insulating film on the first storage electrode. Process 6 and the capacity A seventh step of forming a polycrystalline silicon layer forming a second storage electrode on the insulating film, and anisotropically etching the first insulating film using the polycrystalline silicon layer as a mask to perform the low-temperature etching. An eighth step of exposing the surface of the concentration impurity region and leaving the first insulating film on the side wall of the gate electrode on the side of the low concentration impurity region;
A ninth step of forming a refractory metal layer on the semiconductor substrate, and a heat treatment to convert the exposed surface of the low-concentration impurity region and the surface of the polycrystalline silicon layer into refractory metal silicide, A tenth step of selectively removing the high-melting-point metal layer; and a high-concentration impurity diffusion layer of another conductivity type, which becomes a drain region or a source region of the selection MOS type transistor, in the low-concentration impurity region. And an eleventh step of forming.

Here, instead of the ninth step to the eleventh step, the selection M is formed in the low-concentration impurity region.
A twelfth step of forming a high-concentration impurity diffusion layer to be a drain region or a source region of an OS-type transistor, a thirteenth step of forming a refractory metal layer on the semiconductor substrate, and a heat treatment to form the high-concentration impurity layer. First, a refractory metal silicide is formed on the surface of the impurity diffusion layer and the surface of the polycrystalline silicon layer, and then the refractory metal layer is selectively removed.
4 steps may be included.

[0029]

In the semiconductor integrated circuit device of the present invention, the selection MO
Since the N-type high-concentration region is not formed in the impurity diffusion layer electrically connected to the first storage electrode of the S-type transistor, one of the source region and the drain region of the selection MOS type transistor has a shallow junction, The gate length can be shortened. Further, by making the second storage electrode a double structure of polycrystalline silicon and a silicide of a refractory metal,
The resistance of the second storage electrode can be reduced, a more stable potential can be supplied, and the margin for the potential fluctuation of the second storage electrode at the time of reading / writing information can be improved. Furthermore, M for selection
By siliciding one surface of the source region and the drain region of the OS type transistor,
The speed of the S-type transistor can be increased.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the second storage electrode can have a double structure of polycrystalline silicon and a silicide of a refractory metal, so that the second storage electrode has a low structure. The resistance can be made, a more stable potential can be supplied, and the margin against the potential fluctuation of the second storage electrode at the time of reading / writing information can be improved. Further, by siliciding one surface of the source region and the drain region of the selection MOS type transistor, the speed of the selection MOS type transistor can be increased. Further, since the source region and the drain region of the selection MOS type transistor are formed after the formation of the capacitance portion, the heat treatment after the formation of the source region and the drain region of the selection MOS type transistor can be reduced and the gate length can be shortened. Further, since the heat treatment after the formation of the refractory metal silicide can be reduced, a stable refractory metal silicide can be formed.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a vertical structure of a stack type DRAM which is a first embodiment of a semiconductor integrated circuit device of the present invention.

The stack type DRAM of this embodiment is essentially different from the above-mentioned conventional stack type DRAM in the following points. (1) N-type high-concentration region 2 of selection MOS-type transistor
A titanium silicide film 26 ₃ is formed on the surface of 7 ₃ . (2) A titanium silicide film 26 ₃ is formed on the common electrode 23 made of polycrystalline silicon in the capacitor portion. That is, the second storage electrode of the capacitor portion has a two-layer structure of a polycrystalline silicon layer and a refractory metal silicide layer.

The stack type DRAM of this embodiment is
Also in the following points, the above-mentioned conventional stack type DRAM
Different from (1) The titanium silicide film 26 ₁ , on the surface of the _two N-type high concentration regions 27 ₁ , 27 ₂ of the transistor of the peripheral circuit,
26 ₂ are formed respectively. (2) First silicon oxide films 14 ₁ and 14 ₂ are formed on the gate electrode 15 of the MOS transistor for selection and the gate electrode 16 of the transistor of the peripheral circuit, respectively.

Next, the structure of the stack type DRAM of this embodiment will be described in detail.

The stack type DRAM of this embodiment comprises a selection MOS type transistor, a capacitor section, a peripheral circuit transistor, and a wiring section.

Here, the selection MOS type transistor is
The gate electrode 15 formed on the right side of the P-type silicon substrate 11 in the figure and the gate electrode 15 in the P-type silicon substrate 11
Of the N-type low concentration region 17 ₄ (N-type low-concentration impurity diffusion layer) formed on the right side of the figure and the N-type high concentration region 2 formed on the left side of the gate electrode 15 in the P-type silicon substrate 11 in the figure.
7 ₃ (N-type high-concentration impurity diffusion layer). Note that N
The high-concentration type region 27 ₃ is an N-type low-concentration region 17 formed on the left side of the gate electrode 15 in the P-type silicon substrate 11 in the figure.
Together they are formed in the _3, N-type high concentration region 27 ₃
A titanium silicide film 26 ₃ (silicide of refractory metal) is formed on the surface of the.

The capacitance portion is the second silicon oxide film 1 formed on the gate electrode 15 and the N-type low concentration region 17 _4.
It is formed on the N-type low-concentration region 17 ₄ via 8 (first insulating film). That is, the capacitor portion has the extraction electrode 21 (first accumulation) that is electrically connected to the N-type low concentration region 17 ₄ through the first contact hole formed by opening the second silicon oxide film 18. Electrode), a common electrode 23 made of polycrystalline silicon formed on the extraction electrode 21 via a capacitance film 22 (capacitor insulating film), and a titanium silicide film 26 ₄ formed on the common electrode 23. . The common electrode 23 and the titanium silicide film 26
₄ functions as a second storage electrode having a two-layer structure of a polycrystalline silicon layer and a refractory metal silicide layer.

The transistors of the peripheral circuit are the gate electrode 16 formed on the left side of the figure on the P-type silicon substrate 11,
The N-type low concentration region 17 ₂ and the N-type low concentration region 1 formed on the right side of the gate electrode 16 in the P-type silicon substrate 11 in the figure.
7 ₂ within the N-type high concentration region 27 ₂ , N-type low concentration region 17 ₁ formed on the left side of the gate electrode 16 in the P-type silicon substrate 11 in the drawing, and N type low concentration region 17 ₁ And an N-type high-concentration region 27 ₁ formed therein. Incidentally, titanium silicide films 26 ₁ and 26 ₂ are formed on the surfaces of the N-type high concentration regions 27 ₁ and 27 ₂ .

The wiring portion is composed of selection MOS type transistors.
Titanium silicide film 26_Four And N-type high concentration region 27₃ 
The third silicon oxide film 28 (second insulating film) formed on the
Through a second contact hole formed by opening the film)
N-type high concentration region 27₃ Signal wiring electrically connected to
And the field oxide film 12 on the left side of the drawing₁ , N type high concentration area
Area 27₁ , Gate electrode 16, N-type high concentration region 27₂ And
And field oxide film 12 ₂ Third silicon formed on top
Second contact hole formed by opening the oxide film 28
Through two N-type high-concentration regions 27₁, 27₂And electrically
Two peripheral wirings 30 connected to each other₁, 30₂Including
Mu.

Gate electrode 16 of transistor of peripheral circuit
Also, the first silicon oxide films 14 ₁ and 14 ₂ are formed on the gate electrode 15 of the selection MOS transistor. Peripheral circuit transistor gate electrode 1
6 and the first silicon oxide film 14 ₁ have sidewalls 24 ₁ and 24 ₂ respectively formed on the sidewalls thereof, and the gate electrode 15 of the selection MOS transistor and the first silicon oxide film 14 are formed. _A sidewall 24 ₃ is formed on the N-type high concentration region 27 ₃ side (left side in the drawing) of No. 2.

The three N-type high-concentration regions 27 _{1 to} 27 ₃
Has an impurity concentration of 10 ²⁰ cm ^-3 or more, and the four N-type low concentration regions 17 _{1 to} 17 _{3 have} an impurity concentration of 10 ¹⁹ cm ^-3 or less. The impurity concentration of the polycrystalline silicon layer forming the common electrode 23 is 10 ¹⁸ cm ⁻³ or more.

Next, a method of manufacturing the stack type DRAM shown in FIG. 1 will be described with reference to FIGS.

The field oxide films 12 _{1 to} 12 ₃ are shown in FIG.
As shown in (A), the gate oxide film 1 having a film thickness of 200Å is formed at a predetermined position on the P-type silicon substrate 11.
3 ₁ and 13 ₂ are formed between the field oxide film 12 ₁ and the field oxide film 12 ₂ and between the field oxide film 12 ₂ and the field oxide film 12 ₃ .

Then, polycrystalline silicon having a film thickness of 3000 Å
A film is formed on the P-type silicon substrate 11 by the CVD method.
After that, phosphorus is diffused to form an N-type conductive film. Continued
The 1500 Å thick silicon oxide film is made of polycrystalline silicon.
Formed on the upper surface of the insulating film. Then, the silicon oxide film and
And polycrystalline silicon film are etched by photo etching method
As shown in FIG.
Gate electrode 1 of the MOS transistor for selection which becomes the drain line
5 and the gate electrode 16 of the transistor of the peripheral circuit
Is made. At this time, the gate electrode 16 and the gate electrode
The first silicon oxide film 14 is formed on the upper surface of 15.₁ And the
1 silicon oxide film 14₂ Is left. Then the gate
Electrodes 15 and 16 and field oxide film 12₁~ 12₃And
Energy of 40 KeV and dose of 2 ×
10¹³cm^-2Under the conditions, phosphorus is in the P-type silicon substrate 11
By implanting ions into the N-type low concentration region 17₁
~ 17_FourBut the field oxide film 12₁ And gate electrode 16
Between the gate electrode 16 and the field oxide film 12.₂ With
Field oxide film 12₂ Between the gate electrode 15 and
And the gate electrode 15 and the field oxide film 12₃ Between
It is formed. The gate electrode 15 and the field oxide film
12₃ N-type low concentration region 17 formed between _Four Is an election
Source region or drain of optional MOS transistor
An N-type low-concentration impurity diffusion layer to be a region is formed.

Thereafter, a second silicon oxide film 18 (first insulating film) having a film thickness of 1500 Å is formed on the P-type silicon substrate 11 by the CVD method as shown in FIG. Subsequently, after the first mask material 19 ₁ is applied on the P-type silicon substrate 11, the second silicon oxide film 18 on the low-concentration N-type region 17 ₄ on the right side of the selection MOS type transistor in the figure is photomasked. By etching by the etching method, the contact hole 20 (first contact hole) is formed as shown in FIG. Then, a polycrystalline silicon layer having a film thickness of 3000 Å is formed on the P-type silicon substrate 11 by the CVD method, and then phosphorus-diffused to form an N-type conductive film. Then, this polycrystalline silicon layer is etched into a predetermined pattern by a photoetching method using the _second mask material 19 ₂ .
As shown in FIG. 7B, the extraction electrode 21 (first storage electrode) electrically contacts with the low concentration N-type region 17 ₄ on the right side of the selection MOS transistor through the contact hole 20. Is formed as.

Thereafter, the silicon nitride film having a film thickness of 80 Å is changed to C
After being formed by the VD method, a silicon oxide film having a film thickness of 10 Å is formed on the surface of the silicon nitride film by a heat treatment for 15 minutes in an oxygen atmosphere at 900 ° C. As shown in FIG. A capacitor film 22 (capacitor insulating film) is formed on and around the extraction electrode 21.
Then, a polycrystalline silicon film with a film thickness of 1500 Å is formed by CVD.
Formed by a phosphorous method to form an N-type conductor film of about 2 × 10 ¹⁹ cm ^−3, and then etched into a predetermined pattern by a photo-etching method using the _third mask material 19 ₃ . A common electrode 23 (second storage electrode) is formed on the capacitance film 22 as shown in FIG. The phosphorus concentration of the common electrode 23 is 10 ¹⁸ cm.
^-3 or more, and is set so as to suppress the silicidation reaction with titanium described below and not all the common electrode 23 is silicidized to realize a stable two-layer structure.

Then, using the common electrode 23 and the like as a mask
The second silicon oxide film 18 is anisotropically etched.
As shown in Fig. 4 (A), the
N-type low concentration formed on both sides of the gate electrode 16 of the transistor
Area 17₁, 17₂And the selection MOS type transistor
N-type low concentration region formed on the left side of the gate electrode 15 in the figure
17₃ Is exposed and the sidewall 2
Four₁, 24₂Is the gate electrode 16 of the transistor of the peripheral circuit
And the first silicon oxide film 14 on the gate electrode 16₁ 
Formed on both side walls of the side wall 24₃ Is selected
Electrode and gate of MOS type MOS transistor
First silicon oxide film 14 on electrode 15 ₂ On the left
Formed on the sidewall.

Thereafter, a titanium film 25 having a film thickness of 800 Å is formed,
As shown in FIG. 4B, it is formed on the P-type silicon substrate 11 by the sputtering method. Subsequently, by annealing for 10 minutes in a nitrogen atmosphere at 700 ° C., the three N-type low-concentration regions 17 _{1 to} 17 ₃ which are in direct contact with the titanium film 25.
And by reacting a common electrode 23 over the silicon and the titanium layer 25, by removing the titanium film 25 of unreacted as titanium silicide film 26 _{1-26 4,} shown in FIG. (C), It is formed on the N-type low concentration regions 17 _{1 to} 17 ₃ and the common electrode 23. Next, the gate electrode 16 of the transistor of the peripheral circuit and the three sidewalls 2
4 _{1-24 3} and the field oxide film 12 ₁ of the left side and the field oxide film 12 ₂ of the illustrated central and common electrode 23 as a mask, the energy 70KeV and a dose of 5 × 1
0 ¹⁵ In the conditions of cm ^-2, by arsenic is ion-implanted, the N-type high concentration region 27 _{1-27 3,} as shown in FIG. 5 (A), on both sides of the gate electrode 16 of the transistor of the peripheral circuit Are formed in the N-type low-concentration regions 17 ₁ and 17 ₂ and the N-type low-concentration region 17 ₃ formed on the left side of the gate electrode 15 of the selection MOS transistor in the figure. Note that no N-type high-concentration region is formed in the N-type low-concentration region 17 ₄ formed on the right side of the gate electrode 15 of the selection MOS-type transistor in the figure. Thus, the N-type high-concentration regions 27 ₁ and 27 _{2 serving as} the source region and the drain region of the transistor of the peripheral circuit and the N-type high-concentration region 27 _{3 serving as} the source region or the drain region of the selection MOS transistor are capacitive. Stack DR having the same advantages as those of the trench DRAM by being formed after the formation of the portion
AM can be obtained.

After that, as shown in FIG. 5B, a third silicon oxide film 28 containing phosphorus and boron is formed on the P-type silicon substrate 11, and then in a nitrogen atmosphere at 900 ° C. It is flattened by heat treatment for 10 minutes. Subsequently, contact holes for connecting the signal wiring and contact holes for connecting the peripheral wiring are opened at predetermined positions, and then an aluminum film having a film thickness of 9000Å is formed on the P-type silicon substrate 11 by the sputtering method, and at the same time. The signal wiring 29 and the peripheral wirings 30 ₁ and 30 ₂ are formed by etching into the pattern. As a result, the stack type DRAM is completed.

[0051] In the above-description was stacked DRAM manufacturing method has formed the N-type high concentration region 27 _{1-27 3} after forming the titanium silicide film 26 _{1-26 4,}
May be formed of titanium silicide film 26 _{1-26 4} after forming the N-type high concentration region 27 _{1-27 3.} However, in this case, the respective steps shown in FIGS. 4B to 5A are changed as follows.

As shown in FIG. 4A, after the surfaces of the N-type low concentration regions 17 _{1 to} 17 ₃ are exposed and the sidewalls 24 _{1 to} 24 ₃ are formed, the transistors of the peripheral circuit are formed. Gate electrode 16 and three sidewalls 24
_{1 to} 24 ₃ , the field oxide film 12 ₁ on the left side in the figure, the field oxide film 12 _{2 in the} center in the figure, and the common electrode 23 are used as a mask, and the energy is 70 KeV and the dose amount is 5 × 10 5.
Under conditions of ¹⁵ cm ^-2, by arsenic is ion-implanted, N type high concentration region 27 _{1-27 3,} N-type low-concentration region 17 are formed on both sides of the gate electrode 16 of the transistor of the peripheral circuit ₁ , 17 ₂ and an N-type low-concentration region 17 ₃ formed on the left side of the gate electrode 15 of the selection MOS transistor in the drawing.

Thereafter, a titanium film 25 having a film thickness of 800 Å is formed.
It is formed on the P-type silicon substrate 11 by the sputtering method. Then, by annealing for 10 minutes in a nitrogen atmosphere at 700 ° C., a titanium film 25 and in direct contact with and three N-type high concentration region 27 _{1-27 3} and the common electrode 23 over the silicon and the titanium layer 25 by reacting a, by removing the titanium film 25 of unreacted titanium silicide film 26 _{1-26 4} is formed on the N-type high concentration region 27 _{1-27 3} and the common electrode 23.

Next, the second semiconductor integrated circuit device of the present invention
A method of manufacturing the stack type DRAM which is the embodiment will be described with reference to FIGS. 6 (A) and 6 (B), respectively.

[0055] stacked DRAM of the present embodiment, as shown in FIG. (B), to the upper surface of the gate electrode 16 of the transistor of the peripheral circuit in that the titanium silicide film 26 ₅ is formed, in Fig. 1 This is different from the stack type DRAM of the first embodiment shown. As a result, the stacked DRAM of this embodiment has the gate electrode 16 of the transistor of the peripheral circuit.
Since it is possible to reduce the resistance of the transistor, the transistors in the peripheral circuits can operate at higher speed.

[0056] The manufacturing method of a stacked DRAM of the present embodiment, in order to form a titanium silicide film 26 ₅ to the upper surface of the gate electrode 16 of the transistor of the peripheral circuit, the first that shown in FIG. 2 (B) The formation of the silicon oxide films 14 ₁ and 14 ₂ is unnecessary, and before the formation of the titanium film 25 shown in FIG. 4B, the second gate electrode 16 of the transistor of the peripheral circuit is also exposed. Silicon oxide film 18
Is anisotropically etched (see FIG. 6A), which is different from the method for manufacturing the stacked DRAM of the first embodiment described above.

In the above-described embodiment of the semiconductor integrated circuit device of the present invention, only the N-channel transistor was formed as the transistor of the peripheral circuit. However, an N-type well is formed on the P-type silicon substrate and titanium silicide is formed therein. A P-channel transistor can be formed by forming a film.

[0058]

Since the present invention is configured as described above, it has the following effects.

The invention described in claims 1 to 3 (semiconductor integrated circuit device of the invention) has the following effects. (1) Since the N-type high-concentration region is not formed in the impurity diffusion layer electrically connected to the first storage electrode of the selection MOS type transistor, one of the source region and the drain region of the selection MOS type transistor is The shallow junction can be achieved, the gate length can be shortened, and the memory cell can be miniaturized. (2) Since the second storage electrode has a double structure of polycrystalline silicon and a silicide of a refractory metal, the second storage electrode can have a low resistance, a more stable potential can be supplied, and information of It is possible to improve the margin with respect to the potential variation of the second storage electrode at the time of reading / writing. (3) By siliciding one surface of the source region and the drain region of the selection MOS type transistor, the speed of the selection MOS type transistor can be increased. (4) When transistors for peripheral circuits are formed on the same semiconductor substrate, the source region, drain region, and gate electrode of the transistors are made of a refractory metal silicide, so that the speed of the transistors can be increased.

The invention described in claims 4 and 5 (the method for manufacturing a semiconductor integrated circuit device of the present invention) has the following effects. (1) Since the second storage electrode can have a double structure of polycrystalline silicon and a silicide of a refractory metal, the resistance of the second storage electrode can be reduced and a more stable potential can be supplied.
It is possible to improve the margin for the potential fluctuation of the second storage electrode at the time of reading / writing information. (2) By speeding one surface of the source region and the drain region of the selection MOS transistor, the speed of the selection MOS transistor can be increased. (3) Since the source region and the drain region of the selection MOS type transistor are formed after the formation of the capacitor portion, the heat treatment after the formation of the source region and the drain region of the selection MOS type transistor can be reduced and the gate length can be shortened. The element can be miniaturized. (4) Since the heat treatment after the formation of the refractory metal silicide can be reduced, a stable refractory metal silicide can be formed.

[Brief description of drawings]

FIG. 1 is a diagram showing a vertical structure of a stack type DRAM which is a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a diagram for explaining a manufacturing method of the stack type DRAM shown in FIG.

3A and 3B are views for explaining a method of manufacturing the stack type DRAM shown in FIG.

FIG. 4 is a diagram for explaining a method of manufacturing the stack type DRAM shown in FIG.

5A and 5B are views for explaining a method of manufacturing the stack type DRAM shown in FIG.

FIG. 6 is a diagram for explaining a manufacturing method of the stack type DRAM which is the second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 7 is a diagram for explaining a method of manufacturing a stack type DRAM which is one of the conventional one-transistor type dynamic RAMs.

FIG. 8 is a diagram for explaining a conventional example of a method of manufacturing a stack DRAM that is one of the one-transistor dynamic RAMs.

FIG. 9 is a diagram for explaining a conventional example of a method of manufacturing a trench DRAM, which is one of the one-transistor dynamic RAMs.

FIG. 10 is a graph showing temperature dependence of layer resistance and transistor characteristics of a titanium silicide film, (A) is a graph showing temperature dependence of layer resistance, and (B) is a graph showing temperature dependence of transistor characteristics. is there.

[Explanation of symbols]

11 P-type silicon substrate 12 _{1 to} 12 ₃ field oxide film 13 ₁ and 13 ₂ gate oxide film 14 ₁ and 14 ₂ and 18 and 28 silicon oxide film 15 gate electrode 16 gate electrode 17 _{1 to} 17 ₄ N of transistor of peripheral circuit Low-concentration type region 19 _{1 to} 19 ₃ Mask material 20 Contact hole 21 Extraction electrode 22 Capacitive film 23 Common electrode 24 _{1 to} 24 ₃ Side wall 25 Titanium film 26 _{1 to} 26 ₄ Titanium silicide film 27 _{1 to} 27 ₃ N type high concentration Area 29 Signal wiring 30 ₁ , 30 ₂ Peripheral wiring

Claims (5)

[Claims] 1. A selection MOS having a low-concentration impurity diffusion layer of another conductivity type, a high-concentration impurity diffusion layer of another conductivity type, and a gate electrode formed on a semiconductor substrate of one conductivity type.
-Type transistor, a first insulating film formed on the low-concentration impurity diffusion layer and a gate electrode, and a first contact hole formed by opening the first insulating film, A first storage electrode electrically connected to the concentration impurity diffusion layer, and a polycrystalline silicon layer and a refractory metal silicide layer formed on the first storage electrode via a capacitor insulating film. A second storage electrode having a layered structure, a second insulating film formed on the second storage electrode and on the high-concentration impurity diffusion layer, and formed by opening the second insulating film. A semiconductor integrated circuit including a signal wiring electrically connected to the high-concentration impurity diffusion layer through a second contact hole, and a refractory metal silicide formed on the surface of the high-concentration impurity diffusion layer. Circuit device. 2. The semiconductor integrated circuit according to claim 1, wherein the high concentration impurity diffusion layer has an impurity concentration of 10 ²⁰ cm ⁻³ or more, and the low concentration impurity diffusion layer has an impurity concentration of 10 ¹⁹ cm ⁻³ or less. apparatus. 3. The semiconductor integrated circuit device according to claim 1, wherein an impurity concentration of the polycrystalline silicon layer forming the second storage electrode is 10 ¹⁸ cm ⁻³ or more. 4. A first step of forming a gate electrode of a MOS transistor for selection on a semiconductor substrate of one conductivity type, and a low concentration impurity region of another conductivity type in the semiconductor substrate and the MOS transistor for selection. Second step of forming a low-concentration impurity diffusion layer of another conductivity type, which becomes a source region or a drain region of a transistor of the type, sandwiching the gate electrode, and forming a first insulating film on the semiconductor substrate. A third step; a fourth step of opening the first insulating film to form a first contact hole on the low-concentration impurity diffusion layer; and a step of forming the first contact hole through the first contact hole. A fifth step of forming a first storage electrode electrically connected to the concentration impurity diffusion layer, a sixth step of forming a capacitor insulating film on the first storage electrode, and a step of forming a capacitor insulating film on the first storage electrode. To form the second storage electrode A seventh step of forming a polycrystalline silicon layer according to the above, and anisotropically etching the first insulating film using the polycrystalline silicon layer as a mask to expose the surface of the low concentration impurity region, and An eighth step of leaving the first insulating film on the side wall of the gate electrode on the low-concentration impurity region side, a ninth step of forming a refractory metal layer on the semiconductor substrate, and First, the exposed surface of the concentration impurity region and the surface of the polycrystalline silicon layer are made into a silicide of refractory metal, and then the refractory metal layer is selectively removed.
0, and an eleventh step of forming, in the low-concentration impurity region, the other-conductivity-type high-concentration impurity diffusion layer serving as a drain region or a source region of the selection MOS transistor. Manufacturing method of integrated circuit device. 5. A high-concentration impurity diffusion layer serving as a drain region or a source region of the selection MOS transistor is formed in the low-concentration impurity region in place of the ninth to eleventh steps. 12, a thirteenth step of forming a refractory metal layer on the semiconductor substrate, and a heat treatment to form a refractory metal silicide on the surface of the high-concentration impurity diffusion layer and the surface of the polycrystalline silicon layer. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 4, further comprising a fourteenth step of selectively removing the refractory metal layer.