JP2518359B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a semiconductor memory device capable of improving the reliability of a transistor of a dynamic semiconductor memory having stacked capacitor memory cells. The present invention relates to a manufacturing method of.

[Prior Art] General dynamic semiconductor memory (Dynamic Ran
The circuit configuration of a dom access memory (hereinafter referred to as DRAM) will be described with reference to the block diagram shown in FIG. The DRAM includes a memory cell array 1 configured by arranging a plurality of memory cells for accumulating unit storage information in a matrix. Further, as a peripheral circuit, a row-and-column address buffer 2 which receives an address signal (A _{0 to} A ₉ ) for selecting a memory cell from the outside, and a row decoder for designating a memory cell by decoding the address signal. Three
And a column decoder 4, a sense refresh amplifier 5 for amplifying and reading a signal stored in a designated memory cell, and a data-in buffer 6 for data input / output.
And a data out buffer 7 and a clock generator 8 for generating clock signals φ ₁ and φ ₂ . The clock generator 8 is connected so as to receive a row address strobe signal ▲ ▼ and a column address strobe signal ▲ ▼ from the outside.

FIG. 4 is an equivalent circuit diagram of the memory cells forming the memory cell array 1. The memory cell 9 is composed of one transfer gate transistor 10 and one capacitor 11. The gate electrode of the transfer gate transistor 10 is connected to the word line 12, one of the source / drain regions is connected to the bit line 13, and the other is connected to one electrode of the capacitor 11.

FIG. 5 shows a sectional structural view of the memory cell 9 shown in FIG. Referring to FIG. 5, a thick field oxide film 15 for element isolation is formed on the surface of semiconductor substrate 14.
Further, the transfer gate transistor 10 and the capacitor 11 are formed on the surface of the semiconductor substrate 14 surrounded by the field oxide film 15. The transfer gate transistor 10 includes a gate electrode (word line) 12 formed on a surface of a semiconductor substrate 14 with a gate oxide film 16 interposed therebetween. The periphery of the gate electrode 12 is covered with a silicon oxide film 17 for insulation. In particular, the silicon oxide film 17 formed on the sidewall of the gate electrode 12 constitutes a so-called sidewall structure. Further, the gate electrode 12 is provided in the semiconductor substrate 14.
The low concentration n ^- impurity regions 18a, 18
b is formed. Further, high-concentration n ⁺ impurity regions 19a and 19b are formed in a positional relationship that self-aligns with the sidewalls of the silicon oxide film 17. This n ^- impurity region 18 and n
⁺ So-called LDD (Lightly Doped) due to the impurity region 19
Drain) structure is formed. Then, the impurity regions of this LDD structure become the source / drain regions 18 and 19. The capacitor 11 has a laminated structure of a lower electrode 20 made of polysilicon, a dielectric film 21 made of a laminated film of a silicon nitride film 21a and an oxide film 21b, and an upper electrode 22 made of polysilicon. The capacitor 11 is formed such that the lower electrode 20 extends from the upper portion of the gate electrode 12 of the transfer gate transistor 10 to the upper region of the field oxide film 15.
Further, a part of the lower electrode 20 is connected to one of the n ⁺ source / drain regions 19 of the transfer gate transistor 10. Such a structure in which a part of the capacitor 11 is formed by climbing up to the upper part of the transfer gate transistor 10 or the field oxide film 15 is called a stacked capacitor, and a DRAM including such a capacitor is stacked. It is called a To-type DRAM.

Although not shown in the drawings, the MOS (Metal Oxide Semicondocto) having the LDD structure described above is also used in the peripheral circuits.
r) Transistors are often used.

Here, the effect of the LDD structure of the MOS transistor will be described. The background of the adoption of this LDD structure is the progress of higher integration of DRAM. That is, as DRAM becomes highly integrated, MOS
With the miniaturization of the structure of the transistor, a so-called short channel effect occurs and causes various problems.
That is, the electric field strength in the channel region increases due to the short channel, and hot carriers are generated near the drain, which are trapped in the gate oxide film or generate surface states. As a result, characteristic deterioration such as fluctuation of threshold voltage or reduction of mutual conductance was caused. In order to prevent such characteristic fluctuations due to hot carriers, a low concentration n ^- impurity region and a high concentration n ⁺
An LDD structure has been devised which is formed by offsetting the impurity region. The low-concentration n ^- impurity region of the LDD structure relaxes the junction slope of the pn junction to relax the electric field strength and suppress the generation of hot carriers. Then, it is required to strictly control the diffusion width and the impurity concentration of this low-concentration n ⁻ impurity region.

Next, the manufacturing process of the DRAM will be described with reference to FIGS. 6A to 6H. The manufacturing process of such a DRAM is shown in, for example, Japanese Patent Laid-Open No. 63-44756. In addition,
For convenience of explanation, in this figure, a CMOS transistor (Complementary MOS; hereinafter referred to as CMOS) forming a part of the memory cell 9 and the peripheral circuit is taken up as an example.

First, as shown in FIG. 6A, a field oxide film 15 is formed on the surface of the p-type semiconductor substrate 14 by using the LOCOS (Local Oxide of Silicon) method. In the peripheral circuit region of the semiconductor substrate 14, an n-channel MOS (hereinafter referred to as an nMOS) which constitutes CMOS.
And ap well region 23 and an n well region 24 for forming a p-channel MOS (hereinafter abbreviated as pMOS) are formed.

Next, as shown in FIG. 6B, a thin gate oxide film 25 and a polysilicon layer 26 are sequentially formed on the surface of the semiconductor substrate 14. Further, an oxide film 27 is formed on the surface of the polysilicon layer 26. Then, it is patterned into a predetermined shape using photolithography and etching. As a result, the gate electrode 12 of the nMOS forming the memory cell and the gate electrodes 28a and 28b of the n and pMOS forming the peripheral circuit are formed.

Further, as shown in FIG. 6C, after covering the p.MOS region of the peripheral circuit with a resist 29, low concentration phosphorus (P) ions 30 are ion-implanted on the substrate surface. By this ion implantation step, the n ⁻ impurity regions 18a and 18b of the transfer gate transistor 10 of the memory cell and the n ⁻ impurity region 31 of the nMOS transistor of the peripheral circuit are formed.

After that, as shown in FIG. 6D, after forming the oxide film 34 on the entire surface of the substrate, the oxide film 34 is anisotropically etched. As a result, the gate electrode 12 of the transfer gate transistor 10 and the gate electrode 28 of the nMOS transistor of the peripheral circuit are
A sidewall of the oxide film 34 is formed on the sidewall of a. Then, the side wall of the oxide film 34 is used to ion-implant the n-type impurity ions 30 of high concentration such as phosphorus into the surface of the substrate. Then, by this ion implantation, the n ⁺ impurity regions 19a and 19b of the transfer gate transistor 10 and the n ⁺ impurity region 33 of the nMOS transistor of the peripheral circuit are formed. Through the above steps, the LDD structure of the transfer gate transistor 10 of the memory cell and the LDD structure of the nMOS transistor of the peripheral circuit are formed.

Further, as shown in FIG. 6E, after covering the surface of the nMOS transistor region of the memory cell and the peripheral circuit with a resist 29, p-type impurities such as boron are formed on the substrate surface by using the sidewall of the side wall of the gate electrode 28b. Ions 32 are implanted at a high concentration. This ion implantation step forms the p ⁺ impurity region 35 of the pMOS transistor. Then, the pMOS transistor of the peripheral circuit is formed by the above steps.

Next, in the following, the memory cell capacitor 11
Go to the manufacturing process of. As shown in Fig. 6F, CVD (Chemica) is formed on the substrate surface where the gate electrode of the transistor is formed.
A polysilicon layer is deposited at a temperature of 700 ° C. using the Vapor Deposition method. Then, the lower electrode 20 of the capacitor 11 is formed by patterning this polysilicon layer.

Further, as shown in FIG. 6G, the silicon nitride film 21a is deposited at a temperature of 650 to 750 ° C. by using the CVD method. Further, the surface of the silicon nitride film 21a is oxidized at a temperature of 900 ° C. to form a surface oxide film 21b. Further, a doped polysilicon layer 22 is deposited thereon by using the CVD method. After that, the capacitor 11 is formed by patterning into a predetermined shape using photolithography and etching.

Then, as shown in FIG. 6H, after forming an interlayer insulating film 40 on the surface of the substrate on which elements such as transistors and capacitors are formed, a predetermined region is opened to form a wiring layer 41.

A DRAM including a transistor having an LDD structure is manufactured by the above steps.

[Problems to be Solved by the Invention] As described above, a DRAM including a MOS transistor having an LDD structure and a capacitor is roughly classified into a MOS transistor (FIGS. 6A to 6E) and then a capacitor 11 is formed. (Figs. 6F to 6H). The manufacturing process of the capacitor 11 includes a high temperature thin film deposition process of the lower electrode 20, the upper electrode 22 or the silicon nitride film 21a by the CVD method or the like. Furthermore, the thermal oxidation process of the oxide film 21b formed on the surface of the silicon nitride film 21a is performed at a higher temperature (900 ° C.). Therefore, the MOS transistor of the memory cell or the MOS transistor of the peripheral circuit formed before the manufacturing process of the capacitor 11 is affected by the high temperature. Then, particularly, the impurity regions forming the LDD structure are re-diffused by being affected by the heat at the high temperature. The re-diffusion of the impurity region also progresses in the direction toward the channel region of the transistor, resulting in an increase in gate overlap capacitance and further punch through. Furthermore, since the diffusion rate varies depending on the impurity concentration of the impurity region, the effect of the LDD structure is impaired by changing the offset relationship between the low-concentration impurity region and the high-concentration impurity region forming the LDD structure. Due to such a situation, there arises a problem that the operating speed of the transistor is lowered or the transistor characteristics are changed and the reliability is significantly impaired. As a method of suppressing the re-diffusion of the impurity region, for example, in an n-channel MOS transistor, a method of using arsenic (As) having a lower thermal diffusion rate than phosphorus (P) as impurity ions can be considered. However, compared to phosphorus, arsenic has a more difficult impurity profile shape in the low-concentration impurity region.
There was a problem that the reliability of the D structure was lower than that of phosphorus.

Therefore, the present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor memory device having high reliability by preventing deterioration of the characteristics of an insulated gate field effect element in a manufacturing process. The purpose is to

[Means for Solving the Problems] The present invention is a method for manufacturing a semiconductor memory device having a transistor and a capacitor, wherein a second conductivity type relatively low concentration is formed on a main surface of a first conductivity type semiconductor substrate. Forming a first impurity region, forming a lower electrode layer of the capacitor above the main surface of the semiconductor substrate, and forming a conductive layer on the lower electrode layer with a capacitor dielectric film interposed therebetween. The step of forming an insulating film only on the conductive layer by patterning so as to cover the upper region of the capacitor dielectric film and to have the opening end near the outer periphery of the lower electrode layer, and conducting using the patterned insulating film as a mask Forming the upper electrode layer of the capacitor by patterning the layer, and implanting impurity ions in a state where the insulating film is formed on the upper electrode layer, And a step of forming a second impurity region of the second conductivity type with a relatively high concentration on the main surface of the semiconductor substrate so as to form the source / drain regions in a continuous manner with the object region.

[Operation] In the method for manufacturing a semiconductor memory device of the present invention, the insulating film is formed only on the conductive layer by patterning so as to cover the upper region of the capacitor dielectric film and to have the opening end near the outer periphery of the lower electrode layer. Since the insulating film is used as a mask, the formation of the upper electrode layer and the capacitor dielectric film and the ion implantation for forming the second impurity region are performed, and the film quality of the dielectric film due to the impurity ions is changed. The change can be prevented and the process can be simplified.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view showing a partial sectional structure of a memory cell of a DRAM according to an embodiment of the present invention. According to this example
A DRAM memory cell is composed of one transfer gate transistor 10 and one capacitor 11 connected thereto. Transistor for transfer gate 10
Has a gate electrode (word line) 12 made of a polysilicon layer doped with phosphorus via a gate oxide film 16 on the surface of a p-type semiconductor substrate 14. The gate electrode 12 has a layer thickness
2000 ~ 3000Å, the gate length is 1-1.2μm. Further, the periphery of the gate electrode 12 is covered with the oxide film 34. Also,
A low-concentration n ^- impurity region 18 is formed in the semiconductor substrate 14 so as to be self-aligned with the gate electrode 12, and an oxide film is further formed.
A high-concentration n ⁺ impurity region 19 is formed so as to be self-aligned with 34.

The capacitor 11 has a laminated structure of a lower electrode 20, a silicon nitride film 21a and an oxide film 21b forming a dielectric film, and an upper electrode 22. Further, the formation region thereof has a structure which extends from the upper part of the gate electrode 12 of the transfer gate transistor 10 to the upper part of the field oxide film 15 and rides on it. The lower electrode 20 is formed by depositing an arsenic-implanted polysilicon layer with a film thickness of about 1500 to 3000 Å. A thin oxide film 21b is formed on the surface of the silicon nitride film 21a, and the silicon nitride film 21a is formed to have a film thickness of about 80 to 130Å.
Further, the upper electrode 22 is formed by depositing a polysilicon layer doped with phosphorus to a film thickness of about 1500 to 2500Å.

Furthermore, a CVD oxide film 42 of an insulator, which is a feature of the present invention, is formed on the upper surface of the upper electrode 22 of the capacitor 11. The CVD oxide film 42 is formed in self-alignment with the upper electrode 22 of the capacitor 11. The function of the CVD oxide film 42 will be described in the following description of the manufacturing process.

The DRAM has an LDD structure similar to that of the transfer gate transistor 10 of the memory cell in its peripheral circuit.
It has a channel MOS transistor.

Next, referring to FIGS. 2A to 2I, the DRAM according to the present invention will be described.
The manufacturing process will be described. For convenience of explanation, in this figure, n and
A part of the pMOS transistor is typically illustrated.

In this manufacturing process, the manufacturing process shown in FIGS. 2A to 2C is exactly the same as the process shown in FIGS. 6A to 6C described in the section of the related art, and therefore the description thereof will be given here. Omit it.

Subsequently, as shown in FIG. 2D, after removing the resist 29, a silicon oxide film 34 is deposited on the substrate surface by the CVD method. Further, a resist 29 is applied on the surface of the MOS transistor of the peripheral circuit using photolithography and etching, and the source / drain region on one side not connected to the capacitor 11 of the transfer gate transistor 10 of the memory cell. The resist 29 is left on the impurity region 18a that becomes. Then, the silicon oxide film 34 is etched by anisotropic etching such as reactive ion etching to form sidewalls on the sidewalls of the gate electrode 12. Then, the resist 29 and the silicon oxide film
High-concentration phosphorous ions 30 are ion-implanted on the substrate surface using 34 as a mask. As a result, the high-concentration n ⁺ impurity region 19b of the transfer gate transistor 10 is formed.
Then, the resist 29 is removed.

In the steps so far, in the memory cell region, the LDD structure is formed only in the source / drain impurity region on the side to which the capacitor 11 of the transfer gate transistor 10 is connected. Further, in the peripheral circuit, for example, in the CMOS region, only a low-concentration impurity region is formed. Then, after that, the manufacturing process of the capacitor 11 is performed.

That is, as shown in FIG. 2E, a polysilicon layer is deposited on the entire surface of the substrate by the CVD method. Then, arsenic is implanted into this polysilicon layer (not shown). Alternatively, this step may be substituted by depositing a doped polysilicon layer. After that, patterning is performed using photolithography and etching. As a result, the lower electrode 20 of the capacitor 11 is formed.

Next, as shown in FIG. 2F, a silicon nitride film 21a is deposited by using the CVD method. Further, the surface is kept at a temperature of about 900 ° C and subjected to a thermal oxidation treatment to obtain a surface oxide film.
21b is formed. Further, a doped polysilicon layer 22 is deposited on the surface by the CVD method. Further on
A silicon oxide film 42 is deposited to a film thickness of about 1000 to 1500Å by using the CVD method. Then, a resist 29 is applied thereon and patterned into a predetermined shape by photolithography and etching. Further, using the patterned resist 29 as a mask, the CVD oxide film 42, the doped polysilicon layer 22, the surface oxide film 21b, and the silicon nitride film 21a are sequentially formed.
Is patterned by etching. By this step, the dielectric film 21 and the upper electrode 22 of the capacitor 11, and the CVD oxide film 42 functioning as a protective film of the capacitor 11 are formed.

Further, as shown in FIG. 2G, the silicon oxide film 34 is anisotropically etched by reactive ion etching to form side walls of the gate electrode 12 of the nMOS of the memory cell and the gate electrodes 28a and 28b of the n and pMOS of the peripheral circuit. A side wall is formed. Then, the resist 29 is removed. Then, high-concentration n-type impurity ions such as phosphorus and arsenic are deposited on the entire surface of the substrate.
Is ion-implanted. At this time, the pMOS transistor region of the peripheral circuit is covered with the resist 29. By this ion implantation, the transfer gate transistor 10
An n ⁺ impurity region 19a on one side and an n ⁺ impurity region 33 of the nMOS transistor of the peripheral circuit are formed. In this ion implantation process, the CVD oxide film 42 formed on the capacitor 11 traps the n-type impurity ions 30 in the film, and the n-type impurity ions 30 are trapped in the upper electrode 22 of the capacitor 11 or the dielectric film 21. Are prevented from penetrating. This prevents the dielectric film 21 from being damaged and deteriorating the film quality. Further, the CVD oxide film 42, which is an insulator, also achieves the following effects. That is, when the impurity ions are captured in the CVD oxide film 42, a high electric field is applied to the semiconductor substrate 14 due to the charge-up phenomenon. Then, the CVD oxide film 42 is applied to the capacitor 11 against this high electric field.
And functions as a capacitor connected in series to the dielectric film 21.
However, the film thickness of the CVD oxide film 42 is, for example, 10 times or more thicker than that of the dielectric film 21, so that the ratio of the high electric field to be received by the capacitance division is large. Therefore,
On the contrary, the electric field applied to the dielectric film 21 can be reduced and the dielectric film 21 can be prevented from a high electric field dielectric breakdown.

Further subsequently, as shown in FIG. 2H, this time, the region other than the pMOS transistor region of the peripheral circuit is covered with a resist 29, and high-concentration p-type impurity ions (for example, boron) 32 are ion-implanted. As a result, a high-concentration p ⁺ impurity region 35 of the pMOS transistor of the peripheral circuit is formed. Through the above steps
The manufacturing process of the transistor and capacitor having the LDD structure is completed.

Further, as shown in FIG. 2I, an interlayer insulating film 40 is formed on the surface of the element formed on the substrate. Further, a contact hole is opened in a predetermined region of the interlayer insulating film 40 to form a wiring layer 41. The DRAM is manufactured through the above steps.

Thus, in the peripheral circuit illustrated using the n and pMOS transistors, the high-concentration impurity region of the LDD structure MOS transistor is formed after the manufacturing process of the memory cell capacitor. Therefore, there is no thermal influence due to high temperature such as thermal oxidation treatment when manufacturing the capacitor. This makes it possible to suppress re-diffusion of the impurity region of the LDD structure due to the influence of heat. Therefore, it is possible to manufacture a highly reliable MOS transistor having an LDD structure defined by a predetermined diffusion dimension. This can improve the reliability of the DRAM.

In the above embodiment, the case where the CVD oxide film 42 is used as the insulator formed on the upper electrode 22 of the capacitor 11 has been described, but the present invention is not limited to this. For example, silicon nitride deposited by the CVD method may be used. It may be a film or an oxide film formed by oxidizing the upper electrode 22 of the capacitor 11, and is preferably composed of an amorphous insulator.

Further, in the above-described embodiment, the CMOS transistor configuring the sense refresh amplifier 5 is described as an example of the peripheral circuit, but this is merely an example, and a MOS transistor or other element configuring the peripheral circuit may be used. It is manufactured by the same manufacturing process at the same time.

[Effects of the Invention] As described above, in the method for manufacturing a semiconductor memory device of the present invention, patterning is performed so as to cover the upper region of the capacitor dielectric film and to have the opening end near the outer periphery of the lower electrode layer. Since the method includes the step of forming the insulating film only on the conductive layer, the upper electrode layer and the capacitor dielectric film are formed using the insulating film as a mask, and ion implantation for forming the second impurity region is performed. This prevents the film quality of the dielectric film from being changed by the impurity ions, improving the reliability of the device and simplifying the process.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a DRAM memory cell according to an embodiment of the present invention. 2A, 2B, 2C, 2D,
FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H and FIG. 2I are sectional views showing the manufacturing steps in order for the memory cell and a part of the peripheral circuit of the DRAM according to the embodiment of the present invention. Is. FIG. 3 is a block diagram for explaining a general configuration of DRAM. FIG. 4 is an equivalent circuit diagram of a general DRAM memory cell. FIG. 5 is a cross-sectional structural view of a conventional DRAM memory cell. 6A, 6B, 6C, 6D,
6E, 6F, 6G and 6H are manufacturing process sectional views showing a part of the memory cell and the peripheral circuit in order of the manufacturing process in order to show the manufacturing process of the conventional DRAM. In the figure, 9 is a memory cell, 10 is a transfer gate transistor, 12 is a gate electrode (word line), 18a, 18
b is the n ^- impurity region of the transfer gate transistor 10, and 19a and 19b are the n of the transfer gate transistor 10.
⁺ Impurity region, 20 lower electrode of capacitor, 21 dielectric film, 21a silicon nitride film, 21b surface oxide film, 22 upper electrode, 28a and 28b n and pMOS gate electrodes of peripheral circuit, 31 N ^- impurity region of nMOS transistor of peripheral circuit,
33 is the n ⁺ impurity region of the peripheral circuit nMOS transistor, 35 is the p ⁺ impurity region of the peripheral circuit pMOS transistor, and 42 is the CVD
The oxide film is shown. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koki Okumura 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture Mitsubishi Electric Corp. LSI Research Laboratory (72) Inventor Hideki Genjo 4-Mizuhara, Itami-shi, Hyogo Prefecture No. 1 Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Atsushi Hachisuka 4-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LS Research Laboratory (56) References 1-80068 (JP, A)

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device having a transistor and a capacitor, wherein a second conductivity type relatively low concentration first impurity region is formed on a main surface of a first conductivity type semiconductor substrate. A step of forming a lower electrode layer of the capacitor above the main surface of the semiconductor substrate, a step of forming a conductive layer on the lower electrode layer with a capacitor dielectric film interposed therebetween, the capacitor dielectric film Forming an insulating film only on the conductive layer so as to cover the upper region of the lower electrode layer and to have an opening end near the outer periphery of the lower electrode layer; and the conductive layer using the patterned insulating film as a mask. Forming an upper electrode layer of the capacitor by patterning, and implanting impurity ions in a state where the insulating film is formed on the upper electrode layer. Therefore, a step of forming a second high-concentration second impurity region of the second conductivity type on the main surface of the semiconductor substrate so as to form a source / drain region connected to the first impurity region, Manufacturing method of semiconductor memory device.